Abstract: An interactive test equipment for quality evaluation of resistance value test for electric leakage is disposed on a platform, and includes at least a control unit, a leaking electric current control module and an operating module. The leaking electric current control module includes at least a test set for quality evaluation to determine a resistance value for electric leakage. Each of the at least a test set has a circuit breaker and an electric leakage value display. The electric leakage value display of the each of the at least a test set can be used to display tripping circuit-breaking data of a corresponding circuit breaker. Test subjects can initiate the interactive test equipment and select answers through the operating module, and load questions and determine answers through the control unit.

Abstract: Embodiments of the present invention provide systems and methods for storing calibration data for a test system operable to test a device under test (DUT). The test system includes one or more channel modules and a device interface. A first part of the calibration data is stored on a non-volatile memory. The non-volatile memory can be disposed in different parts of the test system. The non-volatile memory is located on the device interface and can also be located on one or more of the channel modules, as well as an attachment of the test system. The non-volatile memory is associated with the one or more channel modules. The second part of the calibration data is stored on a non-volatile memory associated with the device-under-test interface.

Abstract: A hand-held ultrasound device, for placement on a subject, includes a semiconductor device and a housing to support the semiconductor device. The semiconductor device includes: a plurality of ultrasonic transducer elements; a plurality of pulsers coupled to the plurality of ultrasonic transducer elements; a plurality of waveform generators configured to drive the plurality of pulsers; receive processing circuitry configured to process ultrasound signals received by the plurality of ultrasonic transducer elements; and a plurality of independently controllable registers configured to store a plurality of different parameters for the waveform generators.

Abstract: A method includes receiving, by a computing system, a declarative testing descriptor for active testing of a network slice implemented by first virtualized services in a network; receiving, by the computing system and from an orchestration layer, metadata associated with the network slice; determining, by the computing system and based on the declarative testing description and the metadata, active testing configuration for testing the network slice; and starting an active test according to the active testing configuration and determining service level violations based on a result of the active test.

Abstract: A system, method, and device to test an electronic circuit are disclosed having a stage to supply a driving signal to a load comprising a pull-up switch and a pull-down switch and a pre-driver stage including pre-driver circuits. The electronic circuit including circuits for testing the pre-driver stage under the control of an automatic testing equipment (ATE) to operate a built-in self-test sequence including test commands for the pre-driver stage under the control of an external test signal issued by the ATE. The system includes a time measuring circuit to measure duration of signals at the output of the stage coupled to a pass-fail check circuit, and to evaluate if the duration of signals at the output of the stage to determine whether the output satisfies a pass criterion.

Abstract: An information processing device converts a plurality of original data arranged on a preset n-dimensional map into a plurality of new data arranged on a map according to a conversion rule. In the conversion rule, when an original datum at a target position on the map has a value of out-of-criterion, a new datum at the target position is set to the value of the original datum at the target position, and when the original datum at the target position has a value of within-criterion, each of values of one or more original data excluding an original datum having a value of the out-of-criterion from original data included in a reference region is selected to perform majority voting with the values of the one or more original data selected, and the new datum at the target position is set to a value determined by the majority voting.

Abstract: Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

Abstract: A semiconductor wafer and a multi-chip parallel testing method are provided. The semiconductor wafer includes a plurality of chips, a plurality of test pads, and a test control circuit. The test pads receive a plurality of test signals from a test fixture. The test control circuit is electrically connected to the chips and the test pads, selects at least one selected test signal from the test signals, generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the broadcast test signals to the chips in parallel.

Abstract: Systems and methods are disclosed for configuring a communication network to satisfy a set of demands. A network management system can obtain a network graph representing the communication network, connectivity relationship that indicates valid pairs of edges for each vertex in the network graph, and a structure that lacks zero divisors. The network management system can use the network graph, connectivity relationship, and structure to determine a path length for which a valid path connecting a source vertex and a terminal vertex exists. The path length can be determined using a dynamic programming approach that associates an element of the structure with the collection of paths connecting the source vertex and the terminal vertex. The network management system can then use the network graph, connectivity relationship, and structure to determine a valid path of the path length that connects the source vertex and the terminal vertex.

Abstract: A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

Abstract: A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: Systems, apparatuses, and methods for test devices having parallel impedances to reduce measurement input impedance are disclosed. An apparatus includes a test input terminal, a measurement output terminal, a reference voltage potential node, and a parallel resistor. The test input terminal is configured to electrically connect to a signal output terminal of a signal generator. The test input terminal is configured to receive a test signal from the signal generator via the signal output terminal. The measurement output terminal electrically connects to a measurement input terminal of an electrical measurement instrument. The parallel resistor is electrically connected from the measurement output terminal to the reference voltage potential node. A system includes the apparatus and the electrical measurement instrument. A method includes providing a test signal to the test device, verifying the test signal using the electrical measurement instrument, and providing the test signal to a device under test.

Abstract: A method, and a Solid-State Drive (SSD) memory device and a system for assessing operational effectiveness of the SSD is provided. Upon a failure of the SSD memory device, a command is executed which is received from a host device. The SSD memory device switches to an operational state after executing the command. A data structure having SSD operational parameters is obtained from a plurality of data structures obtained before the failure and stored in a Read Only Memory (ROM) upon the SSD memory device switching to the operational state. The obtained data structure is restored into a Random-Access Memory (RAM).

Abstract: Large and complex software projects may be distributed over multiple repositories and may use test automation of equivalent scale in continuous integration frameworks to maintain quality of the project. Such test automation often has significant hardware and time costs to run, which may mean that a failure of the software in the test automation takes longer to detect. Delay in fixing the software may increase the chance of more failures getting checked into the software repositories and perpetuating software failures. To address this issue, a ranking of historical test data is determined based on a number of failures for each test and a test configuration is determined based on the ranking such that tests that are ranked higher are performed before tests that are ranked lower. The test may be exited upon detection of failure instead of continuing.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

Abstract: A burn-in board includes: a board; a socket mounted on the board; a connector attached to the board; a wiring system that is disposed in the board and that connects the socket and the connector; and a compensation circuit that connects to the wiring system and that compensates a frequency characteristic of a signal transmitted through the wiring system.

Abstract: Systems and methods are provided for dynamic segmentation of users during an experiment based on changes to application data collected during the experiment. Data regarding application interactions and associated application metadata may be collected from users during application experiments that involve testing different variants of a feature or otherwise different user experiences. The data regarding application interactions and associated application metadata may be evaluated to discover segments of users and/or usage patterns (e.g., “cohorts”). During the experiment, the users may be dynamically re-segmented into new/different cohorts based on new application data being collected.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: A method for real-time processing of a detection signal, wherein signal processing is respectively performed when a detection signal is converted from a high level to a low level or vice versa. A moment at which a level of the detection signal is converted is recorded as a start point. A status of the detection signal is then detected in real time at a current moment. A current time width is compared to a maximum interval width of pre-set interference signals, and signal levels are determined and recorded from the start point to the current moment. Using characteristics of different interference signals, anti-interference processing is performed by using a targeted edge positioning and width recognition method, so that the delay impact of filtering on signals is avoided, improving both the recognition precision of weighing data of a checkweigher and the overall performance of the checkweigher.

Abstract: One aspect provides a method and system for saturation of multiple I/O slots by multiple testing ports and verification of link health in between. During operation, the system detects a testing card with a plurality of test ports which are coupled to a plurality of input/output (I/O) slots of a computing device. The system communicates with the plurality of test ports via the plurality of I/O slots. The system generates, by the computing device, a script for each test port, wherein the script comprises a series of read and write operations to be executed by the testing card on a memory device associated with the computing device. The system allows the plurality of test ports to execute the script and perform the corresponding read operations and write operations, thereby facilitating testing of the I/O slots of the computing device in parallel by the test ports of the single testing card.

Abstract: Methods for detecting a glitch at a high sampling rate are provided. In some embodiments, a method includes the following steps: S1, acquiring to-be-identified data; S2, processing the to-be-identified data to obtain normal sampling data; and S3, performing glitch identification on the to-be-identified data to obtain a glitch position of the normal sampling data. In other embodiments, the disclosure provides a system for detecting a glitch at a high sampling rate and for implementing the method for detecting a glitch at a high sampling rate. The system includes an acquisition unit and a glitch identification unit. The acquisition unit acquires and processes the to-be-identified data to obtain the normal sampling data, and the glitch identification unit performs glitch identification on the to-be-identified data to obtain the glitch position of the normal sampling data.

Abstract: A device for detecting railway equipment defects, comprising at least three diagnostic modules mounted on a generic railway vehicle: a first module (geometrical module) configured to measure at least a geometrical feature of the track; a second module (acceleration module) configured to measure in at least a point of said vehicle the side and/or vertical accelerations transmitted from the track to said vehicle; a third module (visual module) configured to acquire the images of the track elements and to analyze them to verify the presence of anomalies; said modules being configured to associate with each detection carried out when the railway vehicle passes, on which they are mounted, the position where the detection was carried out and to calculate, for each detection, a severity index representative of the deviation of the detection with respect to the standard condition without defects.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: A boundary scan test method is used to test connectivity of a pad having a direct connection to user logic. The method comprises the following steps: configuring an FPGA to enter a test mode; generating by means of user logic, a boundary scan chain for a boundary scan test; loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a pad to be tested for connectivity; sending, via a TDI port, a first test vector to the pad; performing the boundary scan test, and loading an EXTEST instruction to the device having the pad; and removing first response data from a TDO port, and performing response analysis and fault diagnosis.

Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.

Abstract: An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.

Abstract: Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

Abstract: Systems and methods may ethically evaluate intelligent systems operating in a real-world environment. The systems and methods may generate a clone of the intelligent system, and test the clone in a simulation environment. If the clone passes the testing, the systems and methods may permit the intelligent system to continue operating in the real-world environment. If the clone fails the testing, the systems and methods may override the intelligent system, such as disabling the intelligent system and assuming control in the real-world environment. The systems and methods may be implemented at a hardware level of a data processing device to prevent interference with the systems and methods by the intelligent system.

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed.

Abstract: Embodiments described herein generally relate to analyzing a signal generated by a device under test (DUT). In particular, the signal generated by the DUT may be compared to a reference signal to determine pass/fail results for the DUT. For example, a method may include: storing, on a computing device, a reference signal from a reference device; receiving a test signal from a device under test (DUT); synchronizing the reference signal and the test signal based on a time-synchronization buffer of each signal; after the synchronization, comparing the test signal and the reference signal to determine a pass or fail result for the DUT; and generating a notification indicating the pass or fail result for the DUT.

Abstract: Phased parameterized combinatoric testing for a data storage system is disclosed. A testing recipe can be performed according to different input arguments. Combinatoric testing of the data storage system can be based on different combinations of operations and arguments. The disclosed testing can employ a consistent integer index for arguments passed into the sequenced operations of the recipe. The recipe can be employed to generate a phased test tree that can enable testing based on a phase rather than loading an entire test suite into memory. The consistent integer index can be used to identify failed test cases such that the entire test can be reconstituted from stored failed test information. Distribution of test cases to worker process can based on the phased test tree to facilitate interning an operation. Stored failed test information can include human-readable failure information.

Abstract: Adaptive automated testing methods and systems are disclosed. In an embodiment, an automatic test controller of an automated test system may collect a log of a plurality of actions executed by a plurality of devices of the automated test system and apply a heuristic to the log as the automated test system operates to determine whether to execute a next action by a device of the automated test system. When the next action is to be executed, the automatic test controller automatically directs the device to execute the next action. Otherwise, the automatic test controller indicates the next action was intentionally skipped by recording such omission in the log and automatically skipping the next action.

Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

Abstract: Disclosed are various implementations of approaches for continuous delivery of management configurations. In some examples, a management configuration delivery workflow is retrieved from a source environment. The management configuration is transmitted to a destination environment specified in the management configuration delivery workflow. The destination environment us updated to apply the management configuration.

Abstract: A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.

Abstract: Apparatuses and methods for identifying network anomalies. A method includes determining a cumulative anomaly score over a predefined time range based on a subset of historical PM samples and determining an anomaly ratio of a first time window and a second time window, based on the cumulative anomaly score. The method also includes determining one or more anomaly events coinciding with CM parameter changes based on the anomaly ratio; collating the PM, alarm, and CM data into a combined data set based on matching fields and timestamps; generating a set of rules linking one or more CM parameter changes and the collated data to anomaly events; and generating root cause explanations for CM parameter changes that are linked to anomaly events.

Abstract: A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.