Abstract: A method for real-time processing of a detection signal, wherein signal processing is respectively performed when a detection signal is converted from a high level to a low level or vice versa. A moment at which a level of the detection signal is converted is recorded as a start point. A status of the detection signal is then detected in real time at a current moment. A current time width is compared to a maximum interval width of pre-set interference signals, and signal levels are determined and recorded from the start point to the current moment. Using characteristics of different interference signals, anti-interference processing is performed by using a targeted edge positioning and width recognition method, so that the delay impact of filtering on signals is avoided, improving both the recognition precision of weighing data of a checkweigher and the overall performance of the checkweigher.

Abstract: Methods for detecting a glitch at a high sampling rate are provided. In some embodiments, a method includes the following steps: S1, acquiring to-be-identified data; S2, processing the to-be-identified data to obtain normal sampling data; and S3, performing glitch identification on the to-be-identified data to obtain a glitch position of the normal sampling data. In other embodiments, the disclosure provides a system for detecting a glitch at a high sampling rate and for implementing the method for detecting a glitch at a high sampling rate. The system includes an acquisition unit and a glitch identification unit. The acquisition unit acquires and processes the to-be-identified data to obtain the normal sampling data, and the glitch identification unit performs glitch identification on the to-be-identified data to obtain the glitch position of the normal sampling data.

Abstract: One aspect provides a method and system for saturation of multiple I/O slots by multiple testing ports and verification of link health in between. During operation, the system detects a testing card with a plurality of test ports which are coupled to a plurality of input/output (I/O) slots of a computing device. The system communicates with the plurality of test ports via the plurality of I/O slots. The system generates, by the computing device, a script for each test port, wherein the script comprises a series of read and write operations to be executed by the testing card on a memory device associated with the computing device. The system allows the plurality of test ports to execute the script and perform the corresponding read operations and write operations, thereby facilitating testing of the I/O slots of the computing device in parallel by the test ports of the single testing card.

Abstract: A device for detecting railway equipment defects, comprising at least three diagnostic modules mounted on a generic railway vehicle: a first module (geometrical module) configured to measure at least a geometrical feature of the track; a second module (acceleration module) configured to measure in at least a point of said vehicle the side and/or vertical accelerations transmitted from the track to said vehicle; a third module (visual module) configured to acquire the images of the track elements and to analyze them to verify the presence of anomalies; said modules being configured to associate with each detection carried out when the railway vehicle passes, on which they are mounted, the position where the detection was carried out and to calculate, for each detection, a severity index representative of the deviation of the detection with respect to the standard condition without defects.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: A boundary scan test method is used to test connectivity of a pad having a direct connection to user logic. The method comprises the following steps: configuring an FPGA to enter a test mode; generating by means of user logic, a boundary scan chain for a boundary scan test; loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a pad to be tested for connectivity; sending, via a TDI port, a first test vector to the pad; performing the boundary scan test, and loading an EXTEST instruction to the device having the pad; and removing first response data from a TDO port, and performing response analysis and fault diagnosis.

Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.

Abstract: An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: A non-volatile memory combines a hard bit and a soft bit read into a single, efficient soft sense sequence by using two sense per state level to improve read time efficiency. Rather than a standard hard bit read, where two soft bit reads are performed, offset above and below the hard bit read value, the hard bit read is shifted so that it reliable senses one state but less reliably senses the other state and soft bit data is only determined for the less reliably sensed state. This reduces the amount of soft bit data. The efficient soft sense sequence can be used as a default read mode, providing soft bit information for ECC correction without triggering a read error handling flow. Merging the soft bit and hard bit sense into one sequence can avoid extra overhead for read sequence operations.

Abstract: Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations.

Abstract: Systems and methods may ethically evaluate intelligent systems operating in a real-world environment. The systems and methods may generate a clone of the intelligent system, and test the clone in a simulation environment. If the clone passes the testing, the systems and methods may permit the intelligent system to continue operating in the real-world environment. If the clone fails the testing, the systems and methods may override the intelligent system, such as disabling the intelligent system and assuming control in the real-world environment. The systems and methods may be implemented at a hardware level of a data processing device to prevent interference with the systems and methods by the intelligent system.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed.

Abstract: Adaptive automated testing methods and systems are disclosed. In an embodiment, an automatic test controller of an automated test system may collect a log of a plurality of actions executed by a plurality of devices of the automated test system and apply a heuristic to the log as the automated test system operates to determine whether to execute a next action by a device of the automated test system. When the next action is to be executed, the automatic test controller automatically directs the device to execute the next action. Otherwise, the automatic test controller indicates the next action was intentionally skipped by recording such omission in the log and automatically skipping the next action.

Abstract: Phased parameterized combinatoric testing for a data storage system is disclosed. A testing recipe can be performed according to different input arguments. Combinatoric testing of the data storage system can be based on different combinations of operations and arguments. The disclosed testing can employ a consistent integer index for arguments passed into the sequenced operations of the recipe. The recipe can be employed to generate a phased test tree that can enable testing based on a phase rather than loading an entire test suite into memory. The consistent integer index can be used to identify failed test cases such that the entire test can be reconstituted from stored failed test information. Distribution of test cases to worker process can based on the phased test tree to facilitate interning an operation. Stored failed test information can include human-readable failure information.

Abstract: Embodiments described herein generally relate to analyzing a signal generated by a device under test (DUT). In particular, the signal generated by the DUT may be compared to a reference signal to determine pass/fail results for the DUT. For example, a method may include: storing, on a computing device, a reference signal from a reference device; receiving a test signal from a device under test (DUT); synchronizing the reference signal and the test signal based on a time-synchronization buffer of each signal; after the synchronization, comparing the test signal and the reference signal to determine a pass or fail result for the DUT; and generating a notification indicating the pass or fail result for the DUT.

Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

Abstract: A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.

Abstract: Disclosed are various implementations of approaches for continuous delivery of management configurations. In some examples, a management configuration delivery workflow is retrieved from a source environment. The management configuration is transmitted to a destination environment specified in the management configuration delivery workflow. The destination environment us updated to apply the management configuration.

Abstract: Apparatuses and methods for identifying network anomalies. A method includes determining a cumulative anomaly score over a predefined time range based on a subset of historical PM samples and determining an anomaly ratio of a first time window and a second time window, based on the cumulative anomaly score. The method also includes determining one or more anomaly events coinciding with CM parameter changes based on the anomaly ratio; collating the PM, alarm, and CM data into a combined data set based on matching fields and timestamps; generating a set of rules linking one or more CM parameter changes and the collated data to anomaly events; and generating root cause explanations for CM parameter changes that are linked to anomaly events.

Abstract: A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Abstract: A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.

Abstract: An electronic device includes a processing unit with a memory, a JTAG interface with test-data-input and test-mode-select lines coupled to the processing unit, a bridge circuit, and a multiplexer circuit. The bridge circuit includes a serial communication interface receiving a serial data input signal which conveys an input serial data frame. The bridge circuit includes a serial-to-parallel converter circuit block receiving the input serial data frame, processing the input serial data frame to read first and second subsets of input binary values therefrom, and transmitting the first subset via a first output signal and the second subset via a second output signal. The multiplexer circuit selectively propagates a received test-data-input signal or the first output signal to the test data input line, and selectively propagates a test-mode-select signal or the second output signal to the test mode select line of the JTAG interface.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: A method for secure usage of cryptographic material in networked system components provided with the cryptographic material in which a lifecycle of every system component includes at least one development phase and one production phase. The entire cryptographic material is at least directly securely marked as development or production material. Each system component has a binary state flag showing which phase the system component is in and which is secured against unauthorized manipulation. Each system component determines via an assessment function which phase it is in, according to which each system component carries out a check, during which the current phase and the marker of the cryptographic material are compared. Security measures are introduced if there is no agreement between the phase and the marker.

Abstract: A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Abstract: An information processing apparatus includes an acquisition unit, a power supply unit, and a controller. The acquisition unit acquires failure information for the information processing apparatus via a wireless communication line from a management apparatus holding failure information. The power supply unit supplies power to the acquisition unit when the main power supply is not on. The controller exerts control in such a manner that, when the acquisition unit acquires the failure information from the management apparatus in the state in which the main power supply is not on, only a subset of functions of the apparatus are activated by supplying power from the power supply unit, and a process for limiting use of a function related to the failure is performed.

Abstract: The present disclosure provides a method and a device for determining a root cause of fault, a server and a computer-readable medium. The method for determining a root cause of fault includes: determining fault characteristic information when a fault occurs in a service, and determining a fault root cause node according to the fault characteristic information and a preset fault propagation graph, the fault propagation graph is configured to represent directed association relationships among different fault propagation nodes, and directed association relationships among a fault node, the fault propagation nodes and fault root cause nodes, and the nodes in the fault propagation graph are configured to represent the fault characteristic information.

Abstract: An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.

Abstract: Computer-implemented systems and methods for automatically generating an electronic circuit IP block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints, including time constraints. Exemplary systems and methods may include an electronic circuit layout generator and/or IP generator to obtain manufacturing processes and design rules from an external source, define a type of electronic circuit to be fabricated, prepare a circuit schematic of the defined electronic circuit, and generate an IP block for the defined electronic circuit based on the circuit schematic. A computer program generator is provided to create the defined electronic circuit. A computer readable storage medium contains processing instructions for obtaining the manufacturing processes and design rules and for fabricating the electronic circuit.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.

Abstract: An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.

Abstract: The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

Abstract: In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.