Digital Logic Testing Patents (Class 714/724)
  • Patent number: 10929273
    Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 23, 2021
    Assignee: HITACHI, LTD.
    Inventors: Toru Motoya, Masahiro Shiraishi, Satoshi Nishikawa, Keisuke Yamamoto, Tadanobu Toba, Takumi Uezono, Hideo Harada, Yusuke Kanno
  • Patent number: 10922150
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system comprising at least one processor, a management controller communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system, a debugging circuit, and a logic device coupled to the host system and to the management controller. The logic device may be configured to determine that a trigger event has taken place, and in response to the trigger event, provide a serial data stream corresponding to the trigger event to the debugging circuit. The debugging circuit may be configured to provide access to the serial data stream to a debugging information handling system via a wireless interface.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 16, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jeffrey Kennedy
  • Patent number: 10903641
    Abstract: A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 26, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Jan Roelof Westra, Jan Mulder
  • Patent number: 10895598
    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 19, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10890619
    Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma
  • Patent number: 10886001
    Abstract: A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product includes a pattern memory that stores a part of the test pattern. The pattern memory is rewritten during a time when the semiconductor product is tested by a part of the test pattern stored in the pattern memory included in the semiconductor-product testing device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Yamada, Yoshiyuki Matsumoto, Kazuhiro Nishimura
  • Patent number: 10845408
    Abstract: A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. The wafer burn-in test circuit may include a wafer burn-in signal decoding unit configured to generate a plurality of decoding signals by decoding the plurality of timing-compensated input signals and output the plurality of decoding signals as a plurality of wafer burn-in signals by latching the plurality of decoding signals.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Jae Choi
  • Patent number: 10831639
    Abstract: A method and a device for non-intrusively collecting function trace data of a software application running on a processor-core, comprising translating a source code of the software application which comprises traceable function source code into executable code. The steps to execute the executable code include allocating the executable code of the traceable function within at least one pre-defined code memory region, checking each function call or jump instruction for its target address, and if the target address is located within the pre-defined code memory region, logging the execution of the traceable function.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 10, 2020
    Assignee: Gliwa GmbH Embedded Systems
    Inventor: Peter Gliwa
  • Patent number: 10823781
    Abstract: Embodiments are directed to apparatuses and methods for providing a logic built-in self-test (LBIST) using an LBIST logic circuit and an auxiliary logic circuit. An example method includes using switch circuitry in an integrated circuit (IC) to change modes of operation associated with functional logic circuit, the modes of operation including an LBIST mode and an application mode, and to provide an internally generated digital clock signal to the functional logic circuitry and an LBIST logic circuit in response to the LBIST mode. The method further includes performing an LBIST using the internally generated digital clock signal, the LBIST logic circuit to test select nodes in the IC via control of the functional logic circuitry and via application of digital logic sequences provided as inputs to the I/O pad cells of the IC.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 10810338
    Abstract: A method and a device for generating boundary-scan interconnection lines are disclosed. In the method, the boundary scan test model is established according to boundary scan components and intermediate components on least one test card and a unit under test (UUT) board, and connection relationships therebetween; the boundary scan nets of the boundary scan test model are constructed; the boundary scan paths of each boundary scan net are generated, and a path establishment condition of each boundary scan path is obtained; and the boundary scan paths are filtered and integrated, and the filtered and integrated boundary scan paths are divided according to the path establishment conditions of filtered and integrated boundary scan paths, into subtests which each has at least one boundary-scan interconnection line. As a result, the accuracy and high coverage of a path search operation can be guaranteed.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 20, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Chang-Qing Mu
  • Patent number: 10794955
    Abstract: A method of testing a tester, comprising testing electronic units using a plurality of sites in order to obtain first bin assignment, instructing the tester to perform a tester quality test if conditions CiQA,1 and CiQA,2 are met, the tester quality test comprising performing a second plurality of tests on an electronic unit using a first site, thereby obtaining second bin assignment for the electronic unit, the second bin assignment being representative of passing or failing of the electronic unit of the second plurality of tests with respect to at least one second test criteria, wherein CiQA,1 is met if passing first bin assignment has been obtained for said electronic unit connected to the tester using the first site, and wherein CiQA,2 is met if data representative of passing first bin assignment obtained for electronic units which have been tested on the first site, meets a quality criteria.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 6, 2020
    Assignee: OPTIMAL PLUS LTD
    Inventors: Hagay Gur, Dan Glotter, Shaul Teplinsky
  • Patent number: 10763836
    Abstract: Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Yi Kuo, Ying-Yen Chen, Wen-Hsuan Hsu
  • Patent number: 10740515
    Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jagjot Kaur, Priyanka Dasgupta, Vivek Chickermane, Gopi Kudva
  • Patent number: 10698029
    Abstract: A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 30, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Sheng-Ping Yung, Pei-Ying Hsueh, Chun-Yi Kuo
  • Patent number: 10690722
    Abstract: Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed “glitch”) before settling to a final value consistent with the input values being applied to said logic circuit.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 23, 2020
    Assignee: Real Intent, Inc.
    Inventor: Pranav Ashar
  • Patent number: 10665288
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Patent number: 10657893
    Abstract: The present application discloses a display device and a driving method thereof using the SSD method capable of charge with the data voltage in the pixel circuit and sufficient internal compensation even if the high resolution of a display image is improved. m demultiplexers corresponding to m sets of data signal line groups with k data signal lines being one set are provided. Each demultiplexer sets a prescribed period in a period after a time point when to start supplying a data signal output last in each of horizontal intervals among m data signals to a time point before a time point when to end supplying the data signal is set in advance as a delay period, and a scanning line drive circuit starts to select a scanning line corresponding to the pixel circuit to which the prescribed number of data signals are supplied, when the delay period of each of the horizontal intervals ends.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Mitani, Fumiyuki Kobayashi, Makoto Yokoyama
  • Patent number: 10651519
    Abstract: The battery pack includes a base having a heat dissipation wall, a switching device for controlling current having a plurality of electrode terminals, being disposed so as to be capable of transferring released heat to the heat dissipation wall, and a bus bar having a connection terminal that is connected to the switching device or a unit cell so as to enable energization. The connection terminal is disposed so as to be positioned in an area corresponding to a width of the switching device in a direction in which the electrode terminals are arranged in line and in an area extending to a periphery of the switching device in a direction orthogonal to the direction in which the electrode terminals are arranged in line.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 12, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yoshimitsu Inoue, Takahiro Jo, Hidemitsu Watanabe
  • Patent number: 10649032
    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10634721
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 28, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10637447
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 28, 2020
    Inventors: Alok Kumar Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal
  • Patent number: 10634709
    Abstract: A diagnostic having an analog-to-digital converter that is electrically coupled to an output port of a first analog multiplexer and an output port of a second analog multiplexer is provided. The analog-to-digital converter receives the high side voltage level signal and the low side current level signal at first and second times, respectively, and outputs a high side voltage value and a low side current value, respectively, based on the high side voltage level signal and the low side current level signal, respectively, that are received by a microcontroller. The microcontroller commands a high side driver circuit and a low side driver circuit to transition a contact of the contactor to an open operational position when the first analog multiplexer is malfunctioning based on the high side voltage value.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: April 28, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Kerfegar K. Katrak, Sagar V. Nagaluru, Thaddeus Steyskal, Su Hyuk Jang, Kunal Tipnis
  • Patent number: 10622345
    Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 14, 2020
    Assignee: Honeywell International Inc.
    Inventor: James L. Tucker
  • Patent number: 10613952
    Abstract: Embodiments provide multi-port communications switches with automated flip emulation for multi-orientation data connectors, for example, to test data connector system components. One embodiment includes multiple ports, each with pins adapted to electrically couple with corresponding structures of a data connector when the connector is physically coupled with the port in any of multiple connector orientations. A flip controller couples pins of first and second ports in accordance with a selected configuration, such that: in a first mode, the flip controller effectively emulates the coupled ports being in a same connector orientation; and in a second mode, the flip controller effectively emulates the coupled ports being in different orientations (e.g., as if one of the connectors is flipped over).
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Acroname, Inc.
    Inventors: Justin Lawrence Gregg, Matthew Joseph Krugman, Lance Chapin Davies, Jeremiah Reece Sullenger
  • Patent number: 10607537
    Abstract: What is disclosed are systems and methods of optical feedback for pixel identification, evaluation, and calibration for active matrix light emitting diode device (AMOLED) and other emissive displays. Optical feedback is utilized to calibrate pixel whose output luminance exceeds a threshold difference from a reference value, and may include the use of sparse pixel activation to ensure pixel identification and luminance measurement, as well as a coarse calibration procedure for programming the starting calibration data for a fine calibration stage.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 31, 2020
    Assignee: Ignis Innovation Inc.
    Inventor: Gholamreza Chaji
  • Patent number: 10606335
    Abstract: A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: March 31, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Deming Gu, Zhou Hong
  • Patent number: 10601860
    Abstract: Methods and systems provide application platform security enforcement. A distributed system communicates between a plurality of remote devices and at least one secured server to facility providing a secured service. The distributed system may comprise a remote communication server and one or more security layer components where the plurality of remote devices connect through ones of the security layer components. Upon detection of a security breach by a first remote device, the distributed system determines potential devices at risk from the plurality of remote devices, analyzing risk factors for commonalities. A lock down and/or quarantine of the first remote device and the devices at risk is instructed. Risk factors may include whether the remote devices communicate via a same security layer component, are geographically proximate; and/or are associated at the user level, for example are proximate users in a social network graph. Reactivation is also provided.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 24, 2020
    Assignee: THE TORONTO-DOMINION BANK
    Inventors: Koko Mihan, Dino D'Agostino, Paul Mon-Wah Chan, John Jong-Suk Lee, Paul Milkman, Satwinder Singh Brar
  • Patent number: 10585841
    Abstract: Techniques and systems for performing calibration. A method includes: creating a common calibration pool for performing a calibration operation for two or more communication links, wherein the calibration operation is common to the two or more communication links; and performing a calibration on each of the two or more communication links using the common calibration pool by receiving a calibration request associated with the common calibration operation via a link calibration interface, wherein the calibration request is from at least one of the two or more communication links, upon determining the calibration agent is available to handle the calibration request, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, retrieving a calibration engine from at least one of the plurality of calibration clusters corresponding to the calibration operation, and performing the common calibration based on the retrieving.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xu Guang Sun, Yang Xiao, Xiao Di Xing, Zhen Peng Zuo
  • Patent number: 10565241
    Abstract: A system, method and graphical user interface (GUI) for creating a new correlation search based on fluctuations in key performance indicators (KPIs) displayed in a set of graph lanes. The graph lanes may provide graphical visualizations of the KPIs associated with one or more services and may assist a user in identifying a situation (e.g., problem or a pattern of interest) in the performance of the services. The graph lanes can be adjusted (e.g., add graph lanes, zooming-in) in order to display the situation, at which point a new correlation search may be generated to detect if the situation reoccurs. The system may generate the new correlation search by iterating through the set of graph lanes and analyzing the fluctuations of each KPI to determine triggering criteria. The system may then run the correlation search and generate a notable event or alarm when the situation reoccurs.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: February 18, 2020
    Assignee: Splunk Inc.
    Inventors: Tristan Antonio Fletcher, Alok Anant Bhide
  • Patent number: 10566911
    Abstract: A device and method for controlling an inverter is disclosed. The inverter-controlling device in accordance with the present disclosure determines an operation state of a switching element of an initial charging module based on predetermined time durations and a magnitude of a DC link voltage measured at each of time points corresponding to the predetermined time durations.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: February 18, 2020
    Assignee: LSIS CO., LTD.
    Inventors: Deok-Young Lim, Hu-Jin Lee, Chun-Suk Yang
  • Patent number: 10560609
    Abstract: A system includes at least two capture devices, each switchable from a respective idle mode to a respective recording mode upon receipt of a trigger signal from a trigger via a network. A controller saves data packets generated by the capture devices during the respective idle modes to a short-term memory, and saves data packets generated during the respective recording modes to a long-term memory such that the data packets form respective saved data streams. The synchronizer sends a sync signal to the capture devices via the network. The compensator determines respective delay periods between sending of the sync signal by the synchronizer and receipt of the sync signal by each of the capture devices, and transfers from the short-term memory to the long-term memory any data packets generated during the respective delay period.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: February 11, 2020
    Assignee: Karl Storz Endoscopy-America, Inc.
    Inventor: Stephen Lau
  • Patent number: 10530250
    Abstract: Provided is a multiphase converter having a plurality of voltage conversion units, and is configured to protect the faulty phase and continue driving using another phase when an abnormality occurs in any phase. A DC-DC converter includes a plurality of voltage conversion units that are in parallel between an input-side conductive path and an output-side conductive path. A control unit subjects the plurality of voltage conversion units to a test operation in which a duty ratio of a PWM signal for each voltage conversion unit is changed. The control unit identifies an abnormal voltage conversion unit based on at least one of the states of the electric current, the voltage, and the temperature of the multiphase conversion unit during this test period, and causes the remaining voltage conversion unit other than the identified abnormal voltage conversion unit to perform voltage conversion.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 7, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Tsutsui, Seiji Takahashi, Takanori Itou
  • Patent number: 10516682
    Abstract: A data recorder stores endpoint activity on an ongoing basis as sequences of events that causally relate computer objects such as processes and files. When a security event is detected, an event graph may be generated based on these causal relationships among the computing objects. For a root cause analysis, the event graph may be traversed in a reverse order from the point of an identified security event (e.g., a malware detection event) to preceding computing objects, while applying one or more cause identification rules to identify a root cause of the security event. Once a root cause is identified, the event graph may be traversed forward from the root cause to identify other computing objects that are potentially compromised by the root cause.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 24, 2019
    Assignee: Sophos Limited
    Inventors: Beata Ladnai, Mark David Harris, Andrew J. Thomas, Andrew G. P. Smith, Russell Humphries, Kenneth D. Ray
  • Patent number: 10502763
    Abstract: Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 10, 2019
    Assignee: Tektronix, Inc.
    Inventors: Barton T. Hickman, John J. Pickerd, Pirooz Hojabri, Patrick Satarzadeh, Khadar Baba Shaik
  • Patent number: 10496506
    Abstract: A self-test capable integrated circuit apparatus includes a pattern generator, a results store and testable logic. The testable logic includes a plurality of scan channels, each of the channels being respectively coupled between the pattern generator and the results store. A self-test controller is arranged to supervise a self-test in respect of the testable logic to generate self-test result data, the self-test result data being stored in the results store. A processing resource is coupled to the self-test controller and coupled between the pattern generator and the results store, the processing resource being capable of evaluating the self-test result data stored in the results store. The testable logic includes the processing resource, arranged to cooperate with the self-test controller. The processing resource is able, subsequent to the self-test, to evaluate the self-test result data.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 3, 2019
    Assignee: u-blox AG
    Inventors: Yassine Fkih, Djordje Zegarac, Eric Demey, Luca Plutino, Marzia Sapienza
  • Patent number: 10474459
    Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney, Zeev Sperber, Amit Gradstein
  • Patent number: 10451676
    Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 22, 2019
    Assignee: Nvidia Corporation
    Inventors: Milind Sonawane, Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla, Sailendra Chadalavda, Rajendra Kumar Reddy.S, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
  • Patent number: 10451653
    Abstract: Example automatic test equipment (ATE) includes: a per-pin measurement unit (PPMU); logic configured to execute a state machine to control the PPMU; memory that is part of, or separate from, the logic; and a control system to command the logic; where, in response to a command from the control system, the state machine is configured to obtain, at a known interval or ATE event, data that is based on an output of a measurement by the PPMU and to store the data in the memory, or to output data to the PPMU from the memory at a known interval or synchronous to an event.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 22, 2019
    Assignee: Teradyne, Inc.
    Inventors: Marc Spehlmann, John J. Keough, Marc Hutner
  • Patent number: 10440237
    Abstract: A display device is provided. A data line includes a main line section, a first line section and a second line section spaced apart from one another. The first and second line sections respectively cross over a first scan line set to form first and second crossing regions. The main line section crosses over a second scan line set to form third crossing regions. The first line section is electrically connected to the main line section and one scan line of a third scan line set via a first switch element. The second line section is electrically connected to the main line section and another scan line of the third scan line set via a second switch element. First pixel units, second pixel units and third pixel units correspond respectively to the first crossing regions, the second crossing regions and the third crossing regions.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 8, 2019
    Assignee: Au Optronics Corporation
    Inventors: Pin-Miao Liu, Ting-Wei Guo
  • Patent number: 10438680
    Abstract: Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor. In some examples, a device includes a processor, a non-volatile memory, a test controller, and at least one further circuit part. In a test mode, the processor is configured to test the at least one further circuit part, and wherein the test controller is configured to test the non-volatile memory concurrently with at least part of the testing of the at least one further circuit part.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventor: Thorsten Bucksch
  • Patent number: 10430320
    Abstract: The method includes identifying, by one or more computer processors, elements of a test case, wherein elements include components that provide parameters of the test case. The method further includes assigning, by one or more computer processors, a score for each component of the one or more identified elements. The method further includes determining, by one or more computer processors, a priority score for each of the one or more test cases based upon the assigned score for each component of the one or more identified elements, wherein the priority score is a representation of a measure of importance for each one of the one or more tests case by a user.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Krishna R. Dhulipala
  • Patent number: 10417363
    Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 17, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jagjot Kaur, Priyanka Dasgupta, Pratyush Aditya Kothamasu, Vivek Chickermane
  • Patent number: 10418996
    Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Molka Ben Romdhane, Berndt Gammel
  • Patent number: 10404384
    Abstract: A method for testing a device under test with regard to spherical coverage is described, wherein a device under test is placed in an anechoic space to which a measurement antenna is assigned. A spherical coverage test is performed. The spherical coverage test is stopped after a minimum test criteria has been fulfilled. Further, a test system is described.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Heinz Mellein
  • Patent number: 10395726
    Abstract: A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 27, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Ying-Te Tu
  • Patent number: 10386404
    Abstract: A method for detecting damage of a solder joint of a printed circuit board of an electronic product by using a device for detecting damage of an electronic product according to the present invention includes: generating a digital signal and applying the digital signal to the solder joint of the printed circuit board; measuring a signal transmitted through the solder joint of the printed circuit board; and determining whether the solder joint of the printed circuit board is damaged using the measured signal. Accordingly, the device for detecting damage of an electronic product according to the present invention can nondestructively examine damage of the electronic product by using the digital signal.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 20, 2019
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Daeil Kwon, Jeong Ah Yoon
  • Patent number: 10372535
    Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 6, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Seow-Fong Lim, Ngatik Cheung, Chi-Shun Lin
  • Patent number: 10365703
    Abstract: Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Hang Tian, Jong Kang
  • Patent number: 10359961
    Abstract: According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi, Shintaro Hayashi
  • Patent number: 10355967
    Abstract: A video analysis system may utilize display screen snapshots captured from a device. The system may receive time information that indicates a time duration, position-related information that indicates a region, and reference information that indicates information expected to appear in the region during the time duration. The system may transmit an instruction to capture display screen snapshots during a time duration indicated by the time information. The system may receive a display screen snapshot and recognize information in the region indicated by the position-related information. The system may then determine whether the recognized information corresponds to the reference information and based on the result determine whether the video test automation has passed.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 16, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventor: Ambud Sharma