Abstract: Disclosed are various implementations of approaches for continuous delivery of management configurations. In some examples, a management configuration delivery workflow is retrieved from a source environment. The management configuration is transmitted to a destination environment specified in the management configuration delivery workflow. The destination environment us updated to apply the management configuration.

Abstract: A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.

Abstract: Apparatuses and methods for identifying network anomalies. A method includes determining a cumulative anomaly score over a predefined time range based on a subset of historical PM samples and determining an anomaly ratio of a first time window and a second time window, based on the cumulative anomaly score. The method also includes determining one or more anomaly events coinciding with CM parameter changes based on the anomaly ratio; collating the PM, alarm, and CM data into a combined data set based on matching fields and timestamps; generating a set of rules linking one or more CM parameter changes and the collated data to anomaly events; and generating root cause explanations for CM parameter changes that are linked to anomaly events.

Abstract: A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Abstract: A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.

Abstract: An electronic device includes a processing unit with a memory, a JTAG interface with test-data-input and test-mode-select lines coupled to the processing unit, a bridge circuit, and a multiplexer circuit. The bridge circuit includes a serial communication interface receiving a serial data input signal which conveys an input serial data frame. The bridge circuit includes a serial-to-parallel converter circuit block receiving the input serial data frame, processing the input serial data frame to read first and second subsets of input binary values therefrom, and transmitting the first subset via a first output signal and the second subset via a second output signal. The multiplexer circuit selectively propagates a received test-data-input signal or the first output signal to the test data input line, and selectively propagates a test-mode-select signal or the second output signal to the test mode select line of the JTAG interface.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: A method for secure usage of cryptographic material in networked system components provided with the cryptographic material in which a lifecycle of every system component includes at least one development phase and one production phase. The entire cryptographic material is at least directly securely marked as development or production material. Each system component has a binary state flag showing which phase the system component is in and which is secured against unauthorized manipulation. Each system component determines via an assessment function which phase it is in, according to which each system component carries out a check, during which the current phase and the marker of the cryptographic material are compared. Security measures are introduced if there is no agreement between the phase and the marker.

Abstract: A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

Abstract: An information processing apparatus includes an acquisition unit, a power supply unit, and a controller. The acquisition unit acquires failure information for the information processing apparatus via a wireless communication line from a management apparatus holding failure information. The power supply unit supplies power to the acquisition unit when the main power supply is not on. The controller exerts control in such a manner that, when the acquisition unit acquires the failure information from the management apparatus in the state in which the main power supply is not on, only a subset of functions of the apparatus are activated by supplying power from the power supply unit, and a process for limiting use of a function related to the failure is performed.

Abstract: An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.

Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Abstract: The present disclosure provides a method and a device for determining a root cause of fault, a server and a computer-readable medium. The method for determining a root cause of fault includes: determining fault characteristic information when a fault occurs in a service, and determining a fault root cause node according to the fault characteristic information and a preset fault propagation graph, the fault propagation graph is configured to represent directed association relationships among different fault propagation nodes, and directed association relationships among a fault node, the fault propagation nodes and fault root cause nodes, and the nodes in the fault propagation graph are configured to represent the fault characteristic information.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.

Abstract: Computer-implemented systems and methods for automatically generating an electronic circuit IP block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints, including time constraints. Exemplary systems and methods may include an electronic circuit layout generator and/or IP generator to obtain manufacturing processes and design rules from an external source, define a type of electronic circuit to be fabricated, prepare a circuit schematic of the defined electronic circuit, and generate an IP block for the defined electronic circuit based on the circuit schematic. A computer program generator is provided to create the defined electronic circuit. A computer readable storage medium contains processing instructions for obtaining the manufacturing processes and design rules and for fabricating the electronic circuit.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.

Abstract: An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.

Abstract: In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

Abstract: The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.

Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.

Abstract: A production system for producing products from raw materials by a production process with several steps has a number of production facilities that perform the steps and a control device. The control device determines a control target value by referring to information about group combinations specified in accordance with the relative merits of the manufacturing condition routes followed by respective lots during the production process. The routes are respectively set for a number of groups that are classified on the basis of raw material properties formed of a combination of property items of one or more types of raw materials. The relative merits of the routes are determined on the basis of quality items of the lots, classified for inter-step combinations of groups, which are classified on the basis of manufacturing conditions at the steps.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Abstract: A production system for producing products from raw materials by a production process with several steps has a number of production facilities that perform the steps and a control device. The control device determines a control target value by referring to information about group combinations specified in accordance with the relative merits of the manufacturing condition routes followed by respective lots during the production process. The relative merits are determined on the basis of quality items of the lots, classified for inter-step combinations of groups, which are classified on the basis of manufacturing conditions at the steps.

Abstract: Examples relate to determining a sampling threshold of a receiver (e.g., SERDES receiver). In particular, the examples relate to determining an updated sampling threshold of the receiver based on a reference sampling threshold of the receiver. A controller may determine the reference sampling threshold based on the training sequence and determine an upper voltage level and a lower voltage level of a voltage range based on the reference sampling threshold of the receiver. The controller then narrows the voltage range based on upper voltage accumulated hit rate and a lower voltage accumulated hit rate to determine the updated sampling threshold of the receiver.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: A method and system for capturing and annotating measurement data includes communicatively connecting a mobile computing device to one or more measurement devices, and receiving measurement data from the one or more measurement devices. The mobile computing device stores the received measurement data and annotates the stored measurement data with metadata. The metadata includes group identifying information that associates the stored measurement data with other data having similar group identifying information. In at least one embodiment, measurement data is automatically associated with the group identifying information based on the measurement data being captured within a predetermined amount of time of each other or within a predetermined distance of each other as determined by a positioning system.

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

Abstract: A clock self-testing method and circuit. The clock self-testing method includes introducing a first clock signal and a second clock signal, counting cycles of the first clock signal and the second clock signal respectively beginning at the same moment, and if one of the number of cycles of the first clock signal being counted and the number of cycles of the second clock signal being counted is equal to N, determining whether the remained number of cycles is in a count range from M to N. If the remained number of cycles is out of the count range from M to N, the first clock signal and the second clock signal have errors.

Abstract: For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.

Abstract: A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: A method for operating a communication system, in which multiple communication units exchange data via a communication medium, the method including the following steps: shifting the communication system at least temporarily into a diagnostic operating mode, in which data exchanged by multiple, in particular, by all of the communication units via the communication medium are available on at least one of the multiple communication units and/or on at least one component of the communication medium.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: A manufacturing process monitoring apparatus capable of determining a manufacturing process is anomaly, without requiring any threshold value for determining the as anomaly is provided.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

Abstract: A signal analysis method of analyzing a performance of a device under test is described. A digitized input signal is obtained, wherein the digitized input signal is associated with the device under test. At least one characteristic quantity is determined via an artificial intelligence circuit. The artificial intelligence circuit includes at least one computing parameter. The at least one characteristic quantity is determined based on the digitized input signal and based on the at least one computing parameter. The at least one characteristic quantity is indicative of at least one performance property of the device under test. Further, a test system for analyzing a performance of a device under test as well as a computer program or program product are described.

Abstract: A demarcating system for indicating the boundary of an area to an object (for example a robot, such as a robotic lawnmower), which has a receiver for receiving electromagnetic signals. The system includes a control system, a wire loop, a signal generator, and current sensing circuitry. The wire loop can be arranged by a user along a path, so as to indicate the path to the object as part of a boundary of the area. The signal generator is electrically connected to the wire loop in order to apply voltage signals thereto, such signals causing the emission of corresponding electromagnetic boundary indicating signals from the wire loop that may be received by the receiver of the object. The signal generator is under the control of the control system with the voltage signals applied by the signal generator to the wire loop being controlled by the control system. The current sensing circuitry senses current signals present within the wire loop and the processors of the control system analyse such current signals.

Abstract: A driving method of a display panel is provided. The driving method of the display panel includes: within one frame, in a charging period of sub-pixels electrically connected to an ith scan line, each multiplexing circuit charging N data lines electrically connected to the multiplexing circuit in a charging sequence of a first preset sequence; in a charging period of sub-pixels electrically connected to a jth scan line, each multiplexing circuit charging the N data lines electrically connected to the multiplexing circuit in a charging sequence of a second preset sequence; the second preset sequence is different from the first preset sequence, and charging rankings of each data line electrically connected to each multiplexing circuit in at least two charging sequences are different, where N is an integer and N?2, and i and j are positive integers and j?i.

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.