Abstract: A power control device of a display apparatus includes a display panel configured to include a plurality of pixels, a panel driver configured to drive the display panel, a power control unit configured to output a power control signal into which one or more pieces of control command data are encoded, and a power source unit configured to shift an output level of a source voltage needed for an operation of each of the display panel and the panel driver, based on the control command data, wherein the control command data comprises a plurality of control pulses where a logic low period and a logic high period are alternated, and the logic low period is implemented with two or more different lengths.

Abstract: Transmitting sampled flows in datagrams to a collector includes adding entropy to the headers of the UDP packets that encapsulate the datagrams. The entropy, for example, can be a timestamp associated with a sampled data packet contained in the datagram. Each UDP packet is transmitted on a data patch selected from among a plurality of data paths using at least the UDP header. The entropy in each UDP header serves to spread the transmission of UDP packets across the plurality of data paths.

Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

Abstract: An example test system includes a test instrument configured to test a device under test (DUT). The test instrument is configured to interact with the DUT using first commands having a first syntax. The test system also includes one or more processing devices configured (i) to receive a definitions file, where the definitions file includes information defining a second syntax that is used by a third party to communicate with the DUT, (ii) to receive second commands having the second syntax, (iii) to convert the second commands into the first commands having the first syntax based on the definitions file, and (iv) to send the first commands to the test instrument to enable the test instrument to interact with the DUT.

Abstract: Systems and techniques for multi-phase cloud service node error prediction are described herein. A set of spatial metrics and a set of temporal metrics may be obtained for node devices in a cloud computing platform. The node devices may be evaluated using a spatial machine learning model and a temporal machine learning model to create a spatial output and a temporal output. One or more potentially faulty nodes may be determined based on an evaluation of the spatial output and the temporal output using a ranking model. The one or more potentially faulty nodes may be a subset of the node devices. One or more migration source nodes may be identified from one or more potentially faulty nodes. The one or more migration source nodes may be identified by minimization of a cost of false positive and false negative node detection.

Abstract: A method is provided for communicating between passive subscribers of a bus system. A first passive subscriber encodes an original static pattern in a first transmit SERDES element and encodes original user data in a time-synchronized manner with the original static pattern in a second transmit SERDES element. The second passive subscriber receives the encoded static pattern and user data, and generates a sampling clock having a first phase offset and a clock synchronous with a transmit-receive clock having a second phase offset, from the encoded static pattern. The second passive subscriber decodes the encoded static pattern using a first receive SERDES element and the encoded user data, using a second receive SERDES element to obtain a receive data word. The first receive SERDES element and the second receive SERDES element are operated based on the sampling clock, and the receive data word is output synchronously with the synchronous clock.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine performance of audience measurement meters. An example apparatus disclosed herein is to cause an audio output device of a meter to emit an audio signal into an environment, the audio signal based on a test pattern including a first plurality of watermarks and cause an audio input device of the meter to collect data from the environment during emission of the audio signal. Additionally, the example apparatus is to determine whether a second plurality of watermarks decoded from the data match the first plurality of watermarks and based on a difference between the first plurality of watermarks and the second plurality of watermarks indicative of a fault, cause an alert to be transmitted to a device associated with an audience measurement company that issued the meter.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: Techniques are provided for capturing a processing state snapshot of a device under test (DUT) that enable a previous test run to be restored and resumed from the same point the snapshot was taken. The techniques enable restoring the snapshot into the same or a different device to resume a previous test run. In an illustrative example, a DUT is controlled by a Joint Test Action Group (JTAG) test controller to capture a Steady State Snapshot by controlling peripheral components of the DUT to complete any on-going tasks to reach a steady state and then flush data to a memory of the DUT. The flushed steady state peripheral component data and other processing state data is transferred to the test controller for analysis and for enabling the subsequent restore and resume operation. Solid state drive (SSD) examples are provided.

Abstract: A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.

Abstract: An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

Abstract: The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

Abstract: A method of testing a connectivity controller includes, in part, setting a configuration register disposed in the connectivity controller to a first value; causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value; returning data received by the second component, via the first component, for storage in a second section of the memory; comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and verifying the test if the first data matches the returned data.

Abstract: A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

Abstract: A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: A test system for a DRAM module of an AMD system is configured to verify information write and read functions of an EEPROM included in the DRAM module. The test system includes at least one memory module slot and a processing unit. The at least one memory module slot is configured for insertion of the DRAM module. The DRAM module includes the EEPROM. After an operating system controlling the processing unit, an I2C operation register of the processing unit can access the DRAM module through an I2C bus, and can write test data to and read the test data from the EEPROM. When the test data does not have sample data, it can be replaced by serial presence detection information.

Abstract: According to an aspect, there is provided a method for determining a sequence of bus nodes in a multi-drop communication bus. The method includes for each bus node: sending a request to the bus node using an bus node physical identifier to set the bus node to a loopback mode; transmitting at least one signal to the bus node via the multi-drop communication bus; receiving from the bus node a loopback signal caused by the at least one signal; and measuring a roundtrip delay between the at least one signal and the loopback response signal. The method further includes solving the physical order of the bus nodes in the multi-drop communication bus based on the roundtrip delays.

Abstract: Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.

Abstract: In certain aspects, a waveform driving device for a tester channel includes a waveform generator, a bit map register, and an output logic circuit. The waveform generator is configured to generate a waveform signal based on a driving source signal. The bit map register is configured to store a bit map associated with the tester channel. The output logic circuit is coupled to the bit map register and the waveform generator, and configured to control an output of the waveform signal through the tester channel based on a bit control signal from the bit map.

Abstract: An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.

Abstract: Various embodiments set forth systems and techniques for identifying issues associated with a domain name system (DNS) ecosystem. The techniques include receiving a first target domain name; identifying a plurality of DNS elements included in the DNS ecosystem that should be tested based on the first target domain name; performing one or more validation operations on the plurality of DNS elements based on the first target domain name to generate a first set of validation results; and identifying a first DNS issue associated with the first target domain name based on the first set of validation results.

Abstract: The present disclosure relates to a method and an apparatus for processing accelerated test data based on multiple performance degradation, and a device.

Abstract: A method includes selecting a first of a plurality of devices-under-test that has been connected in electronic communication with the test device for a longest period of time compared to others of the plurality of devices-under-test. A first task is performed on the first of the plurality of devices-under-test. After completing the first task, determining whether the test device needs to perform the first task on a second of the plurality of devices-under-test. Causing the first task to be performed on the second of the plurality of devices-under-test or selecting a third of the plurality of devices-under-test that has been connected in electronic communication with the test device for a next longest period of time compared to others of the plurality of devices-under-test.

Abstract: A system and method are provided for testing logic using a logic built in self-test (LBIST) system, and in particular where the LBIST system tolerates unknown inputs (Xs) to the logic cells forming an XLBIST system. The system allows for providing multiple test system clocks from the LBIST system to the logic during a system clock capture cycle of a system clock during testing of the logic, wherein the system clock is separate from the multiple test system clocks of the LBIST system. Further, timing of an application of clock cycles of the multiple test system clocks of the LBIST system is controlled and provided to the logic during the system clock capture cycle.

Abstract: An interactive test equipment for quality evaluation of resistance value test for electric leakage is disposed on a platform, and includes at least a control unit, a leaking electric current control module and an operating module. The leaking electric current control module includes at least a test set for quality evaluation to determine a resistance value for electric leakage. Each of the at least a test set has a circuit breaker and an electric leakage value display. The electric leakage value display of the each of the at least a test set can be used to display tripping circuit-breaking data of a corresponding circuit breaker. Test subjects can initiate the interactive test equipment and select answers through the operating module, and load questions and determine answers through the control unit.

Abstract: Embodiments of the present invention provide systems and methods for storing calibration data for a test system operable to test a device under test (DUT). The test system includes one or more channel modules and a device interface. A first part of the calibration data is stored on a non-volatile memory. The non-volatile memory can be disposed in different parts of the test system. The non-volatile memory is located on the device interface and can also be located on one or more of the channel modules, as well as an attachment of the test system. The non-volatile memory is associated with the one or more channel modules. The second part of the calibration data is stored on a non-volatile memory associated with the device-under-test interface.

Abstract: A hand-held ultrasound device, for placement on a subject, includes a semiconductor device and a housing to support the semiconductor device. The semiconductor device includes: a plurality of ultrasonic transducer elements; a plurality of pulsers coupled to the plurality of ultrasonic transducer elements; a plurality of waveform generators configured to drive the plurality of pulsers; receive processing circuitry configured to process ultrasound signals received by the plurality of ultrasonic transducer elements; and a plurality of independently controllable registers configured to store a plurality of different parameters for the waveform generators.

Abstract: A system, method, and device to test an electronic circuit are disclosed having a stage to supply a driving signal to a load comprising a pull-up switch and a pull-down switch and a pre-driver stage including pre-driver circuits. The electronic circuit including circuits for testing the pre-driver stage under the control of an automatic testing equipment (ATE) to operate a built-in self-test sequence including test commands for the pre-driver stage under the control of an external test signal issued by the ATE. The system includes a time measuring circuit to measure duration of signals at the output of the stage coupled to a pass-fail check circuit, and to evaluate if the duration of signals at the output of the stage to determine whether the output satisfies a pass criterion.

Abstract: A method includes receiving, by a computing system, a declarative testing descriptor for active testing of a network slice implemented by first virtualized services in a network; receiving, by the computing system and from an orchestration layer, metadata associated with the network slice; determining, by the computing system and based on the declarative testing description and the metadata, active testing configuration for testing the network slice; and starting an active test according to the active testing configuration and determining service level violations based on a result of the active test.

Abstract: An information processing device converts a plurality of original data arranged on a preset n-dimensional map into a plurality of new data arranged on a map according to a conversion rule. In the conversion rule, when an original datum at a target position on the map has a value of out-of-criterion, a new datum at the target position is set to the value of the original datum at the target position, and when the original datum at the target position has a value of within-criterion, each of values of one or more original data excluding an original datum having a value of the out-of-criterion from original data included in a reference region is selected to perform majority voting with the values of the one or more original data selected, and the new datum at the target position is set to a value determined by the majority voting.

Abstract: Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

Abstract: A semiconductor wafer and a multi-chip parallel testing method are provided. The semiconductor wafer includes a plurality of chips, a plurality of test pads, and a test control circuit. The test pads receive a plurality of test signals from a test fixture. The test control circuit is electrically connected to the chips and the test pads, selects at least one selected test signal from the test signals, generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the broadcast test signals to the chips in parallel.

Abstract: Systems and methods are disclosed for configuring a communication network to satisfy a set of demands. A network management system can obtain a network graph representing the communication network, connectivity relationship that indicates valid pairs of edges for each vertex in the network graph, and a structure that lacks zero divisors. The network management system can use the network graph, connectivity relationship, and structure to determine a path length for which a valid path connecting a source vertex and a terminal vertex exists. The path length can be determined using a dynamic programming approach that associates an element of the structure with the collection of paths connecting the source vertex and the terminal vertex. The network management system can then use the network graph, connectivity relationship, and structure to determine a valid path of the path length that connects the source vertex and the terminal vertex.

Abstract: A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

Abstract: A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Abstract: Systems, apparatuses, and methods for test devices having parallel impedances to reduce measurement input impedance are disclosed. An apparatus includes a test input terminal, a measurement output terminal, a reference voltage potential node, and a parallel resistor. The test input terminal is configured to electrically connect to a signal output terminal of a signal generator. The test input terminal is configured to receive a test signal from the signal generator via the signal output terminal. The measurement output terminal electrically connects to a measurement input terminal of an electrical measurement instrument. The parallel resistor is electrically connected from the measurement output terminal to the reference voltage potential node. A system includes the apparatus and the electrical measurement instrument. A method includes providing a test signal to the test device, verifying the test signal using the electrical measurement instrument, and providing the test signal to a device under test.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: A method, and a Solid-State Drive (SSD) memory device and a system for assessing operational effectiveness of the SSD is provided. Upon a failure of the SSD memory device, a command is executed which is received from a host device. The SSD memory device switches to an operational state after executing the command. A data structure having SSD operational parameters is obtained from a plurality of data structures obtained before the failure and stored in a Read Only Memory (ROM) upon the SSD memory device switching to the operational state. The obtained data structure is restored into a Random-Access Memory (RAM).

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: Large and complex software projects may be distributed over multiple repositories and may use test automation of equivalent scale in continuous integration frameworks to maintain quality of the project. Such test automation often has significant hardware and time costs to run, which may mean that a failure of the software in the test automation takes longer to detect. Delay in fixing the software may increase the chance of more failures getting checked into the software repositories and perpetuating software failures. To address this issue, a ranking of historical test data is determined based on a number of failures for each test and a test configuration is determined based on the ranking such that tests that are ranked higher are performed before tests that are ranked lower. The test may be exited upon detection of failure instead of continuing.

Abstract: A burn-in board includes: a board; a socket mounted on the board; a connector attached to the board; a wiring system that is disposed in the board and that connects the socket and the connector; and a compensation circuit that connects to the wiring system and that compensates a frequency characteristic of a signal transmitted through the wiring system.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

Abstract: Systems and methods are provided for dynamic segmentation of users during an experiment based on changes to application data collected during the experiment. Data regarding application interactions and associated application metadata may be collected from users during application experiments that involve testing different variants of a feature or otherwise different user experiences. The data regarding application interactions and associated application metadata may be evaluated to discover segments of users and/or usage patterns (e.g., “cohorts”). During the experiment, the users may be dynamically re-segmented into new/different cohorts based on new application data being collected.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: Methods for detecting a glitch at a high sampling rate are provided. In some embodiments, a method includes the following steps: S1, acquiring to-be-identified data; S2, processing the to-be-identified data to obtain normal sampling data; and S3, performing glitch identification on the to-be-identified data to obtain a glitch position of the normal sampling data. In other embodiments, the disclosure provides a system for detecting a glitch at a high sampling rate and for implementing the method for detecting a glitch at a high sampling rate. The system includes an acquisition unit and a glitch identification unit. The acquisition unit acquires and processes the to-be-identified data to obtain the normal sampling data, and the glitch identification unit performs glitch identification on the to-be-identified data to obtain the glitch position of the normal sampling data.

Abstract: A method for real-time processing of a detection signal, wherein signal processing is respectively performed when a detection signal is converted from a high level to a low level or vice versa. A moment at which a level of the detection signal is converted is recorded as a start point. A status of the detection signal is then detected in real time at a current moment. A current time width is compared to a maximum interval width of pre-set interference signals, and signal levels are determined and recorded from the start point to the current moment. Using characteristics of different interference signals, anti-interference processing is performed by using a targeted edge positioning and width recognition method, so that the delay impact of filtering on signals is avoided, improving both the recognition precision of weighing data of a checkweigher and the overall performance of the checkweigher.

Abstract: One aspect provides a method and system for saturation of multiple I/O slots by multiple testing ports and verification of link health in between. During operation, the system detects a testing card with a plurality of test ports which are coupled to a plurality of input/output (I/O) slots of a computing device. The system communicates with the plurality of test ports via the plurality of I/O slots. The system generates, by the computing device, a script for each test port, wherein the script comprises a series of read and write operations to be executed by the testing card on a memory device associated with the computing device. The system allows the plurality of test ports to execute the script and perform the corresponding read operations and write operations, thereby facilitating testing of the I/O slots of the computing device in parallel by the test ports of the single testing card.