Digital Logic Testing Patents (Class 714/724)
  • Patent number: 11450366
    Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Kwang Soon Kim, Dae Ho Yang, Yo Han Jeong, Jun Sun Hwang
  • Patent number: 11430536
    Abstract: An automated test equipment (ATE) system comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor. The tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports an arbitrary sector size, and wherein software layers on the tester processor perform computations to be able control data flow between the tester processor and sectors of arbitrary size in the DUT.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Advantest Corporation
    Inventors: Srdjan Malisic, Chi Albert Yuan
  • Patent number: 11422184
    Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 23, 2022
    Assignee: Apple Inc.
    Inventors: Charles J. Fleckenstein, Tal Lazmi, Ori Isachar
  • Patent number: 11423964
    Abstract: An example memory device includes an array of memory cells, a plurality of boundary cells, mixed pads connected to the memory cells, high speed pads connected to the boundary cells, a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive at least first and second input signals, and the three state multiplexer block is connected to the mixed pads. The example memory device further includes an enabling circuit connected to a mixed pad and configured to receive an external enabling signal and provide the three state MUX with an internal enabling signal, and comprising: a tester presence detector circuit connected to the mixed pad and configured to provide a presence signal to a logical gate, the logical gate having input terminals connected to the tester presence detector circuit and configured to provide the internal enabling signal.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11415628
    Abstract: An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Advantest Corporation
    Inventors: Olaf Pöppe, Klaus-Dieter Hilliges, Alan Krech
  • Patent number: 11408938
    Abstract: A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: August 9, 2022
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11378489
    Abstract: An object is to provide a propagation property analyzing apparatus that can alleviate the influence of an error caused by crosstalk, and accurately evaluate a few-mode optical fiber that multiplexes a plurality of modes, in a distributional and non-destructive manner.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 5, 2022
    Inventors: Hiroshi Takahashi, Tomokazu Oda, Kunihiro Toge, Tetsuya Manabe
  • Patent number: 11354480
    Abstract: Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: June 7, 2022
    Assignee: Cadence Design Systems, Ine.
    Inventors: Matthew David Eaton, Ji Xu, George Simon Taylor, Zhuo Li
  • Patent number: 11346897
    Abstract: A magnetic field sensor comprises a signal conditioning IC and a magnetic field sensor IC, the magnetic field sensor IC being mounted on and connected to the signal conditioning IC. The magnetic field sensor IC comprises a semi-conductor substrate with a sensor active layer disposed an outer facing side of the magnetic field sensor opposite the signal conditioning IC. The sensor active layer is connected to conductive vias that extend through the semi-conductor substrate from said outer facing side to an underside facing the signal conditioning IC, an underside of the conductive via being electrically interconnected to a connection pad on the signal conditioning IC via a chip-on-chip interconnection comprising a conductive bead connection and a solder connection.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 31, 2022
    Assignee: LEM International SA
    Inventors: Jean-François Lanson, Dominik Schläfli
  • Patent number: 11327554
    Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: May 10, 2022
    Assignee: Abbott Diabetes Care Inc.
    Inventors: Daniel M. Bernstein, Saeed Nekoomaram, Mark K. Sloan
  • Patent number: 11293969
    Abstract: This application is related to a measuring system and method for performing various measurement tasks. The measuring system comprises a test-setup configured to measure the characteristics of a device-under-test and an input-device of the test-setup configured to receive a test-case. The measuring system further comprises several measurement-hardware devices configured to perform the measurements according to the test-case. A computer unit of the measuring system is configured to determine at least one required hardware device on the basis of the test-case and to select the additional measurement-hardware devices. The computer unit is further configured to identify an adding of the selected additional measurement-hardware.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 5, 2022
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Byron-Lim Timothy Steffan, Peter Wolanin
  • Patent number: 11294660
    Abstract: An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 5, 2022
    Inventors: Yuanlu Xie, Kun Zhang, Haitao Sun, Jing Liu, Jinshun Bi, Ming Liu
  • Patent number: 11287630
    Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Franco Stellari, Peilin Song
  • Patent number: 11283451
    Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 22, 2022
    Assignee: Google LLC
    Inventor: Jonathan Ross
  • Patent number: 11275104
    Abstract: A waveform data acquisition module acquires the waveforms of electrical signals for multiple channels. A memory controller continuously writes a digital signal S3 to one from among a first memory unit and a second memory unit. When a given memory unit has become full, the memory controller notifies an external higher-level controller that the corresponding memory unit is full and switches the wiring target to the other memory unit.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 15, 2022
    Inventors: Takeshi Yaguchi, Kazushige Yamamoto, Hideyuki Oshima, Shintaro Ichikai
  • Patent number: 11276678
    Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 15, 2022
    Assignee: Honeywell International Inc.
    Inventor: James L. Tucker
  • Patent number: 11263883
    Abstract: A system on a chip (SoC) for smoke detection includes power regulator circuits coupled to respective pins and analog sensor amplifier circuits that are each coupled to a respective pin of the pins coupled to the power regulator circuits. A first analog sensor amplifier circuit of the analog sensor amplifier circuits has a photoelectric amplifier circuit, a first LED driver and a second LED driver. The SoC also has a digital core that includes a digital logic circuit, register bits, and an MCU communication circuit. The MCU communication circuit is coupled to a data pin, the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written to by an MCU.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 1, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Grant Evan Falkenburg, Shinya Morita, Mehedi Hassan, Lundy Findlay Taylor
  • Patent number: 11257564
    Abstract: Methods, systems, and devices for defect detection for a memory device are described. A segmented digital die defect detector may include multiple signal lines, each coupled with a test circuit, and a control circuit to form a path. At least part of the path may extend through an internal portion of the die. A test circuit may generate a digital feedback signal that indicates a condition of a respective signal line. The control circuit may generate a single output signal, indicative of the condition of the signal lines. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die defect detector may be reduced and a power consumption associated with the testing operation may be reduced.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chun Yi Lu
  • Patent number: 11250167
    Abstract: Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: R Selvakumar Raja Gopal, Asad Azam
  • Patent number: 11238212
    Abstract: Described in detail herein are methods and systems dynamically generating maintenance data. The system includes a first computing system which can receive identification credentials associated with a user. The second computing system can receive the identification credentials associated with the user. The second computing system can authenticate the identification credentials associated with the user. The second computing system can determine whether the user is a first type or a second type in response to authenticating the identification credentials associated with the user. The second computing system can dynamically generate and display an editable form with empty fields, on the interactive display of the first computing system, in response to determining the user is of a first type. The second computing system can dynamically populate and display a read-only report on the interactive display of the first computing system, in response to determining the user is of a second type.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 1, 2022
    Assignee: RailWorks Corporation
    Inventors: Justin Mueller, Robert Rolf, Richard Stephens
  • Patent number: 11221365
    Abstract: An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 11, 2022
    Assignee: Teradyne, Inc.
    Inventors: Stephen J. Lyons, David Tu
  • Patent number: 11217653
    Abstract: A display apparatus includes: a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape; a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits; a first voltage line extending on the display area in the first direction; a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line; a test circuit outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minchae Kwak, Ilgoo Youn, Byungsun Kim, Jieun Lee, Seunghan Jo, Junyoung Jo, Minhee Choi
  • Patent number: 11204849
    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 21, 2021
    Assignee: NVIDIA Corporation
    Inventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
  • Patent number: 11176011
    Abstract: Disclosed herein are an apparatus and method for transmitting fuzzing data. The apparatus may include one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may collect context information pertaining to a one-way fuzzing target device that uses a one-way protocol, may determine the execution state of the one-way fuzzing target device by analyzing the context information, and may transmit fuzzing data to the one-way fuzzing target device based on the result of determination of the execution state.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 16, 2021
    Inventors: Gae-Il An, Won-Jun Song, Yang-Seo Choi
  • Patent number: 11178192
    Abstract: Embodiments of the present disclosure relate to a method and device for facilitating a connectivity check between a terminal device and a media gateway. In example embodiments, the session controller receives, via a web gateway associated with said terminal device, a request for establishing a real-time communication call and an indication for indicating a capability of said terminal device for early reception of a connectivity parameter of said media gateway to be used in said connectivity check. The session controller obtains said connectivity parameter from said media gateway. Then, in response to said connectivity parameter being obtained, the session controller sends said connectivity parameter via said web gateway towards said terminal device within a time limit. In this way, said terminal device may initiate said connectivity check to said media gateway earlier, and thus a latency of call establishment may be reduced significantly.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 16, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Huoming Dong, Julio Martinez Minguito
  • Patent number: 11169205
    Abstract: A waveform data acquisition module includes an A/D converter that converts an electrical signal relating to a DUT into a digital signal, and a first memory unit that stores waveform data configured as a digital signal sequence. A function test module includes a test unit and a second memory unit. A higher-level controller instructs the waveform data acquisition module to start data sampling, and holds the time point thereof. Furthermore, the higher-level controller instructs the function test module to start to execute a pattern program, and records the time point thereof. The first memory unit records the time point at which the data sampling is started. The higher-level controller records the time point at which the execution of the pattern program is started.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: November 9, 2021
    Inventors: Naoya Toyota, Yasuki Akita
  • Patent number: 11143700
    Abstract: An optic probe is used to measure signals from a device under test. The optic probe is positioned at a target probe location within a cell of the device under test, the cell including a target net to be measured and a plurality of non-target nets. A test pattern is applied to the cell with the optic probe a laser probe (LP) waveform is obtained in response. A target net waveform is extracted from the LP waveform by: (i) simulating a combinational logic analysis (CLA) cross-talk waveform to model cross-talk from selected non-target nets by simulating an optical response of the cell to the test pattern with the target net masked; (ii) estimating a cross-talk weight; and (iii) determining a target net waveform by weighting the CLA cross-talk waveform according to the cross-talk weight and subtracting the weighted CLA cross-talk waveform from the LP waveform.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Venkat Krishnan Ravikumar, Nathan Linarto, Wen Tsann Lua, Abel Tan Yew Hong, Shei Lay Phoa, Gopinath Ranganathan, Jiann Minn Chin
  • Patent number: 11125816
    Abstract: A method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pin.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 21, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaodong Xu, Xiangming Zhao, Shunlin Liu, Yi Chen
  • Patent number: 11119471
    Abstract: A method for operating a component of predetermined geometry ? that is cyclically loaded during operation, wherein a probability of failure P is determined for the component taking account of distributions of failure times, which are caused by deviations in material properties, the component is operated depending on the determined probability of failure P, wherein at least one maintenance time is set for the component, in particular depending on the determined probability of failure P.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 14, 2021
    Inventors: Hanno Gottschalk, Mohamed Saadi, Sebastian Schmitz
  • Patent number: 11106197
    Abstract: A prediction model creation apparatus includes a feature amount acquisition unit that acquires values of types of feature amounts that are calculated from operating state data indicating an operating state of a production facility that produces a product, for both a normal time at which the production facility produces the product normally and a defective time at which a defect occurs in the product that is produced, a feature amount selection unit that selects a feature amount effective in predicting the defect from among the acquired types of feature amounts, based on a predetermined algorithm that specifies a degree of association between the defect and the types of feature amounts, from the values of the types of feature amounts acquired at the normal time and the defective time, and a prediction model construction unit that constructs a prediction model for predicting occurrence of the defect, using the selected feature amount.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 31, 2021
    Assignee: OMRON Corporation
    Inventors: Reiko Hattori, Kosuke Tsuruta, Kota Miyamoto, Yuya Ota, Hideki Higashikage, Yuki Hirohashi, Noriyuki Oikawa
  • Patent number: 11073558
    Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.
    Type: Grant
    Filed: December 1, 2019
    Date of Patent: July 27, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Tzung-Jin Wu, Jeong-Fa Sheu, Po-Lin Chen, Yin-Ping Chern, Ying-Yen Chen
  • Patent number: 11074623
    Abstract: The present disclosure discloses a method and device for pushing information to a target user. One example method includes identifying a plurality of users that meet a predetermined condition; selecting a target user from the identified users to be provided with information, where in the target user is selected based on a relationship strength and an influence of the identified users; and transmitting the information to the determined target user over a network, and relates to the field of information technologies.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 27, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Nian Song
  • Patent number: 11071920
    Abstract: A modular multi-system gaming console can be configurable for use in conjunction with expansion consoles (also referred to as expansion modules, expansion units, and/or element modules herein) as a gaming console emulator and/or for use as an audio/video converter (e.g., an up-converter), data recorder, or streaming device. Further, the modular multi-system gaming console can evoke the original gaming experience of a game played on original hardware. A modular multi-system gaming console can provide a consistent platform for display, content management, statistical storage and analysis (e.g., high scores, fastest speed runs, etc.), and live streaming and other services (including core services described herein) across a multitude of gaming console platforms. A modular multi-system gaming console can also provide a more authentic game experience via active cartridge reading.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 27, 2021
    Inventors: Bryan Alan Bernal, Eric Christensen, Robert Wyatt
  • Patent number: 11069400
    Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 20, 2021
    Inventors: Seongil O, Namsung Kim, Sukhan Lee
  • Patent number: 11041904
    Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 22, 2021
    Inventors: Tapan Jyoti Chakraborty, Umesh Srikantiah, Rachana Rout
  • Patent number: 11009547
    Abstract: A computer system includes a circuit board, one or more electronic components and a board management controller (BMC). The electronic components are disposed on the circuit board. The BMC is disposed on the circuit board and electrically connected to the one or more electronic components. The BMC is configured to enable/initiate a boundary scan test for the one or more electronic component.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 18, 2021
    Inventors: Mao Sui Wang, Pao-Ting An
  • Patent number: 11010520
    Abstract: One embodiment provides a system and method for automated design of a computational system. During operation, the system obtains a component library comprising a plurality of computational components, receives design requirements, and builds a plurality of universal component cells. A respective universal component cell is configurable, by a selection signal, to behave as one of the computational components. The system further constructs a candidate computational system using the universal component cells, constructs a miter based on the design requirements and the candidate computational system, and converts the miter into a quantified satisfiability (QS) formula. The system generates a set of inputs that are a subset of all possible inputs of the QS formula, solves the QS formula by performing partial input expansion on the generated set of inputs to obtain at least one design solution, and outputs the at least one design solution to facilitate construction of the computational system.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 18, 2021
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Alexandre Campos Perez, Aleksandar B. Feldman, Johan de Kleer
  • Patent number: 11012056
    Abstract: A ring oscillator including a plurality of flip-flops is provided. The flip-flops are connected in a ring. The flip-flops are configured to start to oscillate according to a start signal to generate an output signal, and stop oscillating according to a stop signal to stop generating the output signal. When the stop signal changes from a first level to a second level, the output signal becomes floating. In addition, a time measuring circuit including the foregoing ring oscillator is also provided.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Taihei Shido
  • Patent number: 11010414
    Abstract: A system to collect and store in a special data structure arranged for rapid searching massive amounts of data. Performance metric data is one example. The performance metric data is recorded in time-series measurements, converted into Unicode, and arranged into a special data structure having one directory for every day which stores all the metric data collected that day. The data structure at the server where analysis is done has a subdirectory for every resource type. Each subdirectory contains text files of performance metric data values measured for attributes in a group of attributes to which said text file is dedicated. Each attribute has its own section and the performance metric data values are recorded in time series as Uinicode hex numbers as a comma delimited list. Analysis of the performance metric data is done using regular expressions.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 18, 2021
    Inventors: Ajit Bhave, Arun Ramachandran, Sai Krishnam Raju Nadimpalli, Sandeep Bele
  • Patent number: 10990736
    Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Satyaprakash Pareek, Krishna Garlapati, Ashish Sirasao
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Patent number: 10929273
    Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 23, 2021
    Assignee: HITACHI, LTD.
    Inventors: Toru Motoya, Masahiro Shiraishi, Satoshi Nishikawa, Keisuke Yamamoto, Tadanobu Toba, Takumi Uezono, Hideo Harada, Yusuke Kanno
  • Patent number: 10922150
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system comprising at least one processor, a management controller communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system, a debugging circuit, and a logic device coupled to the host system and to the management controller. The logic device may be configured to determine that a trigger event has taken place, and in response to the trigger event, provide a serial data stream corresponding to the trigger event to the debugging circuit. The debugging circuit may be configured to provide access to the serial data stream to a debugging information handling system via a wireless interface.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 16, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jeffrey Kennedy
  • Patent number: 10903641
    Abstract: A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 26, 2021
    Inventors: Jan Roelof Westra, Jan Mulder
  • Patent number: 10895598
    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 19, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10890619
    Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma
  • Patent number: 10886001
    Abstract: A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product includes a pattern memory that stores a part of the test pattern. The pattern memory is rewritten during a time when the semiconductor product is tested by a part of the test pattern stored in the pattern memory included in the semiconductor-product testing device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 5, 2021
    Inventors: Naoki Yamada, Yoshiyuki Matsumoto, Kazuhiro Nishimura
  • Patent number: 10845408
    Abstract: A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. The wafer burn-in test circuit may include a wafer burn-in signal decoding unit configured to generate a plurality of decoding signals by decoding the plurality of timing-compensated input signals and output the plurality of decoding signals as a plurality of wafer burn-in signals by latching the plurality of decoding signals.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Jae Choi
  • Patent number: 10831639
    Abstract: A method and a device for non-intrusively collecting function trace data of a software application running on a processor-core, comprising translating a source code of the software application which comprises traceable function source code into executable code. The steps to execute the executable code include allocating the executable code of the traceable function within at least one pre-defined code memory region, checking each function call or jump instruction for its target address, and if the target address is located within the pre-defined code memory region, logging the execution of the traceable function.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 10, 2020
    Assignee: Gliwa GmbH Embedded Systems
    Inventor: Peter Gliwa
  • Patent number: 10823781
    Abstract: Embodiments are directed to apparatuses and methods for providing a logic built-in self-test (LBIST) using an LBIST logic circuit and an auxiliary logic circuit. An example method includes using switch circuitry in an integrated circuit (IC) to change modes of operation associated with functional logic circuit, the modes of operation including an LBIST mode and an application mode, and to provide an internally generated digital clock signal to the functional logic circuitry and an LBIST logic circuit in response to the LBIST mode. The method further includes performing an LBIST using the internally generated digital clock signal, the LBIST logic circuit to test select nodes in the IC via control of the functional logic circuitry and via application of digital logic sequences provided as inputs to the I/O pad cells of the IC.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat