Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to generate test patterns to apply to scan chains in an integrated circuit. The computing system can implement a defect diagnosis tool to simulate a circuit design describing an integrated circuit, inject faults from a fault list into the simulated circuit design, and apply the test patterns to the simulated circuit design. The computing system implementing the defect diagnosis tool can determine fault responses to the test patterns read from the simulated circuit design, which indicate a detection of the faults injected in the simulated circuit design, compress, for each of the faults in the fault list, the fault responses into fault signatures, consolidate the faults from the fault list into fault groups based on the fault signatures, and estimate a diagnosis resolution for the integrated circuit based, at least in part, on the fault groups.

Abstract: A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.

Abstract: A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.

Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.

Abstract: A system includes at least one sensor and an equipment health monitoring (EHM) unit. The at least one sensor is configured to measure one or more characteristics of an asset, where the asset includes a piece of equipment. The EHM unit includes at least one sensor interface configured to receive at least one input signal associated with the asset from the sensor(s). The EHM unit also includes at least one processing unit operable to be pre-configured to identify a specified fault in the asset using the input signals and an asset-specific model that includes a combination of standard subsystem models. The EHM unit further includes at least one output interface configured to provide an indicator identifying the fault. The standard subsystem models could include standardized fault models configured to identify faults for standard assets.

Abstract: Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Abstract: This embodiment relates to software verification and in particular to automatic generation of Modified Condition/Decision Coverage (MC/DC) tests scenarios. A system and method for reducing Modified Condition/Decision coverage (MC/DC) test scenarios is described along with selection of test data automatically for an input Boolean expression. An MC/DC test case engine generates optimal test case for a Boolean expression using an algorithm. The optimal minimal number of MC/DC cases generated to for satisfy the MC/DC condition for ‘n’ number of inputs may be ‘n+1’. The MC/DC test engine supports Boolean expression with Arithmetic and Comparison operators.

Abstract: Methods and apparatus are provided for determining whether a built-in-test fault code (BITFC) data sequence generated by a built-in-test (BIT) of a particular module of a complex system is indicative of an actual fault condition. A regression function is generated for the particular module based on stored BITFC data sequences generated by the BIT and stored repair data for that module from a fault history database. Later, during operation of the particular module, the BIT generates a new BITFC data sequence. A processor can then load the new BITFC data sequence and execute the regression function with respect to the new BITFC data sequence to determine whether the new BITFC data sequence is indicative of an actual fault condition at the particular module or is indicative of a false fault condition at the particular module.

Abstract: A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.

Abstract: Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor.

Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.

Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: providing a data detection circuit including a first detection processing circuit, a second detection processing circuit, a decoder processing circuit, and a memory circuit; performing a data detection algorithm on an input data set by the first detection processing circuit to yield a first detected output; writing a derivative of the first detected output to the memory circuit; accessing the derivative of the first detected output from the memory circuit; performing a decoder algorithm on the derivative of the first detected output using the decoder processing circuit to yield a decoded output; writing the decoded output to the memory circuit; accessing the decoded output from the memory circuit; and performing the data detection algorithm on a combination of the input data set and the decoded output to yield a second detected output.

Abstract: A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: A method and system of supporting and testing equipment distant from the support system are provided. The method includes the steps of forming a communications link between the equipment and the support system, using the support system to measure performance of the equipment and to provide a set of performance data, providing library data relating to the equipment, comparing the performance data with the library data and analysing the compared data whereby to provide a performance diagnosis of the equipment, all in a substantially continuous real time operation.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.

Abstract: A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern.

Abstract: A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.

Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.

Abstract: Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A periodic Low Density Parity Check (LPDC) coding apparatus and method allows reference to an LDPC code parity check matrix, where such reference is accomplished row by row. A specially configured memory and cyclical shift operation are used by the apparatus to efficiently compute check equations of the periodic LDPC code.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: A design data storage unit stores design data of constituent elements constituting a computer system to be monitored. A monitoring condition storage unit stores monitoring conditions of abnormal detection of the object to be monitored and error information to be outputted when the object meets particular monitoring conditions. A constituent component simulated failure setting unit causes the constituent elements in the design data to simulate failure one by one. A monitoring condition check unit checks if each monitoring condition is met when one constituent element is set in a failed state by instructing a network examining unit to examine the design data and extracts all the error information relevant to the met monitoring conditions. According to the results, information on the correspondence between the failed constituent elements and all extracted error information is stored in a monitoring simulation result storage unit.

Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.

Abstract: The invention relates to a detection of a simultaneous occurrence of an event of a predetermined kind at a plurality of electronic devices. At least two devices detect the event and record at their end the time elapsing after this detection. Then, a communication channel is established between the devices. Once the communication channel has been established, an indication of the recorded elapsed times can be exchanged. At least one of the devices compares a recorded elapsed time with an indicated elapsed time received from another device. If both elapsed times are similar to each other, it can be assumed that the event occurred simultaneously at both devices. The invention relates equally to corresponding devices, to a corresponding data transfer system and to corresponding software program products.

Abstract: Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

Abstract: A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.

Abstract: Certain exemplary embodiments provide a method comprising a plurality of activities, comprising: automatically: receiving a signal; and via a plurality of iterations, determining, for the received signal, a provable near-optimal B-term representation formed from a linear combination of a plurality of elements selected from a predetermined redundant ?-coherent dictionary, said determined near-optimal B-term representation corresponding to an error that is a minimum of a set of errors corresponding to all possible B-term representations associated with the predetermined redundant ?-coherent dictionary.

Abstract: A testing apparatus includes a logic comparing unit for comparing the output value with a predetermined expectation value; a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit; and a clock generating circuit including a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputting a second comparison result signal; and a reproduced clock generating module for generating the reproduced clock based on the first and second comparison result signals.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber, calculating dynamic estimation errors for the precursor and/or purging process, and determining if the dynamic estimation errors can be associated with pre-existing BIST rules for the process. When the dynamic estimation error cannot be associated with a pre-existing BIST rule, the method includes either modifying the BIST table by creating a new BIST rule for the process, or stopping the process when a new BIST rule cannot be created.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber; determining a measured dynamic process response for a rate of change for a process parameter; executing a real-time dynamic model to generate a predicted dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the expected process response; and comparing the dynamic estimation error to operational limits.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

Abstract: In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input signal lines and the output signal lines, different symbols are injected into fanout branches of one faulty candidate of the gates.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.

Abstract: The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated for the purpose of displaying test assessments. According to one embodiment of the invention, to supply the desired responses, a reference module produced with the same design and technology as the test specimen and tested as entirely satisfactory is utilized. The same test pattern as for the test specimen is applied to the reference module. The invention furthermore relates to circuit arrangements for carrying out this method, in particular for testing data memories.

Abstract: Logic correction support equipment supports logic correction of a logic circuit in LSI design for synthesizing a logic circuit from a register transfer level by logic synthesis. The logic correction support equipment finds a logic that was redundant before logic correction and becomes non-redundant after the logic correction by comparing redundant fault between the RTL before the logic correction and the RTL after the logic correction, and thereby supports manual correction of the logic circuit.

Abstract: A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.

Abstract: A method and apparatus are provided for determining the health of a desired node in a multi-level system. The method includes defining a first fault model associated with a first node of a first level of the system, defining a second fault model associated with a second node of a second level of the system, and defining a third fault model associated with a third node associated with a third level of the system. The method further includes determining a health value associated with at least one of the first node, the second node, and the third node of the system based on at least one of the first fault model, second fault model, and the third fault model.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STE) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: A virtual environment browser (64) holds a number of clip-in files (70, 72, 74) defining guide characters—locally generated visual aids to navigation that appear within a generated image of a virtual environment and follow a user's input (80) navigational commands to provide an advance cue as to the effects of an input command. Where the virtual environment data is supplied from a remote source (62) and includes (78) an indication of a preferred mode for navigating that environment, for example, flying or walking, the browser (64) detects this indication and automatically selects the appropriate guide character. Scaling (84) of the guide character to match the scale of the virtual environment, or such as to render the guide character unobtrusive, may also be provided.