Abstract: Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model is disclosed. In one aspect, a partial replay controller is provided in a processor(s) of a central processing unit (CPU). If an instruction is detected in the instruction block associated with a potential architectural state modification, or an exception occurs during execution of instructions, the instruction block is re-executed. During re-execution of the instruction block, the partial replay controller is configured to record produced results from load/store instructions. Thus, if an exception occurs during re-execution of the instruction block, previously recorded produced results for the executed load/store instructions before the exception occurred are replayed during re-execution of the instruction block after the exception is resolved.

Abstract: A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.

Abstract: A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.

Abstract: A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups; determining an order of the plurality of groups to be shortened, based on a ratio of a number of bits to be shortened to a number of bits to be punctured; determining a length of an information word to be obtained by shortening the plurality of groups; shortening the plurality of groups on a group basis in the determined order based on the determined length of the information word; and LDPC-encoding a shortened information word.

Abstract: A method for detecting codewords in solid-state storage devices. The method includes the steps of: obtaining respective read signals by reading memory cells that stores a group of codewords, where each of the read signals includes N signal components corresponding to respective symbols of the codeword; producing an ordered read signal by ordering the components of each of the read signals according to a signal level; producing an average read signal by averaging corresponding components of the ordered read signals; determining a reference signal level that corresponds to each of q levels of the memory cells in relation to the average read signal with predefined probabilities of each symbol value occurring at each symbol position in the codeword, where the symbols of the codeword are ordered according to the symbol value; and detecting the codeword corresponding to each of the read signal in relation to the reference signal levels.

Abstract: A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.

Abstract: A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A system and method are provided for efficiently initializing a redundant array of independent disks (RAID). The method monitors host write operations and uses that information to select the optimal method to perform a parity reconstruction operation. The bins to which data access write operations have not occurred can be initialized using a zeroing process. In one aspect, the method identifies drives in the RAID array capable of receiving a ‘WriteRepeatedly’ command and leverages that capability to eliminate the need for the RAID disk array controller to provide initialization data for all disk array initialization transfers. This reduces the RAID array controller processor and I/O bandwidth required to initialize the array and further reduces the time to initialize a RAID array. In a different aspect, a method is provided for efficiently selecting a host write process for optimal data redundancy and performance in a RAID array.

Abstract: A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.

Abstract: A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups; determining an order of the plurality of groups to be shortened, based on a ratio of a number of bits to be shortened to a number of bits to be punctured; determining a length of an information word to be obtained by shortening the plurality of groups; shortening the plurality of groups on a group basis in the determined order based on the determined length of the information word; and LDPC-encoding a shortened information word.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period.

Abstract: The present techniques provide systems and methods for decoding a data signal with a control bit to improve bit estimation. The techniques in one embodiment involve using decoding algorithms to estimate the a posteriori state probabilities and the a posteriori transition probabilities of the data encoding, and estimating bit state probabilities. The techniques further involve using a control bit in the bit stream and comparing the estimation of the control bit state in the segment of the bit stream with a test control bit determined based on an average of bit states from the encoded segment of the bit stream. If the estimation of the control bit and the test control bit are not equal, the state of the bit estimate with the lowest confidence probability will be changed.

Abstract: A Berger invert code encoding and decoding method is disclosed. The method includes steps: Selecting logic value 0 or 1 to represent the stable and unstable states respectively. Calculating the stable bit count and the unstable-bit count of the codeword. Checking whether the unstable bit count is larger than the stable bit count or not. Setting the Invert Bit to the unstable state for indicating the inversion when the unstable bit count is larger than the stable bit count. Resetting the Invert Bit to the stable state for indicating the non-inversion when the unstable bit count is not larger than the stable bit count. Concatenating the Invert Bit to the codeword as a new codeword.

Abstract: Block modulus coding (BMC) systems implement block coding on non-binary modulus m symbols, where m is greater than 2. BMC systems can be used for, among other things, forward error correction (FEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data is represented by non-binary symbols that may be corrupted by burst errors. The block coding is preferably performed using a distributed arrangement of block encoders or decoders. A distributed block modulus encoder (DBME) encodes sequential source data symbols of modulus m with a plurality of sequential block encoders to produce interleaved parity codewords. The codewords utilize modulus m symbols where the medium can reliably resolve m symbol states.

Abstract: The invention concerns a method for processing a signal using an approximate MAP (maximum a posteriori) algorithm for determining a likelihood ratio ?kX of a set of states X of a lattice at a time k, with each of said states being associated at least one intermediate variable belonging to a group comprising a so-called forward variable and a so-called backward variable, propagated by said MAP algorithm and recursively calculated respectively in a direct orientation and in an indirect orientation at said time k relative to said lattice. The invention is characterized in that said process comprises a step which consists in reducing the number of selected states by said MAP algorithm so as to calculate said likelihood ratio, and, for at least some unselected states, in assigning to said forward variable and/or said backward variable at least one specific value, to calculate an approximate likelihood ratio.

Abstract: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.

Abstract: Disclosed is an apparatus and method for detecting errors in one-hot words, which have only a single bit set in the absence of errors. The apparatus comprises a plurality of input signal lines, a plurality of switching devices, a plurality of intermediate signal lines, and logic circuitry. The switching devices are connected to the input signal lines. The intermediate signal lines are also connected to the switching devices. The connection is in such a way that when a particular input signal line is set, all intermediate signal lines connected by a switching device to that particular input signal line are forced to a predetermined logic state. The intermediate signal lines are input to the logic circuitry, which outputs a signal indicative of whether at least two of the plurality of input signal lines are set. The method detects non-one-hot conditions in a group of M bits.

Abstract: A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

Abstract: An apparatus for encoding digital data for storage on a data storage medium includes a non-deterministic randomizer code generator. The randomizer code generator may select different randomizer codes for different portions of the data to be stored. The randomizer code used to randomize a given portion of the data may be stored on the media for use in subsequent data retrieval.