Error/fault Detection Technique Patents (Class 714/799)
  • Patent number: 11436081
    Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanbyeul Na, Jaehun Jang, Hongrak Son
  • Patent number: 11392449
    Abstract: The present invention concerns an anti-tearing protection system (1) for a non-volatile memory (3) comprising a first memory block (5) and a second memory block (7), the first and second memory blocks (5, 7) being arranged to store a data set comprising user data and an error detection code obtained based on the user data. The first and second memory blocks (5, 7) can be read in a first read mode for determining logic states of data elements comprised in the data set according to the first read mode. The user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value. The first and second memory blocks (5, 7) can further be read in a second read mode for determining the logic states of the data elements comprised in data set according to the second read mode.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 19, 2022
    Assignee: EM MICROELECTRONIC-MARIN S.A.
    Inventors: Tomas Novak, Filippo Marinelli
  • Patent number: 11354361
    Abstract: Document discrepancy determination and mitigation can include marking a fragment of a first document and a corresponding fragment of a second document in response to determining a dependency between the first document and the second document. A discrepancy probability with respect to the first document and the second document can be identified based on a discrepancy measure, which can be determined by comparing the marking of the fragment of the first document and the marking of the corresponding fragment of the second document. One or more discrepancy mitigation procedures can be initiated in response to the discrepancy measure exceeding a predetermined threshold.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul R. Bastide, Matthew E. Broomhall, Robert E. Loredo
  • Patent number: 11327863
    Abstract: An electronic control device includes: a diagnostic circuit unit configured to be reconfigurable so as to be used to diagnose each of a plurality of processing circuits that processes an input signal; an input data storage unit configured to temporarily store the input signal; an output data storage unit configured to temporarily store an output signal of the plurality of processing circuits; a reconfiguration control unit configured to sequentially write, to the diagnostic circuit unit as circuit configuration information, circuit information the same as that of the plurality of processing circuits; a diagnostic control unit configured to cause the diagnostic circuit unit to perform calculation using the input signal stored in the input data storage unit when the circuit configuration information is written to the diagnostic circuit unit; and a comparator configured to diagnose each of the plurality of processing circuits by comparing output of the diagnostic circuit unit and the output signal stored in the
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 10, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Kenichi Shimbo, Tadanobu Toba, Hideyuki Sakamoto
  • Patent number: 11322218
    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Donald Martin Morgan, Victor Wong, Jongtae Kwak
  • Patent number: 11263104
    Abstract: In some examples, a system is to, given an anomaly score threshold over which at least one anomalous point is to be observed in a test set of points with a specified probability, determine, using raw anomaly scores for a training set of points, a first mapping between raw anomaly scores in a first range and first transformed anomaly scores using a first transformation technique. The system is to determine, using the raw anomaly scores for the training set of points, a second mapping between raw anomaly scores in a second range greater than the first range and second transformed anomaly scores using a second transformation technique different from the first transformation technique. The system is to use the first mapping and the second mapping to detect an anomaly in a computing environment based on the test set of points.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 1, 2022
    Assignee: Micro Focus LLC
    Inventors: Manish Marwah, Andrey Simanovsky
  • Patent number: 11245569
    Abstract: A method and system for adding a notification to an error message. A first node and a second node are positioned in a communication network, and the first node is different from the second node. The first node is configured to process a network message before sending the network message to the second node. The first node encounters an error when processing the network message, and, before sending the network message to the second node, writes a reason of the error in a header section of the network message. The first node is configured to send the network message to the second node with the header section.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: February 8, 2022
    Assignee: T-Mobile USA, Inc.
    Inventor: Mayank Kaul
  • Patent number: 11206421
    Abstract: A prediction information deriving unit derives the inter-prediction information candidates from inter-prediction information of a prediction block neighboring to a coding target prediction block or a prediction block present at the same position as or near the coding target prediction block in a coded picture at a temporally different position from the coding target prediction block. A candidate supplementing unit supplements inter-prediction information candidates having the same prediction mode, reference index, and motion vector until the number of inter-prediction information candidates reaches the designated number of candidates when the number of inter-prediction information candidates is smaller than the designated number of candidates.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 21, 2021
    Assignee: JVCKENWOOD Corporation
    Inventors: Hiroya Nakamura, Shigeru Fukushima, Hideki Takehara
  • Patent number: 11200461
    Abstract: Logic may identify feature contributions to erroneous predictions by predictive models. Logic may provide a set of two or more models. Each model may train based on a training dataset and test based on a testing dataset and two or more models may be unique. Logic may test the set during a monitoring period. Logic may perform residual modeling on each model in the set during the monitoring period and may determine a list of input features that contribute to a residual of each model of the set. A residual comprises a difference between a predicted result and an expected result. Logic may generate a combined list of the input features from the set and may rank the input features. Logic may perform a voting process to generate the ranks for the input features. And logic may classify features as exogenous or endogenous based on a threshold and the ranks.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 14, 2021
    Assignee: Capital One Services, LLC
    Inventors: Nanda Kumar Trichy Rajarathinam, Evan Engel, Madhav Khosla, Leela Prabhu, Kevin Wu
  • Patent number: 11169500
    Abstract: Provided is a control system, comprising: a processing unit which executes a user program; one or a plurality of function units; one or a plurality of communication units which relay data between the processing unit and the one or the plurality of function units; and a reflection means which, when in the user program a variable is designated which has been associated with any of the data which the function units retain and which denotes the validity of the data, reflects, as the value which the variable denotes, a result of having aggregated states of each of the communication units which are present upon a transmission path from the function units which retain the designated data to the processing unit.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 9, 2021
    Assignee: OMRON Corporation
    Inventors: Kazunari Miyake, Shigeyuki Eguchi, Takamasa Ueda
  • Patent number: 11165772
    Abstract: A network node is configured to enable authentication of a user of a client device based on biometric data captured by the client device. The network node receives, from the client device, a request to authenticate a user that includes a first set of transformed biometric data transformed with a first secret feature transform key shared with the client device; fetches, from a secure end-user repository, a second set of enrolled transformed biometric data associated with the first set of transformed biometric data and a second secret feature transform key with which the second set of biometric data was transformed at enrolment of the transformed biometric data; and submits the second set of transformed biometric data and the second secret feature transform key over a secure communication channel to the client device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 2, 2021
    Assignee: FINGERPRINT CARDS AB
    Inventor: Christian Gehrmann
  • Patent number: 11128321
    Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Min Shin, Beom Kyu Shin, Heon Hwa Cheong, Jun Jin Kong, Hong Rak Son, Yeong Geol Song, Se Jin Lim
  • Patent number: 11121895
    Abstract: A repeater includes a reception unit, a permission signal generating unit that detects the state of the pulses of the signal, and generates a permission signal that permits a relay of the signal when the permission signal generating unit detects the pulses, and that inhibits the relay of the signal when the permission signal generating unit detects an end of the pulses, and a transmission unit. When detecting the end of the pulses, for the permission signal, the permission signal generating unit sets a pulse re-input monitoring period for determining whether or not the pulses of the signal are re-detected. When detecting the pulses of the signal during the pulse re-input monitoring period, the permission signal generating unit determines that the signal continues, and when not detecting the pulses of the signal, the permission signal generating units determines that the signal ends.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihiro Nakahara, Shingo Yamamoto
  • Patent number: 11119854
    Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 14, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Yu-Kuo Yang, Takao Akaogi, Pauling Chen
  • Patent number: 11070402
    Abstract: A receiving apparatus includes a first sample circuit configured to extract first binary data based on a first voltage and a clock timing of a received signal, a second sample circuit configured to extract second binary data based on an adjustable second voltage and a clock timing of the received signal, and a waveform processor configured to acquire a plurality of the second binary data from the second sample circuit using a pattern, the pattern corresponding to the first binary data extracted by the first sample circuit with consecutive sampling timings, determine an appearance frequency of the received signal based on the plurality of second binary data and the first binary data, and generate waveform information of the received signal according to the determined appearance frequency.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takaya Yamamoto
  • Patent number: 11031961
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which optimize one or more metrics of a communication system by intentionally changing symbols in a bitstream after encoding by an error correction coder, but prior to transmission. The symbols may be changed to meet a communication metric optimization goal, such as decreasing a high PAPR, reducing an error rate, reducing an average power level (to save battery), or altering some other communication metric. The symbol that is intentionally changed is then detected by the receiver as an error and corrected by the receiver utilizing the error correction coding.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Amer Aref Hassan
  • Patent number: 11023323
    Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Rao, Karthik Ramasubramanian, Brian Paul Ginsburg
  • Patent number: 10972131
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10901843
    Abstract: Disclosed herein are techniques for use in managing data storage. For example, in one embodiment, the techniques comprise determining a size of the write request. The size of the write request equating to half or more non-parity data portions in a full stripe of data but less than all non-parity data portions in the full stripe.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Marc Cassano, Robert Foley, Daniel Cummins, Socheavy Heng
  • Patent number: 10878265
    Abstract: An image processing device includes an importance calculating unit, a capturing-direction acquiring unit, a parameter estimating unit, and an important-area setting unit. The importance calculating unit is configured to calculate importance of each of a plurality of positions in an image. The capturing-direction acquiring unit is configured to acquire, for each of the positions, a capturing direction in a three-dimensional space. The parameter estimating unit is configured to regard importance distributions in respective capturing directions as a mixture distribution made up of element distributions, so as to estimate a parameter of each of the element distributions. The important-area setting unit is configured to set an important area from the image in accordance with the parameter.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: December 29, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventor: Takayuki Hara
  • Patent number: 10863200
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for storing, in memory, at least one master forward transform matrix comprising signed constants having a defined number of precision bits and a sign bit and determining, by processing circuitry, which forward transform matrix to use to perform a transformation based on at least a transform unit size. Further, various techniques may include performing, by the processing circuitry, the transformation on residuals of pixel values of a frame using one of the at least one master forward transform matrix or a forward transform matrix derived from one of the master forward transform matrix at least partially based on the determination.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventor: Douglas L. Li
  • Patent number: 10791336
    Abstract: A prediction information deriving unit derives the inter-prediction information candidates from inter-prediction information of a prediction block neighboring to a coding target prediction block or a prediction block present at the same position as or near the coding target prediction block in a coded picture at a temporally different position from the coding target prediction block. A candidate supplementing unit supplements inter-prediction information candidates having the same prediction mode, reference index, and motion vector until the number of inter-prediction information candidates reaches the designated number of candidates when the number of inter-prediction information candidates is smaller than the designated number of candidates.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 29, 2020
    Assignee: JVCKENWOOD CORPORATION
    Inventors: Hiroya Nakamura, Shigeru Fukushima, Hideki Takehara
  • Patent number: 10761966
    Abstract: A method of generating program analysis data for analysing the operation of a computer program. The method comprises, executing an instrumented process of the computer program to define a reference execution of the program, intercepting a call to a library function by the instrumented process, executing the library function in an uninstrumented process, for the uninstrumented process, capturing in a log, only data generated by or modified through the execution of the library function required by the instrumented process to continue execution of the program, and wherein the captured log is arranged to enable deterministically reproducing the effect of the library function call on the instrumented process upon re-running of the reference execution based upon the captured log to generate the program analysis data.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 1, 2020
    Assignee: Undo Ltd.
    Inventors: Nicholas Peter Bull, Julian Philip Smith, Gregory Edward Warwick Law
  • Patent number: 10700714
    Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Min Shin, Beom Kyu Shin, Heon Hwa Cheong, Jun Jin Kong, Hong Rak Son, Yeong Geol Song, Se Jin Lim
  • Patent number: 10684909
    Abstract: A system and method that automatically detects anomalies in a cloud service system on an ongoing basis and which can be used to trigger live migration of cloud services includes a cloud server system configured to provide a plurality of virtualized cloud services through processes running over a set of virtual machines hosted on the cloud server system, and a processor which receives data related to the operations of the virtual machines and determines whether any of the virtual machines are exhibiting anomalous behavior. The processor applies a Kalman Filter to make predictions on the future state and covariance of the virtual machines and then calculates the log likelihood of the predicted values. If the predicted values deemed to be very unlikely, then the processor signals that an anomaly has occurred.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 16, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Michael A. August, Mamadou H. Diallo, Dillon P. Glasser, Christopher T. Graves, Roger A. Hallman, Scott M. Slayback
  • Patent number: 10671508
    Abstract: Some examples described herein relate to testing of a cloud service. In an example, a cloud service to be tested may be deployed in a cloud system. A test load may be applied to the cloud service. Upon application of the test load to the cloud service, a determination may be made whether a performance metric related to the cloud service meets a pre-configured criterion. If the performance metric related to the cloud service meets a pre-configured criterion, the cloud service may be scaled. Operations of applying, determining, and scaling may iterated until an end condition is met, wherein the test load applied to the cloud service may vary after each iteration operation.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 2, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Upendra Gopu, Anusha Kadambala, Siva Subramaniam Manickam
  • Patent number: 10635522
    Abstract: A processor-fault reproduction method includes: determining a heating time of a processor taken using a heating program which heats the processor to a fault occurrence temperature when a fault occurs from a current temperature based on first information regarding the current temperature of the processor, second information regarding a power consumption value and a temperature of the processor before the fault occurs and a refrigerant temperature of a cooling medium to cool the processor, third information regarding the fault occurrence temperature, and fourth information regarding a power consumption value of the processor during execution of the heating program; determining an execution time by adding a fault reproduction time taken by a fault reproducing program which reproduces a state of the processor when the fault occurs to the heating time; and reporting the execution time to a job scheduler with a request to execute the heating and fault reproducing programs.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Jumpei Kubota, Tsuyoshi Hashimoto
  • Patent number: 10623001
    Abstract: Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10608790
    Abstract: Various embodiments disclosed herein provide for a transmission system using codeblock segmentation that does not have to retransmit each of the codeblock segments if one of the codeblock segments is determined to have an error at the receiver. The transmitter segments a transport block into a group of codeblock segments, each having respective cyclic redundancy check bits. The receiver receives the group of codeblock segments, and during decoding, if it is determined that one of the segments have an error, instead of just sending back to the transmitter a negative acknowledgement (NAK) the receiver can send back a NAK as well as an indicator of which segment was in error. The transmitter can then resend just the segment in error in order to improve efficiency and decrease power requirements.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 31, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventor: SaiRamesh Nammi
  • Patent number: 10514861
    Abstract: Methods and apparatus are provided for reporting space savings due to pattern matching in storage systems. An exemplary method comprises, when a given allocation unit in a storage system matches one or more predefined patterns, (i) setting a corresponding pattern flag for the given allocation unit, and (ii) incrementing at least one pattern counter; generating at least one snapshot of at least a portion of a file comprising the given allocation unit; and determining a data reduction attributed to pattern matching based on the at least one pattern counter, wherein the one or more predefined patterns in the at least one snapshot are excluded from the data reduction attributed to pattern matching.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 24, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ivan Basov, Ahsan Rashid, Michal Marko, Walter Forrester
  • Patent number: 10498662
    Abstract: A method for packet field suppression in broadband wireless communication is provided. Values for packet suppression can be learned and subsequently used for suppression. The learning can involve determining a new packet field suppression rule and a packet field suppression index. Packets can be suppressed based on the learned values.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 3, 2019
    Assignee: Ondas Networks Inc.
    Inventors: Menashe Shahar, Guy Robert Simpson
  • Patent number: 10489238
    Abstract: A client management server manages client devices deployed throughout an enterprise facility that may be used for various applications such as wayfinders and internal and external meeting room computers. The client management receives screenshots from the client devices and applies a classifier to classify an operating state of each device as corresponding to a normal operating state or an error state. If the operating state is classified as corresponding to the error state, a remedial action is triggered. The classifier may be a machine trained model that is trained using supervised or unsupervised learning, including by simulating errors on the clients.
    Type: Grant
    Filed: October 28, 2017
    Date of Patent: November 26, 2019
    Assignee: Facebook, Inc.
    Inventors: Oliver Pell, Davide Guerri
  • Patent number: 10469104
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 10445181
    Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Inon Cohen, Asaf Gueta
  • Patent number: 10425107
    Abstract: Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 24, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Louis-Philippe Hamelin
  • Patent number: 10382554
    Abstract: Inter-zone network traffic generated during deletion of a data chunk that has been replicated by employing geographically distributed (GEO) erasure coding is reduced. In one aspect, if a data chunk is to be deleted, partial coding chunks are generated by a source zone and provided to destination zones that store complete coding chunks for updating the complete coding chunks based on combining them with the received partial coding chunks. In another aspect, if a first data chunk is to be deleted and a second data chunk is to be replicated, partial coding chunks are generated by the source zone for each data chunk. Further, the partial coding chunks created for different data chunks can be combined to generate transforming chunks, which can then be transferred to the destination zones. The destination zones can then update the complete coding chunks based on combining them with the received transforming chunks.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 13, 2019
    Assignee: EMC CORPORATION
    Inventors: Mikhail Danilov, Konstantin Buinov
  • Patent number: 10331514
    Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy
  • Patent number: 10313054
    Abstract: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, a device encodes information using a low density parity check (LDPC) code to generate an LDPC coded signal and transmits the LDPC coded signal to another communication device. in other examples, a device receives an LDPC coded signal from another communication device and decodes the LDPC coded signal using an LDPC matrix. The LDPC matrix includes a left hand side matrix and a right hand side matrix (e.g., having CSI (Cyclic Shifted Identity) sub-matrices on a main diagonal and another diagonal adjacently located to the main diagonal).
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 4, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Ba-Zhong Shen, Matthias Korb, Andrew John Blanksby, Ron Porat
  • Patent number: 10298430
    Abstract: A transmission apparatus includes a transmission signal generator which, in operation, generates a transmission signal having an aggregate physical layer protocol data unit (PPDU) that includes a legacy preamble, a legacy header, a non-legacy preamble, a plurality of non-legacy headers and a plurality of data fields; and a transmitter which, in operation, transmits the generated transmission signal, wherein the legacy preamble, the legacy header and the plurality of non-legacy headers are transmitted using a standard bandwidth, the non-legacy preamble and the plurality of data fields are transmitted using a variable bandwidth that is larger than the standard bandwidth and wherein a plurality of sets of each of the plurality of non-legacy headers and each of the plurality of data fields are transmitted sequentially in a time domain.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Lei Huang, Hong Cheng Michael Sim, Takenori Sakamoto
  • Patent number: 10269194
    Abstract: It is possible to achieve monitoring of a processor element while suppressing the cost. A multiprocessor system 1 includes a bus mechanism including a storage unit 6 configured to store bus access information when a first processor element 2 has executed a process to be monitored, a requesting unit 7 configured to request a second processor element 3 to execute a monitoring process after the first processor element 2 has completed the execution of the process to be monitored, and a comparing unit 8 configured to compare bus access information regarding access of the first processor element 2 stored in the storage unit 6 with bus access information input from the second processor element 3 when the second processor element 3 has executed the monitoring process. The second processor element 3 executes the monitoring process in an idle time.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naotaka Kawakami
  • Patent number: 10256986
    Abstract: A system and method for recovering missed Multimedia Broadcast and Multicast Service (MBMS) data frames in a Multicast Broadcast Single Frequency Network (MBSFN) is provided. The method includes storing a first set of Service Data Units (SDUs) in a first Radio Link Control (RLC) buffer, wherein the first set of SDUs is broadcasted using a first set of MBMS data frames from a first eNB, storing a second set of SDUs in a second RLC buffer, wherein the second set of SDUs is broadcasted using a second set of MBMS data frames from a second eNB, and comparing the first set of MBMS data frames associated with the first set of SDUs with the second set of MBMS data frames associated with the second set of SDUs to recover the missed MBMS data frame in the first set of RLC SDUs received from the first eNB.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Balaji Srinivasan Thiruvenkatachari, Sivashankar Sekar
  • Patent number: 10193793
    Abstract: The present technology relates to a browser apparatus, a recording medium, a server apparatus, and an information processing method by which a load in viewing web content can be reduced. Provided is a browser apparatus that implements a web browser including a unicast communication function section that sends a request to a web site and receives web content from the web site using a unicast protocol, and a multicast communication function section that receives web content multicast-distributed using a multicast protocol. The browser apparatus includes a control unit that controls, in response to an external input, the unicast communication function section of the web browser to send a request to a web site and receive web content from the web site using the unicast protocol.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 29, 2019
    Assignee: SONY CORPORATION
    Inventors: Tetsuo Yutani, Takashi Togame
  • Patent number: 10165470
    Abstract: Apparatuses, methods, and computer readable media are disclosed. A HE station may include circuitry. The circuitry may be configured to: generate a HE packet with a short preamble format or a long preamble format, wherein the HE packet comprises one or more legacy signal (L-SIG) fields followed by one or more HE signal fields (HE-SIG) and an HE long-training field (HE-LTF); and configure the HE packet to indicate whether the HE packet is configured with the short preamble format or the long preamble format. The HE packet may be configured with the short preamble format or the long preamble format based on one from the following group: a symbol after the L-SIG fields, a L-SIG polarity of a repeated L-SIG, a number of times the L-SIG fields is repeated, or a length field of one of the one or more L-SIG fields.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel IP Corporation
    Inventors: Shahrnaz Azizi, Robert J. Stacey, Thomas J. Kenney, Eldad Perahia
  • Patent number: 10157013
    Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed. The output storage values and the compressed confidence levels are transferred from the memory cells over an interface to a memory controller.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: December 18, 2018
    Assignee: Apple Inc.
    Inventors: Uri Perlmutter, Dotan Sokolov, Ofir Shalvi, Oren Golov
  • Patent number: 10120751
    Abstract: Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jawad B. Khan, Anand S. Ramalingam, Pranav Kalavade
  • Patent number: 10063239
    Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 28, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Bruno Nicolas
  • Patent number: 10063557
    Abstract: Some embodiments of the invention provide a program for recovering access to an account. The program receives an access recovery parameter (ARP) after providing a first credential to log into an account and providing a notification of a second credential necessary for accessing another resource. The program then receives a request to modify the first credential and receives the second credential. Next, after authenticating the second credential, the program uses the ARP to modify the first credential without providing the first credential.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 28, 2018
    Assignee: Apple Inc.
    Inventors: Ivan Krstic, James Wilson, Eric Daniel Friedman, Selvarajan Subramaniam, Patrice O. Gautier, John Patrick Gates, Ramarathnam Santhanagopal, Prabhakaran Vaidyanathaswami, Sudhakar Mambakkam, Raghunandan Pai, Karthik Narayanan
  • Patent number: 10055141
    Abstract: Provided is a storage device, a liquid container and a host device that appropriately control whether or not writing is to be performed with an efficient data configuration. The storage device 100 includes a control unit 110 that performs processing for communication with a host device 400, a storage unit 120, and a storage control unit 130 that performs access control on the storage unit 120. The control unit 110 receives a write data packet from the host device 400, and if a data pattern of write data included in the write data packet and additional data is judged as not matching a specific pattern, makes update instruction of address information and write instruction regarding write data to the storage control unit 130. If judged as matching, the control unit 110 does not make a write instruction regarding the write data, while making an update instruction of the address information.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 21, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Nakano
  • Patent number: 10042991
    Abstract: A method and apparatus for easily restricting a use right and improving use convenience in a mobile terminal are provided. The method includes displaying a profile list for selecting a set operation mode of the mobile terminal from the displayed profile list; setting an operation mode of the mobile terminal as the selected operation mode, when the set operation mode is selected from the displayed profile list; and displaying a screen associated with the selected operation mode, wherein the set operation mode includes an open mode to use all functions of the mobile terminal and a limited mode to use only set functions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Joo Park, Se Hwan Park
  • Patent number: 10015514
    Abstract: A motion vector predictor candidate generating unit makes a prediction based on a motion vector of one of coded neighboring blocks that are neighboring to a coding target block in space or time and generates a plurality of motion vector predictor candidates. A motion vector predictor redundant candidate removing unit removes the motion vector predictor candidates having identity among the motion vector predictor candidates predicted based on a coded neighboring block that is neighboring in space from a motion vector predictor candidate list with at least one being left. A motion vector predictor selecting unit selects a motion vector predictor from the plurality of motion vector predictor candidates. A first bitstream generating unit codes information representing the selected motion vector predictor.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 3, 2018
    Assignee: JVC KENWOOD Corporation
    Inventors: Shigeru Fukushima, Hiroya Nakamura, Hideki Takehara