Error/fault Detection Technique Patents (Class 714/799)
  • Patent number: 11934264
    Abstract: Error correction code (ECC) coding for key-value data storage devices. In one embodiment, a controller includes a memory interface configured to interface with a memory; an ECC engine configured to perform ECC coding on data stored in memory; a controller memory including a flash translation layer and a namespace database; and an electronic processor. The electronic processor is configured to receive data to be stored, separate the data into a plurality of sub-code blocks, and allocate parity bits to each sub-code block of the plurality of sub-code blocks.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, David Avraham, Alexander Bazarsky
  • Patent number: 11867726
    Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Stewart, Eric J. Stave, Matthew A. Prather
  • Patent number: 11854752
    Abstract: A relay state prediction device according to the present invention includes: a voltage value acquisition unit that measures every moment a detected voltage detected from two ends of a shunt resistor; a voltage value difference calculation unit that calculates a voltage value difference between a first voltage value of when the detected voltage becomes minimum by an armature starting displacement after a primary-side switch is turned off and a second voltage value of when secondary-side contacts are opened; a slope calculation unit that calculates a slope at which the voltage value difference decreases as the secondary-side contacts are repeatedly opened and closed in response to the primary-side switch repeatedly turning on and off; and a state prediction unit that predicts the number of openable and closable times from the present time until the voltage value difference reaches a predetermined threshold value based on the voltage value difference at the present time and the decreasing slope.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: December 26, 2023
    Assignee: OMRON CORPORATION
    Inventors: Shinya Matsuo, Takuya Yamazaki
  • Patent number: 11853159
    Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Space-time correlated edges and other edges are included in the matching graph and weighted based at least in part on confidence values for qubits forming the respective edges.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh, Fernando Brandao
  • Patent number: 11831898
    Abstract: A prediction information deriving unit derives the inter-prediction information candidates from inter-prediction information of a prediction block neighboring to a coding target prediction block or a prediction block present at the same position as or near the coding target prediction block in a coded picture at a temporally different position from the coding target prediction block. A candidate supplementing unit supplements inter-prediction information candidates having the same prediction mode, reference index, and motion vector until the number of inter-prediction information candidates reaches the designated number of candidates when the number of inter-prediction information candidates is smaller than the designated number of candidates.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: November 28, 2023
    Assignee: JVCKENWOOD Corporation
    Inventors: Hiroya Nakamura, Shigeru Fukushima, Hideki Takehara
  • Patent number: 11817883
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine an error correction code (ECC) code length for KV pair data and/or an ECC code rate for the KV pair data, where the ECC code length and the ECC code rate are selected according to a value length and decoding capability of the KV pair data, generate ECC parity based on the selecting, and program the KV pair data and the generated ECC parity to the memory device.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Avraham, Ran Zamir, Alexander Bazarsky
  • Patent number: 11804948
    Abstract: Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 31, 2023
    Assignee: Hughes Network Systems, LLC
    Inventor: Rohit Iyer Seshadri
  • Patent number: 11803127
    Abstract: A method for determining a root cause affecting yield in a process for manufacturing devices on a substrate, the method including: obtaining yield distribution data including a distribution of a yield parameter across the substrate or part thereof; obtaining sets of metrology data, each set including a spatial variation of a process parameter over the substrate or part thereof corresponding to a different layer of the substrate; comparing the yield distribution data and metrology data based on a similarity metric describing a spatial similarity between the yield distribution data and an individual set out of the sets of the metrology data; and determining a first similar set of metrology data out of the sets of metrology data, being the first set of metrology data in terms of processing order for the corresponding layers, which is determined to be similar to the yield distribution data.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 31, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Chenxi Lin, Cyrus Emil Tabery, Hakki Erg√ľn Cekli, Simon Philip Spencer Hastings, Boris Menchtchikov, Yi Zou, Yana Cheng, Maxime Philippe Frederic Genin, Tzu-Chao Chen, Davit Harutyunyan, Youping Zhang
  • Patent number: 11738459
    Abstract: Operation information on a robot is recorded in a temporary data recorder continually only for a predetermined period. The operation information for one cycle during a normal operation of the robot is retrieved from the temporary data recorder, and is recorded in a normal-state data recorder. If a storage control section determines that a predetermined trigger condition has occurred, some pieces of the operation information recorded in the temporary data recorder are recorded in the trigger-state data recorder. An operation information display displays the operation information in a normal state and the operation information in a trigger state so that these pieces of the operation information can be compared with each other.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 29, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Toshinari Mohri
  • Patent number: 11640372
    Abstract: Systems and apparatus for implementation and management of a singularity image format file in a computer system and methods for making and using the same. In various embodiment, these technologies are used to facilitate storage of all data related to a container in a single file among other things.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 2, 2023
    Assignee: SYLABS INC.
    Inventor: Yannick Cote
  • Patent number: 11604692
    Abstract: A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: March 14, 2023
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Yueer Shan, Yanfeng Xu, Jicong Fan, Zhan Jing
  • Patent number: 11539514
    Abstract: A log management system includes a first secret splitting module to split the log data generated regularly or intermittently into a plurality of split log fragments including a split log fragment for remote transmission per predetermined unit using secret splitting scheme, the split log fragment for remote transmission having a smaller size than remaining split log fragments; a first communication control module to transmit the split log fragment for remote transmission to a remote apparatus; a second communication control module to receive, in response to occurrence of an event, one or more remaining split log fragments corresponding to the log data to be partially recovered out of the remaining split log fragments accumulated by a local apparatus; and a second secret splitting module to recover the log data from the one or more remaining split log fragments and the split log fragment for remote transmission using the secret splitting scheme.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 27, 2022
    Assignees: UHURU CORPORATION, ZENMUTECH, INC
    Inventors: Koyo Takenoshita, Kiyoshi Tomomura
  • Patent number: 11523389
    Abstract: An operation method of a first distributed terminal, in a synchronized wireless distributed communication system which has a plurality of communication resources configured with a plurality of channels having different center frequencies and includes the first distributed terminal and a second distributed terminal, may comprise receiving slots mapped to the communication resources in a resource allocation channel having a center frequency independent from the plurality of channels; measuring communication environments of the communication resources by using a mapping relationship between the received slots of the resource allocation channel and the communication resources; selecting a first communication resource to be allocated using the measured communication environments of the communication resources; allocating the selected first communication resource; and continuously occupying the allocated first communication resource.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 6, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Hyun Gu Hwang
  • Patent number: 11436081
    Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanbyeul Na, Jaehun Jang, Hongrak Son
  • Patent number: 11392449
    Abstract: The present invention concerns an anti-tearing protection system (1) for a non-volatile memory (3) comprising a first memory block (5) and a second memory block (7), the first and second memory blocks (5, 7) being arranged to store a data set comprising user data and an error detection code obtained based on the user data. The first and second memory blocks (5, 7) can be read in a first read mode for determining logic states of data elements comprised in the data set according to the first read mode. The user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value. The first and second memory blocks (5, 7) can further be read in a second read mode for determining the logic states of the data elements comprised in data set according to the second read mode.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 19, 2022
    Assignee: EM MICROELECTRONIC-MARIN S.A.
    Inventors: Tomas Novak, Filippo Marinelli
  • Patent number: 11354361
    Abstract: Document discrepancy determination and mitigation can include marking a fragment of a first document and a corresponding fragment of a second document in response to determining a dependency between the first document and the second document. A discrepancy probability with respect to the first document and the second document can be identified based on a discrepancy measure, which can be determined by comparing the marking of the fragment of the first document and the marking of the corresponding fragment of the second document. One or more discrepancy mitigation procedures can be initiated in response to the discrepancy measure exceeding a predetermined threshold.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul R. Bastide, Matthew E. Broomhall, Robert E. Loredo
  • Patent number: 11327863
    Abstract: An electronic control device includes: a diagnostic circuit unit configured to be reconfigurable so as to be used to diagnose each of a plurality of processing circuits that processes an input signal; an input data storage unit configured to temporarily store the input signal; an output data storage unit configured to temporarily store an output signal of the plurality of processing circuits; a reconfiguration control unit configured to sequentially write, to the diagnostic circuit unit as circuit configuration information, circuit information the same as that of the plurality of processing circuits; a diagnostic control unit configured to cause the diagnostic circuit unit to perform calculation using the input signal stored in the input data storage unit when the circuit configuration information is written to the diagnostic circuit unit; and a comparator configured to diagnose each of the plurality of processing circuits by comparing output of the diagnostic circuit unit and the output signal stored in the
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 10, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Kenichi Shimbo, Tadanobu Toba, Hideyuki Sakamoto
  • Patent number: 11322218
    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nobuo Yamamoto, Donald Martin Morgan, Victor Wong, Jongtae Kwak
  • Patent number: 11263104
    Abstract: In some examples, a system is to, given an anomaly score threshold over which at least one anomalous point is to be observed in a test set of points with a specified probability, determine, using raw anomaly scores for a training set of points, a first mapping between raw anomaly scores in a first range and first transformed anomaly scores using a first transformation technique. The system is to determine, using the raw anomaly scores for the training set of points, a second mapping between raw anomaly scores in a second range greater than the first range and second transformed anomaly scores using a second transformation technique different from the first transformation technique. The system is to use the first mapping and the second mapping to detect an anomaly in a computing environment based on the test set of points.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 1, 2022
    Assignee: Micro Focus LLC
    Inventors: Manish Marwah, Andrey Simanovsky
  • Patent number: 11245569
    Abstract: A method and system for adding a notification to an error message. A first node and a second node are positioned in a communication network, and the first node is different from the second node. The first node is configured to process a network message before sending the network message to the second node. The first node encounters an error when processing the network message, and, before sending the network message to the second node, writes a reason of the error in a header section of the network message. The first node is configured to send the network message to the second node with the header section.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: February 8, 2022
    Assignee: T-Mobile USA, Inc.
    Inventor: Mayank Kaul
  • Patent number: 11206421
    Abstract: A prediction information deriving unit derives the inter-prediction information candidates from inter-prediction information of a prediction block neighboring to a coding target prediction block or a prediction block present at the same position as or near the coding target prediction block in a coded picture at a temporally different position from the coding target prediction block. A candidate supplementing unit supplements inter-prediction information candidates having the same prediction mode, reference index, and motion vector until the number of inter-prediction information candidates reaches the designated number of candidates when the number of inter-prediction information candidates is smaller than the designated number of candidates.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 21, 2021
    Assignee: JVCKENWOOD Corporation
    Inventors: Hiroya Nakamura, Shigeru Fukushima, Hideki Takehara
  • Patent number: 11200461
    Abstract: Logic may identify feature contributions to erroneous predictions by predictive models. Logic may provide a set of two or more models. Each model may train based on a training dataset and test based on a testing dataset and two or more models may be unique. Logic may test the set during a monitoring period. Logic may perform residual modeling on each model in the set during the monitoring period and may determine a list of input features that contribute to a residual of each model of the set. A residual comprises a difference between a predicted result and an expected result. Logic may generate a combined list of the input features from the set and may rank the input features. Logic may perform a voting process to generate the ranks for the input features. And logic may classify features as exogenous or endogenous based on a threshold and the ranks.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 14, 2021
    Assignee: Capital One Services, LLC
    Inventors: Nanda Kumar Trichy Rajarathinam, Evan Engel, Madhav Khosla, Leela Prabhu, Kevin Wu
  • Patent number: 11169500
    Abstract: Provided is a control system, comprising: a processing unit which executes a user program; one or a plurality of function units; one or a plurality of communication units which relay data between the processing unit and the one or the plurality of function units; and a reflection means which, when in the user program a variable is designated which has been associated with any of the data which the function units retain and which denotes the validity of the data, reflects, as the value which the variable denotes, a result of having aggregated states of each of the communication units which are present upon a transmission path from the function units which retain the designated data to the processing unit.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 9, 2021
    Assignee: OMRON Corporation
    Inventors: Kazunari Miyake, Shigeyuki Eguchi, Takamasa Ueda
  • Patent number: 11165772
    Abstract: A network node is configured to enable authentication of a user of a client device based on biometric data captured by the client device. The network node receives, from the client device, a request to authenticate a user that includes a first set of transformed biometric data transformed with a first secret feature transform key shared with the client device; fetches, from a secure end-user repository, a second set of enrolled transformed biometric data associated with the first set of transformed biometric data and a second secret feature transform key with which the second set of biometric data was transformed at enrolment of the transformed biometric data; and submits the second set of transformed biometric data and the second secret feature transform key over a secure communication channel to the client device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 2, 2021
    Assignee: FINGERPRINT CARDS AB
    Inventor: Christian Gehrmann
  • Patent number: 11128321
    Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Min Shin, Beom Kyu Shin, Heon Hwa Cheong, Jun Jin Kong, Hong Rak Son, Yeong Geol Song, Se Jin Lim
  • Patent number: 11121895
    Abstract: A repeater includes a reception unit, a permission signal generating unit that detects the state of the pulses of the signal, and generates a permission signal that permits a relay of the signal when the permission signal generating unit detects the pulses, and that inhibits the relay of the signal when the permission signal generating unit detects an end of the pulses, and a transmission unit. When detecting the end of the pulses, for the permission signal, the permission signal generating unit sets a pulse re-input monitoring period for determining whether or not the pulses of the signal are re-detected. When detecting the pulses of the signal during the pulse re-input monitoring period, the permission signal generating unit determines that the signal continues, and when not detecting the pulses of the signal, the permission signal generating units determines that the signal ends.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihiro Nakahara, Shingo Yamamoto
  • Patent number: 11119854
    Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 14, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Yu-Kuo Yang, Takao Akaogi, Pauling Chen
  • Patent number: 11070402
    Abstract: A receiving apparatus includes a first sample circuit configured to extract first binary data based on a first voltage and a clock timing of a received signal, a second sample circuit configured to extract second binary data based on an adjustable second voltage and a clock timing of the received signal, and a waveform processor configured to acquire a plurality of the second binary data from the second sample circuit using a pattern, the pattern corresponding to the first binary data extracted by the first sample circuit with consecutive sampling timings, determine an appearance frequency of the received signal based on the plurality of second binary data and the first binary data, and generate waveform information of the received signal according to the determined appearance frequency.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takaya Yamamoto
  • Patent number: 11031961
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which optimize one or more metrics of a communication system by intentionally changing symbols in a bitstream after encoding by an error correction coder, but prior to transmission. The symbols may be changed to meet a communication metric optimization goal, such as decreasing a high PAPR, reducing an error rate, reducing an average power level (to save battery), or altering some other communication metric. The symbol that is intentionally changed is then detected by the receiver as an error and corrected by the receiver utilizing the error correction coding.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Amer Aref Hassan
  • Patent number: 11023323
    Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Rao, Karthik Ramasubramanian, Brian Paul Ginsburg
  • Patent number: 10972131
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10901843
    Abstract: Disclosed herein are techniques for use in managing data storage. For example, in one embodiment, the techniques comprise determining a size of the write request. The size of the write request equating to half or more non-parity data portions in a full stripe of data but less than all non-parity data portions in the full stripe.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Marc Cassano, Robert Foley, Daniel Cummins, Socheavy Heng
  • Patent number: 10878265
    Abstract: An image processing device includes an importance calculating unit, a capturing-direction acquiring unit, a parameter estimating unit, and an important-area setting unit. The importance calculating unit is configured to calculate importance of each of a plurality of positions in an image. The capturing-direction acquiring unit is configured to acquire, for each of the positions, a capturing direction in a three-dimensional space. The parameter estimating unit is configured to regard importance distributions in respective capturing directions as a mixture distribution made up of element distributions, so as to estimate a parameter of each of the element distributions. The important-area setting unit is configured to set an important area from the image in accordance with the parameter.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: December 29, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventor: Takayuki Hara
  • Patent number: 10863200
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for storing, in memory, at least one master forward transform matrix comprising signed constants having a defined number of precision bits and a sign bit and determining, by processing circuitry, which forward transform matrix to use to perform a transformation based on at least a transform unit size. Further, various techniques may include performing, by the processing circuitry, the transformation on residuals of pixel values of a frame using one of the at least one master forward transform matrix or a forward transform matrix derived from one of the master forward transform matrix at least partially based on the determination.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventor: Douglas L. Li
  • Patent number: 10791336
    Abstract: A prediction information deriving unit derives the inter-prediction information candidates from inter-prediction information of a prediction block neighboring to a coding target prediction block or a prediction block present at the same position as or near the coding target prediction block in a coded picture at a temporally different position from the coding target prediction block. A candidate supplementing unit supplements inter-prediction information candidates having the same prediction mode, reference index, and motion vector until the number of inter-prediction information candidates reaches the designated number of candidates when the number of inter-prediction information candidates is smaller than the designated number of candidates.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 29, 2020
    Assignee: JVCKENWOOD CORPORATION
    Inventors: Hiroya Nakamura, Shigeru Fukushima, Hideki Takehara
  • Patent number: 10761966
    Abstract: A method of generating program analysis data for analysing the operation of a computer program. The method comprises, executing an instrumented process of the computer program to define a reference execution of the program, intercepting a call to a library function by the instrumented process, executing the library function in an uninstrumented process, for the uninstrumented process, capturing in a log, only data generated by or modified through the execution of the library function required by the instrumented process to continue execution of the program, and wherein the captured log is arranged to enable deterministically reproducing the effect of the library function call on the instrumented process upon re-running of the reference execution based upon the captured log to generate the program analysis data.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 1, 2020
    Assignee: Undo Ltd.
    Inventors: Nicholas Peter Bull, Julian Philip Smith, Gregory Edward Warwick Law
  • Patent number: 10700714
    Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Min Shin, Beom Kyu Shin, Heon Hwa Cheong, Jun Jin Kong, Hong Rak Son, Yeong Geol Song, Se Jin Lim
  • Patent number: 10684909
    Abstract: A system and method that automatically detects anomalies in a cloud service system on an ongoing basis and which can be used to trigger live migration of cloud services includes a cloud server system configured to provide a plurality of virtualized cloud services through processes running over a set of virtual machines hosted on the cloud server system, and a processor which receives data related to the operations of the virtual machines and determines whether any of the virtual machines are exhibiting anomalous behavior. The processor applies a Kalman Filter to make predictions on the future state and covariance of the virtual machines and then calculates the log likelihood of the predicted values. If the predicted values deemed to be very unlikely, then the processor signals that an anomaly has occurred.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 16, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Michael A. August, Mamadou H. Diallo, Dillon P. Glasser, Christopher T. Graves, Roger A. Hallman, Scott M. Slayback
  • Patent number: 10671508
    Abstract: Some examples described herein relate to testing of a cloud service. In an example, a cloud service to be tested may be deployed in a cloud system. A test load may be applied to the cloud service. Upon application of the test load to the cloud service, a determination may be made whether a performance metric related to the cloud service meets a pre-configured criterion. If the performance metric related to the cloud service meets a pre-configured criterion, the cloud service may be scaled. Operations of applying, determining, and scaling may iterated until an end condition is met, wherein the test load applied to the cloud service may vary after each iteration operation.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 2, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Upendra Gopu, Anusha Kadambala, Siva Subramaniam Manickam
  • Patent number: 10635522
    Abstract: A processor-fault reproduction method includes: determining a heating time of a processor taken using a heating program which heats the processor to a fault occurrence temperature when a fault occurs from a current temperature based on first information regarding the current temperature of the processor, second information regarding a power consumption value and a temperature of the processor before the fault occurs and a refrigerant temperature of a cooling medium to cool the processor, third information regarding the fault occurrence temperature, and fourth information regarding a power consumption value of the processor during execution of the heating program; determining an execution time by adding a fault reproduction time taken by a fault reproducing program which reproduces a state of the processor when the fault occurs to the heating time; and reporting the execution time to a job scheduler with a request to execute the heating and fault reproducing programs.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Jumpei Kubota, Tsuyoshi Hashimoto
  • Patent number: 10623001
    Abstract: Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10608790
    Abstract: Various embodiments disclosed herein provide for a transmission system using codeblock segmentation that does not have to retransmit each of the codeblock segments if one of the codeblock segments is determined to have an error at the receiver. The transmitter segments a transport block into a group of codeblock segments, each having respective cyclic redundancy check bits. The receiver receives the group of codeblock segments, and during decoding, if it is determined that one of the segments have an error, instead of just sending back to the transmitter a negative acknowledgement (NAK) the receiver can send back a NAK as well as an indicator of which segment was in error. The transmitter can then resend just the segment in error in order to improve efficiency and decrease power requirements.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 31, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventor: SaiRamesh Nammi
  • Patent number: 10514861
    Abstract: Methods and apparatus are provided for reporting space savings due to pattern matching in storage systems. An exemplary method comprises, when a given allocation unit in a storage system matches one or more predefined patterns, (i) setting a corresponding pattern flag for the given allocation unit, and (ii) incrementing at least one pattern counter; generating at least one snapshot of at least a portion of a file comprising the given allocation unit; and determining a data reduction attributed to pattern matching based on the at least one pattern counter, wherein the one or more predefined patterns in the at least one snapshot are excluded from the data reduction attributed to pattern matching.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 24, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ivan Basov, Ahsan Rashid, Michal Marko, Walter Forrester
  • Patent number: 10498662
    Abstract: A method for packet field suppression in broadband wireless communication is provided. Values for packet suppression can be learned and subsequently used for suppression. The learning can involve determining a new packet field suppression rule and a packet field suppression index. Packets can be suppressed based on the learned values.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 3, 2019
    Assignee: Ondas Networks Inc.
    Inventors: Menashe Shahar, Guy Robert Simpson
  • Patent number: 10489238
    Abstract: A client management server manages client devices deployed throughout an enterprise facility that may be used for various applications such as wayfinders and internal and external meeting room computers. The client management receives screenshots from the client devices and applies a classifier to classify an operating state of each device as corresponding to a normal operating state or an error state. If the operating state is classified as corresponding to the error state, a remedial action is triggered. The classifier may be a machine trained model that is trained using supervised or unsupervised learning, including by simulating errors on the clients.
    Type: Grant
    Filed: October 28, 2017
    Date of Patent: November 26, 2019
    Assignee: Facebook, Inc.
    Inventors: Oliver Pell, Davide Guerri
  • Patent number: 10469104
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 10445181
    Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Inon Cohen, Asaf Gueta
  • Patent number: 10425107
    Abstract: Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 24, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Louis-Philippe Hamelin
  • Patent number: 10382554
    Abstract: Inter-zone network traffic generated during deletion of a data chunk that has been replicated by employing geographically distributed (GEO) erasure coding is reduced. In one aspect, if a data chunk is to be deleted, partial coding chunks are generated by a source zone and provided to destination zones that store complete coding chunks for updating the complete coding chunks based on combining them with the received partial coding chunks. In another aspect, if a first data chunk is to be deleted and a second data chunk is to be replicated, partial coding chunks are generated by the source zone for each data chunk. Further, the partial coding chunks created for different data chunks can be combined to generate transforming chunks, which can then be transferred to the destination zones. The destination zones can then update the complete coding chunks based on combining them with the received transforming chunks.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 13, 2019
    Assignee: EMC CORPORATION
    Inventors: Mikhail Danilov, Konstantin Buinov
  • Patent number: 10331514
    Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy