By Count Or Rate Limit, E.g., Word- Or Bit Count Limit, Etc. (epo) Patents (Class 714/E11.004)
  • Patent number: 8977928
    Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Siemens Aktiegesellschaft
    Inventors: Markus Premke, Bernhard Wiesgickl
  • Patent number: 8959406
    Abstract: Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 17, 2015
    Assignee: ADVA Optical Networking SE
    Inventor: Mirko Lawin
  • Publication number: 20140095963
    Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: LSI CORPORATION
    Inventors: Fan Zhang, Wu Chang
  • Publication number: 20140082437
    Abstract: A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 20, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Jun Wan, Bo Lei, Feng Pan, Yongke Sun
  • Publication number: 20140068357
    Abstract: Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: AOPTIX TECHNOLOGIES, INC.
    Inventors: Eric Saint Georges, Joseph Shiran, Scott Alan Young
  • Publication number: 20140040682
    Abstract: A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: LSI CORPORATION
    Inventors: Fan Zhang, Wu Chang, Ming Jin, Shaohua Yang
  • Publication number: 20140040681
    Abstract: A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Jonathan Wolfman, Dana Lee, Jonathan Hsu
  • Publication number: 20130346811
    Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG
  • Publication number: 20130339811
    Abstract: Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Patrick J. Meaney
  • Patent number: 8612809
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: December 17, 2013
    Assignee: Intel Corporation
    Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
  • Publication number: 20130262937
    Abstract: Systems, methods, and other embodiments associated with detecting a node death in a clustered distributed system are described. In one embodiment, a method includes transmitting a ping message to a peer node in the network. If a reply to the ping message is not received from the peer node, a query is sent to table of port identifiers that lists ports in the cluster. In one embodiment, the query includes a port identifier associated with the peer node. The peer node is declared as inactive/dead when the query fails to locate a match in the table for the port identifier. When the query locates a match in the table for the port identifier, another ping message is periodically transmitted to the peer node.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Vijay SRIDHARAN, Huy Nguyen, Jia Shi, Alex Tsukerman, Kothanda Umamageswaran
  • Patent number: 8536888
    Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jinn-Yeh Chien, Hao-Jie Zhan
  • Patent number: 8519875
    Abstract: Various embodiments allow for background calibration of channel-to-channel mismatch errors. In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 27, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Allen Zornig Straayer, Hae-Seung Lee
  • Publication number: 20130219233
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Inventors: Fan Zhang, Shaohua Yang, Yang Han, Xuebin Wu, Wu Chang
  • Publication number: 20130219234
    Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Debjit Roy Choudhury, Dipankar Das, Ashank Reddy
  • Publication number: 20130205176
    Abstract: A control channel may be used to transmit control information, such as Downlink Control Information (DCI), to a mobile device from a network component, such as a base station or a base node. The mobile device may use a blind decoding scheme to detect DCIs. A DCI may be falsely detected by the mobile device. According to some embodiments, data that has been decoded by a blind decoder, from buffer data for a candidate control channel, is re-encoded. The re-encoded data is compared to buffer data for the control channel. The decoded data is treated as control information dependent on the comparison of the re-encoded data with the buffer data. In some embodiments, comparing the re-encoded data to the buffer data includes generating a metric as a function of a degree of similarity between the re-encoded data and the buffer data. The metric may be compared to a threshold.
    Type: Application
    Filed: June 15, 2012
    Publication date: August 8, 2013
    Applicant: RESEARCH IN MOTION LIMITED
    Inventors: XING QIAN, YANGWEN LIANG, JONATHAN OTTO SWOBODA, PHAT HONG TRAN
  • Publication number: 20130198577
    Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.
    Type: Application
    Filed: October 10, 2012
    Publication date: August 1, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Publication number: 20130170063
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a filter circuit, and a mean squared calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The filter circuit is operable to filter the detected output to yield a filtered output. The mean squared calculation circuit is operable to calculate a mean squared error value based at least in part on the data set and the filtered output. A quality indicator is generated at least in part on the mean squared error value.
    Type: Application
    Filed: January 3, 2012
    Publication date: July 4, 2013
    Inventor: Shaohua Yang
  • Publication number: 20130166972
    Abstract: Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Inventors: John L. Seabury, Bruce A. Liikanen
  • Publication number: 20130159796
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Publication number: 20130151911
    Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: XILINX, INC.
    Inventors: Christopher H. Dick, Raghavendar M. Rao
  • Publication number: 20130151912
    Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.
    Type: Application
    Filed: January 23, 2012
    Publication date: June 13, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventor: SARAVANAKUMAR SEVUGAPANDIAN
  • Publication number: 20130145224
    Abstract: A method for transmitting a data block in a wireless communication system and a transmitter are provided. The transmitter transmits the data block to a receiver and generates a retransmission block for the retransmission of the data block if it is determined that the transmission fails. The transmitter determines whether the channel access is performed according to a transmit time of the retransmission block.
    Type: Application
    Filed: May 23, 2012
    Publication date: June 6, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yun Joo Kim, Yu Ro Lee, Sok Kyu Lee
  • Publication number: 20130139009
    Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Hyoung-Gon Lee
  • Publication number: 20130086439
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Inventors: Haitao Xia, Shaohua Yang, Kenneth M. Hall, Mark A. Landreth
  • Publication number: 20130086438
    Abstract: Various embodiments of the present invention provide systems and methods for data processing.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Inventors: Haitao Xia, Shaohua Yang, Kenneth M. Hall, Mark A. Landreth
  • Publication number: 20130080846
    Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 28, 2013
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Siemens Aktiengesellschaft
  • Publication number: 20130076545
    Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiko Sugimoto, Takafumi Yamaji, Junya Matsuno, Masanori Furuta
  • Publication number: 20130080845
    Abstract: An interface with universal serial communication comprises a switching device, a medium device, and a data restoring device for transmitting the data and obtaining the serial communication via one signal line that is inter-strung by afore devices. By simplifying such communication device, the compatibility thereof could be enhanced. Moreover, during the data transmission, computation made by an error coefficient and an error beyond value in the switching device allows the transmitted data to be kept within an acceptable noise value, so that the accuracy of the data could be assured.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: NATIONAL CHIN-YI UNIVERSITY OF TECHNOLOGY
    Inventor: WEN-CHENG PU
  • Publication number: 20130047045
    Abstract: The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Xinde Hu, Anthony D. Weathers, Richard D. Barndt
  • Publication number: 20130047044
    Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 21, 2013
    Applicant: STEC, Inc.
    Inventors: Anthony D. Weathers, Richard D. Barndt, Xinde Hu
  • Publication number: 20130042157
    Abstract: Systems and methods are disclosed for improving throughput in a wireless system utilizing Hybrid Automatic Repeat Request (HARQ) retransmission. In general, prior to a HARQ-enabled transmission, one or more channel conditions for a corresponding transmit channel are obtained. Based on the one or more channel conditions, a set of target block error rates for the HARQ-enabled transmission are determined. In one embodiment, the set of target block error rates maximize throughput for the transmit channel utilizing HARQ retransmission. In another embodiment, the set of target block error rates optimize throughput and one or more additional parameters for the transmit channel utilizing HARQ retransmission.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Arezou Mohammadi, Edward Mah
  • Publication number: 20130036335
    Abstract: Devices and methods for monitoring a bit error rate of an intra-panel data link (e.g., a chip-on-glass (COG) data link) between a timing controller and a display driver are provided. For example, an electronic display according to an embodiment may include a timing controller and display driver circuitry. The timing controller may send test data over a data link to the display driver circuitry. The test data may include a known or predictable stream of data. The display driver circuitry may receive the test data via the data link and detect bit errors based at least partly on the test data. An indication of the bit errors may be displayed on an array of pixels of the display or provided to the timing controller via a separate back channel data link.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: APPLE INC.
    Inventors: Taesung Kim, Paolo Sacchetto
  • Publication number: 20130024735
    Abstract: Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Applicant: OCZ TECHNOLOGY GROUP INC.
    Inventors: Hyun Mo Chung, Franz Michael Schuette
  • Publication number: 20130024736
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Application
    Filed: October 2, 2012
    Publication date: January 24, 2013
    Applicant: MICRON TECHNOLOGY, INC
    Inventor: MICRON TECHNOLOGY, INC
  • Publication number: 20130019129
    Abstract: Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Inventor: Mirko Lawin
  • Publication number: 20130013968
    Abstract: A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Robert Hetzler, William John Kabelac
  • Publication number: 20120331357
    Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.
    Type: Application
    Filed: September 22, 2011
    Publication date: December 27, 2012
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YIJ CHIEH CHU, YUN-ZONG TIAN
  • Publication number: 20120290887
    Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.
    Type: Application
    Filed: December 5, 2011
    Publication date: November 15, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sil JEONG, Sung-Ryul YUN, Hyun-Koo YANG, Se-Ho MYUNG, Alain MOURAD, Ismael GUTIERREZ
  • Publication number: 20120284574
    Abstract: A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 8, 2012
    Inventors: Chris Nga Yee Avila, Jianmin Huang, Lee M. Gavens, Idan Alrod
  • Publication number: 20120278670
    Abstract: An image processing apparatus of the present disclosure includes: a two-dimensional matrix barcode decoding unit configured to decode a two-dimensional matrix barcode in an image of image data; and a restoration determining unit configured (a) to obtain an error detection rate and error detection position information detected while the two-dimensional matrix barcode is decoded, (b) to compare the error detection rate with a predetermined threshold value, (c) on the basis of the comparison result, to determine whether the two-dimensional matrix barcode should be restored, and (d) to adjust the threshold value according to an error detection position determined from the error detection position information.
    Type: Application
    Filed: April 20, 2012
    Publication date: November 1, 2012
    Inventors: Kunihiko Shimamoto, Yuya Tagami
  • Publication number: 20120272106
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20120266032
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20120254676
    Abstract: An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.
    Type: Application
    Filed: March 9, 2012
    Publication date: October 4, 2012
    Applicant: Sony Corporation
    Inventor: Koji Hirairi
  • Publication number: 20120239991
    Abstract: Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 20, 2012
    Applicant: STEC, Inc.
    Inventor: Ashot MELIK-MARTIROSIAN
  • Publication number: 20120239990
    Abstract: A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 20, 2012
    Applicant: STEC, INC.
    Inventors: Richard A. MATAYA, Po-Jen HSUEH, Mark MOSHAYEDI
  • Publication number: 20120226950
    Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a symbol error rate (SER) and an energy metric (EM). The method also includes classifying the data into a first category if the data fails a cyclic redundancy check (CRC) check, into a second category if the data passes the CRC check and is determined to be unreliable, or into a third category if the data passes the CRC check and is determined to be reliable. A reliability of the data is determined based on the decoder metrics and an EM threshold.
    Type: Application
    Filed: September 8, 2011
    Publication date: September 6, 2012
    Applicant: QUALCOMM Incorporated
    Inventors: Prashant Udupa Sripathi, Jittra Jootar, Je Woo Kim, Feng Lu
  • Publication number: 20120221900
    Abstract: A system deployment determination system is provided that can appropriately define the number of information processing apparatuses that satisfies availability defined in an SLA as the number of information processing apparatuses used in a target system to be configured. The list generating means 52 generates a list including information processing apparatuses of which failure rates are less than the failure rate defined, and searches an information processing apparatus used independently or an information processing apparatus group forming a cluster of which cost is the lowest. The apparatus number determining means 53 calculates a number of information processing apparatuses required to satisfy the amount of requested processing during normal operation on the basis of the amount of requested processing during normal operation and an amount of processing performed by the searched information processing apparatus used independently or the searched information processing apparatus group forming the cluster.
    Type: Application
    Filed: October 15, 2010
    Publication date: August 30, 2012
    Applicant: NEC Corporation
    Inventor: Shinjiro Yagi
  • Publication number: 20120216084
    Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 23, 2012
    Applicant: QUALCOMM, Incorporated
    Inventors: Dexter T. Chun, Jack K. Wolf, Jungwon Suh, Tirdad Sowlati
  • Publication number: 20120192020
    Abstract: One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Inventors: Juergen Kreuchauf, Thorsten Clevorn