Abstract: An integrated circuit for a fluid ejection device having actuators to operate during a non-reset operating condition is disclosed. The integrated circuit includes a reset input to receive a reset signal activated for a duration. The reset signal generates a reset condition in the integrated circuit. The integrated circuit also includes a monitor circuit operably coupled to the reset input to indicate if the duration of the reset signal meets or exceeds a selected duration and a nonvolatile memory device having data accessible during the reset condition.

Abstract: Examples of systems and methods for network proxy server for energy efficient video streaming on mobile devices are generally described herein. A proxy server to deliver video content may include a communication module to intercept a request for video content from a mobile device, the request for video content intended for a content server and forward a modified request for the video content to the content server. The communication module may receive the video content from the content server and transfer a portion of the video content to the mobile device using a multipath transport protocol.

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.

Abstract: A transceiver for a CAN bus system and a method for detecting a short circuit using a CAN transceiver. The transceiver includes a transmitter for transmitting a transmission signal to a first bus wire of a bus of the bus system, exclusive, collision-free access to the bus of the bus system of a user station being at least temporarily ensured in the bus system, and for transmitting the transmission signal to a second bus wire of the bus, a receiver for receiving the bus signal transmitted on the bus wires, and a diagnostic unit for detecting a short circuit in the bus system, the diagnostic unit being designed to carry out a diagnosis only in a predetermined communication phase of the bus signal.

Abstract: A computerized system and method may include, in response to receiving a blockchain via a communications network that includes information associated with an event, parsing, by a blockchain parsing engine being executed by a blockchain node, the information to identify a status state of an item related to the event. The blockchain may be inclusive of the information along with the status state of the item may be stored in a storage unit. An event tracking engine may determine from the parsed information that the status state of the item transitioned from a first state to a second state. Responsive to the event tracking engine determining that a qualifying state is satisfied by the item being in the second state, automatically executing, by the blockchain node, a smart code inclusive of initiating communications between a first party and a second party.

Abstract: In a semiconductor device according to the related art, unfortunately, a non-safety unit mounted on the same device as a safety unit is modified with low flexibility. According to one embodiment, a first semiconductor chip and a second semiconductor chip each have space domain separation hardware for limiting access to hardware resources in a functional safety system. Safety unit software and space domain and time domain separation software are executed in a time sharing manner. Based on a timer installed on the semiconductor chip, the space domain and time domain separation software performs separation for intermittently executing the safety unit software in a predetermined cycle, self-diagnosis for examining an operation of the safety unit software, and mutual diagnosis made between the first semiconductor chip and the second semiconductor chip to mutually diagnose the operation of the space domain and time domain separation software for performing the separation and the self-diagnosis.

Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.

Abstract: Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors.

Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.

Abstract: A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.

Abstract: Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments.

Abstract: A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric.

Abstract: A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Systems, methods, and other embodiments associated with detecting a node death in a clustered distributed system are described. In one embodiment, a method includes transmitting a ping message to a peer node in the network. If a reply to the ping message is not received from the peer node, a query is sent to table of port identifiers that lists ports in the cluster. In one embodiment, the query includes a port identifier associated with the peer node. The peer node is declared as inactive/dead when the query fails to locate a match in the table for the port identifier. When the query locates a match in the table for the port identifier, another ping message is periodically transmitted to the peer node.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: Various embodiments allow for background calibration of channel-to-channel mismatch errors. In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A control channel may be used to transmit control information, such as Downlink Control Information (DCI), to a mobile device from a network component, such as a base station or a base node. The mobile device may use a blind decoding scheme to detect DCIs. A DCI may be falsely detected by the mobile device. According to some embodiments, data that has been decoded by a blind decoder, from buffer data for a candidate control channel, is re-encoded. The re-encoded data is compared to buffer data for the control channel. The decoded data is treated as control information dependent on the comparison of the re-encoded data with the buffer data. In some embodiments, comparing the re-encoded data to the buffer data includes generating a metric as a function of a degree of similarity between the re-encoded data and the buffer data. The metric may be compared to a threshold.

Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a filter circuit, and a mean squared calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The filter circuit is operable to filter the detected output to yield a filtered output. The mean squared calculation circuit is operable to calculate a mean squared error value based at least in part on the data set and the filtered output. A quality indicator is generated at least in part on the mean squared error value.

Abstract: Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: A method for transmitting a data block in a wireless communication system and a transmitter are provided. The transmitter transmits the data block to a receiver and generates a retransmission block for the retransmission of the data block if it is determined that the transmission fails. The transmitter determines whether the channel access is performed according to a transmit time of the retransmission block.

Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.

Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.

Abstract: An interface with universal serial communication comprises a switching device, a medium device, and a data restoring device for transmitting the data and obtaining the serial communication via one signal line that is inter-strung by afore devices. By simplifying such communication device, the compatibility thereof could be enhanced. Moreover, during the data transmission, computation made by an error coefficient and an error beyond value in the switching device allows the transmitted data to be kept within an acceptable noise value, so that the accuracy of the data could be assured.

Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.

Abstract: The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first error type corrected in the bits and determining a second error rate of a second error type corrected in the bits. In certain aspects, methods of the subject technology further provides steps for comparing the first error rate with the second error rate and generating a read-level error signal based on the comparison of the first error rate and the second error rate. A decoder and flash storage device are also provided.

Abstract: The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.

Abstract: Systems and methods are disclosed for improving throughput in a wireless system utilizing Hybrid Automatic Repeat Request (HARQ) retransmission. In general, prior to a HARQ-enabled transmission, one or more channel conditions for a corresponding transmit channel are obtained. Based on the one or more channel conditions, a set of target block error rates for the HARQ-enabled transmission are determined. In one embodiment, the set of target block error rates maximize throughput for the transmit channel utilizing HARQ retransmission. In another embodiment, the set of target block error rates optimize throughput and one or more additional parameters for the transmit channel utilizing HARQ retransmission.

Abstract: Devices and methods for monitoring a bit error rate of an intra-panel data link (e.g., a chip-on-glass (COG) data link) between a timing controller and a display driver are provided. For example, an electronic display according to an embodiment may include a timing controller and display driver circuitry. The timing controller may send test data over a data link to the display driver circuitry. The test data may include a known or predictable stream of data. The display driver circuitry may receive the test data via the data link and detect bit errors based at least partly on the test data. An indication of the bit errors may be displayed on an array of pixels of the display or provided to the timing controller via a separate back channel data link.

Abstract: Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors.

Abstract: A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed.

Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.

Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Abstract: A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.

Abstract: An image processing apparatus of the present disclosure includes: a two-dimensional matrix barcode decoding unit configured to decode a two-dimensional matrix barcode in an image of image data; and a restoration determining unit configured (a) to obtain an error detection rate and error detection position information detected while the two-dimensional matrix barcode is decoded, (b) to compare the error detection rate with a predetermined threshold value, (c) on the basis of the comparison result, to determine whether the two-dimensional matrix barcode should be restored, and (d) to adjust the threshold value according to an error detection position determined from the error detection position information.

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.