Abstract: A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.

Abstract: A parallelized or array method is developed for the generation of Reed Solomon parity bytes which utilizes multiple digital logic operations or computer instructions implemented using digital logic. At least one of the operations or instructions used performs the following combinations of steps: a) provide an operand representing N feedback terms where N is greater than one, b) computation of N by M Galios Field polynomial multiplications where M is greater than one, and c) computation of (N?1) by M Galios Field additions producing M result bytes. In this case the result bytes are used to modify the Reed Solomon parity bytes in either a separate operation or instruction or as part of the same operation. A parallelized or array method is also developed for the generation of Reed Solomon syndrome bytes which utilizes multiple digital logic operations or computer instructions implemented using digital logic.

Abstract: In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of a different cyclic code for each codeword. Further provided is a hybrid device which provides the configurability of two modes of operation, whereby in one mode, the hybrid device functions as the encoder as provided above and, in the other mode, the hybrid device functions as the syndrome computer as provided above, with the majority of the components of the hybrid device being shared between the encoding function and the syndrome computing function.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

Abstract: A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B?x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B? is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ? 0 0 0 T ? 0 0 ? ? ? ? ? 0 0 ? T 0 I I ? I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Abstract: An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where “h” is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h?j) bits in the information data based on encoded data including the information and the syndrome data, where “j” is 1 or an integer greater than 1.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.

Abstract: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1) different error patterns potentially introduced in the codeword during transmission across the communication channel. A type of an error pattern within the codeword is detected based on the syndrome or a shifted version of the syndrome, and then a start position of the error pattern within the codeword.

Abstract: A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: ?(n)=f1n+f2n2 mod K, where the QPP coefficients f1 and f2. are designed to provide good error performance for a given block length K.

Abstract: The present invention discloses a method and system for improving the decoding efficiency in a wireless receiver to obtain a correct decoded data string. The method comprises generating an active state metric matrix of a receiving codeword, calculating a differential metric matrix pertinent to the active state metric matrix, identifying a maximum likelihood path and one or more alternative paths based on the differential metric matrix, deriving a first decoded data string corresponding to the maximum likelihood path, deriving a plurality of second decoded data strings corresponding to the one or more alternative paths, respectively examining the integrity of the first decoded data string; and examining the integrity of the plurality of second decoded data strings after the first decoded data string is determined erroneous, wherein the wireless receiver obtains the correct decoded data string.

Abstract: The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(xk+1, . . . , xm) composed of m-k digit(s); a creation means for creating an x?=[xu]=(x1, . . . , xm) by concatenating the vector u=(xk+1, . . . , xm) composed of m-k digit(s) randomly created by the creation means to data x=(x1, . . . , xk) to send; and an output means for outputting a vector of length n by carrying out [n, m] encoding of the x? created by the creation means.

Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.

Abstract: The invention relates to a data live streaming system comprising at least one data live streaming broadcaster LSB and at least two live streaming recipients LSR, said at least two live streaming recipients LSR forming at least a part of a peer-to-peer streaming network and said at least two live streaming recipients LSR each comprising means for generation of peer-to peer streaming to other live streaming recipients LSR of said peer-to peer streaming network and wherein said peer-to peer streaming to other streaming recipients LSR comprises loss resilient code representations of data from said at least one live streaming broadcaster LSB.

Abstract: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n?1)-th-order polynomial multiplying units (12-1 to 12-(m?1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m?1) blocks having a length n and a single block having a length (n-r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length.