Error Detection Or Correction By Redundancy In Data Representation, E.g., By Using Checking Codes, Etc. (epo) Patents (Class 714/E11.03)

  • Patent number: 9003140
    Abstract: A storage system including first storage devices constituting a first logical storage area, second storage devices constituting a second logical storage area; and a storage control apparatus. The storage control apparatus manages the first and second logical storage areas so that the data stored in the first and second logical storage areas have redundancy, and parity data for the data stored in the second logical storage area are stored in parity storage areas arranged in part of the second storage devices. When part of the first storage devices constituting part of the first logical storage area fail, the storage control apparatus generates part of the data stored, before the failure, in the part of the first storage devices, and stores the generated part of the data in at least part of the second parity storage areas in the second logical storage area.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Kazuhiko Ikeuchi, Hidejirou Daikokuya, Takeshi Watanabe, Norihide Kubota, Atsushi Igashira, Kenji Kobayashi, Ryota Tsukahara
  • Patent number: 8948232
    Abstract: A method and device are provided for transmitting a digital signal intended for a network having at least four nodes including two transmitters, a relay and a receiver separated from one another by non-orthogonal links, except between the relay and the destination, between which the link is orthogonal, implementing a spatially distributed network code. The method includes: encoding, in each transmitter, supplying a code word for every block of K bits of information; transmitting, in the transmitters, the code word during ?N transmission intervals, ??[0,1]; jointly, iteratively detecting/decoding, in the relay, in order to separate interfering streams from the transmitters and to determine, for each stream, a vector representing the K bits of information associated with the code word; jointly encoding, in the relay, the two vectors in order to determine redundancy information, and scheduling the relays to transmit the redundancy information during the (1??)N following transmission intervals.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: February 3, 2015
    Assignee: Orange
    Inventors: Atoosa Hatefi, Raphaël Visoz, Antoine Berthet
  • Patent number: 8885762
    Abstract: According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 11, 2014
    Assignee: LG Electronics Inc.
    Inventors: In Hwan Choi, Jong Yeul Suh, Chul Soo Lee, Jae Hyung Song, Jin Pil Kim
  • Patent number: 8862957
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Weijun Tan, Shaohua Yang, Kelly K. Fitzpatrick, Xuebin Wu, Fan Zhang
  • Patent number: 8775902
    Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventor: Takeshi Ootsuka
  • Patent number: 8775124
    Abstract: A method for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults. A complete set of analytical redundancy relations of the system is built from a set of intermediate relations established between observable and non-observable variables of the system, wherein each intermediate relation is generated by combining two predetermined relations Rj, Rk, each of which is expressed in an implicit form as a tuple (i) of a subset Sj of system variables, (ii) of the set Cj of the support components for said relation, and (iii) of the set Tj of the primary relations used to derive said intermediate relation.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Fondazione Istituto Italiano di Technologia
    Inventors: Amir Fijany, Farrokh Vatan
  • Publication number: 20140115431
    Abstract: Various systems and methods for media defect detection.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Applicant: LSI Corporation
    Inventors: Fan Zhang, Weijun Tan, Shaohua Yang
  • Publication number: 20140089759
    Abstract: An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for real-time error correction and decoding by dividing the linear programming problem into independent parallelizable problems so that separate independent portions of the electronic circuit may simultaneously address solutions related to individual bits and/or parity rules. Linear programming is believed to avoid error floors inherent in conventional belief propagation error detection and correction techniques providing a decoding system suitable for high reliability applications.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Stark Draper, Benjamin Recht, Siddharth Barman
  • Publication number: 20140082456
    Abstract: A data storage device includes a non-volatile memory and a controller including a first error correction coding (ECC) engine configured to generate a first codeword corresponding to data to be stored at the non-volatile memory. The data storage device also includes a second ECC engine coupled to the controller and to the non-volatile memory. The second ECC engine is configured to receive a representation of the first codeword from the controller and to perform a decode operation of the representation of the first codeword to correct transmission errors prior to storage of the data in the non-volatile memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventor: TAO LIU
  • Publication number: 20140082448
    Abstract: The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 20, 2014
    Inventors: Fan Zhang, Shaohua Yang, Ming Jin
  • Publication number: 20140082449
    Abstract: The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable node by using check node to variable node (C2V) messages from a previous iteration that are likely to be correct when generating variable node to check node (V2C) messages.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 20, 2014
    Inventor: Fan Zhang
  • Publication number: 20140068325
    Abstract: A computer-implemented method for test case result processing includes receiving, by a test case result processing logic in a processor of a computer, a test result from a test case that executes on the computer; determining, by the test case result processing logic based on a result description file, whether a result description corresponding to the received result exists in the result description file; based on the result description corresponding to the received result existing in the result description file, determining an action description associated with the result description based on an action definition file; and executing an action corresponding to the determined action description.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel L. Masser, David C. Reed, Max D. Smith
  • Publication number: 20140068319
    Abstract: An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventor: David M. Daly
  • Publication number: 20140068372
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Fan Zhang, Shaohua Yang, Yang Han, Chung-Li Wang
  • Publication number: 20140059398
    Abstract: Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventors: Jeffrey C. Cunningham, Horacio P. Gasquet, Ross S. Scouller, Marco A. Cabassi
  • Publication number: 20140040698
    Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, James M. O'Connor, Bradford M. Beckmann, Michael Ignatowski
  • Publication number: 20140040673
    Abstract: Methods, apparatuses, and computer program products for administering incident pools for incident analysis in a distributed processing system are provided. Embodiments include an incident analyzer receiving a plurality of incidents from an incident queue. The incident analyzer also assigns each received incident to an incident pool having a predetermined initial period of time. The predetermined initial period of time is the time within which the incident pool is open to the assignment of incidents. The incident analyzer calculates an arrival rate that incidents are assigned to the incident pool. The incident analyzer also extends based on the arrival rate, for each incident assigned to the incident pool, the predetermined initial period of time by a particular period of time.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James E. Carey, Philip J. Sanders
  • Publication number: 20140040704
    Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.
    Type: Application
    Filed: August 4, 2012
    Publication date: February 6, 2014
    Applicant: LSI CORPORATION
    Inventors: Yunxiang WU, Earl T. COHEN
  • Publication number: 20130332791
    Abstract: A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.
    Type: Application
    Filed: August 22, 2012
    Publication date: December 12, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Publication number: 20130290802
    Abstract: A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • Patent number: 8542761
    Abstract: A digital broadcasting system and method of processing data therein are disclosed. According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 24, 2013
    Assignee: LG Electronics Inc.
    Inventors: In Hwan Choi, Jong Yeul Suh, Chul Soo Lee, Jae Hyung Song, Jin Pil Kim
  • Publication number: 20130219251
    Abstract: In an electronic apparatus, a soft decision likelihood value is generated and subject to a decoding process supporting a convolutional code; and a data series is interleaved, subjected to an error correction process, and decoded data is generated. A detecting unit, based on information concerning the position of a symbol for which an error has been corrected successfully by the error correction process, estimates whether an error occurs in a symbol for which the error correction process failed and detects the position of a symbol estimated to have an error. A setting unit sets based on the decoded data and information concerning the position of the symbol estimated to have an error, a correction value of the soft decision likelihood value. The electronic device interleaves the order of a correction value series of the soft decision likelihood value and feeds the resulting correction value series back to the decoding process.
    Type: Application
    Filed: November 6, 2012
    Publication date: August 22, 2013
    Inventor: Fujitsu Limited
  • Publication number: 20130182916
    Abstract: A method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device. In one embodiment, a method of a custom hardware solution that includes a change in the CPU clock frequency dependency by using programmable logic and a highly parallel array of high capacity flash memory is shown.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Inventors: STEVE FIELDING, LIQUN LARRY WANG
  • Publication number: 20130179746
    Abstract: A transmitting/receiving system includes a first transmitting/receiving apparatus which includes a first transmitting unit and a first receiving unit, and a second transmitting/receiving apparatus which includes a second receiving unit, a detector, a second generator, and a second transmitting unit. The first transmitting unit transmits data with an error detecting code after a bit-number conversion. The first receiving unit receives a response to the data after a bit-number inverse conversion. The second receiving unit subjects the data to a bit-number inverse conversion. The detector detects an error from the error detecting code. The second generator generates a positive or negative acknowledgement depending on the error detection and uses a code which enables distinguishing between positive and negative acknowledgements when a 1-bit error occurs during transportation. The second transmitting unit transmits the acknowledgement after a bit-number conversion to the first transmitting/receiving apparatus.
    Type: Application
    Filed: August 22, 2012
    Publication date: July 11, 2013
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Tsutomu HAMADA
  • Publication number: 20130173968
    Abstract: A method of checking the integrity of a dynamic link library (DLL) file called by an application being executed on a handheld medical device is described. The method includes loading a DLL from a read only memory (ROM) to a random access memory (RAM) beginning at a fixed location in the RAM. The DLL includes a first routine for performing a safety critical function of the handheld medical device and a second routine for performing a cyclical redundancy check (CRC) once the DLL is loaded to the RAM. The method includes selectively executing the first routine from the RAM. The method includes selectively executing the second routine from the RAM including: calculating a check value based on the DLL; comparing the check value with a predetermined check value; and indicating that an error is present when the check value is different than the predetermined check value.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: ROCHE DIAGNOSTICS OPERATIONS, INC.
    Inventors: Gordon L. McVey, Marshall M. Parker, Richard W. Wilson
  • Publication number: 20130173983
    Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.
    Type: Application
    Filed: August 30, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JUNGSOO CHUNG, JUNJIN KONG, CHANGKYU SEOL, HONG RAK SON, PILSANG YOON, SEONGHYEOG CHOI
  • Publication number: 20130139028
    Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manish Goel
  • Publication number: 20130132789
    Abstract: The present disclosure provides video transmission systems and methods with video data flows transmitted over a Carrier Ethernet Network at Layer 2 with redundancy in order to provide hitless protection switching and uninterrupted video service delivery, such as during periods of asymmetric congestion or hard network failures. In an exemplary embodiment, the video transmission systems and methods provide the redundancy in a manner similar to 1+1 linear protection with hit-less protection switching. In another exemplary embodiment, the video transmission systems and methods provide encapsulated video signals over Ethernet using standardized Carrier Ethernet frames with additional sequencing information. Optionally, the video transmission systems and methods may also include packet-based forward error correction information for additional resiliency.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Applicant: CIENA CORPORATION
    Inventors: Michael WATFORD, Ross CAIRD
  • Publication number: 20130117627
    Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.
    Type: Application
    Filed: April 13, 2012
    Publication date: May 9, 2013
    Inventors: Sung Hyun Lee, Jun Hee Yoo
  • Publication number: 20130111297
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is discussed that includes: a data detector circuit, a symbol selective scaling circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data input guided by a first data set derived from a decoded output to yield a detected output. The symbol selective scaling circuit is operable to selectively scale one or more symbols of a second data set derived from the detected output to yield a scaled data set. The data decoder circuit operable to apply a data decode algorithm to a third data set derived from the scaled data set to yield the decoded output.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Inventors: Weijun Tan, Kelly Fitzpatrick, Shaohua Yang, Fan Zhang
  • Publication number: 20130111301
    Abstract: A block management method for managing physical blocks of a rewritable non-volatile memory module, and a memory controller and a memory storage device using the same are provided. The method includes maintaining an error information table for recording one or more error correctable physical blocks among the physical blocks and an error bit number corresponding to the one or more error correctable physical blocks. The method further includes selecting a physical block for writing data according to the one or more error correctable physical blocks and the error bit number thereof recorded in the error information table. Accordingly, the data stability of the memory storage device can be improved.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 2, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien-Hua Chu
  • Publication number: 20130104001
    Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 25, 2013
    Applicant: SONY CORPORATION
    Inventor: SONY CORPORATION
  • Publication number: 20130104003
    Abstract: A memory system and a method for recording/reproducing data thereof, the memory system including a flash memory, and a memory controller configured control an operation to record data on the flash memory or to reproduce the recorded data from the flash memory, wherein the memory controller includes an encoder configured to generate an Error Correction Code (ECC) from data that is to be recorded in the flash memory and to convert the generated ECC by using a particular ECC, a memory interface configured to record the data and the converted ECC to the flash memory, and a decoder configured to restore the converted ECC, which is read from the flash memory, by using the particular ECC and to detect and correct an error of the data, which is read from the flash memory, by using the restored ECC, and the particular ECC is an ECC with respect to 0xff data.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 25, 2013
    Applicant: SAMSUNG ELECTRONIC CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8427870
    Abstract: Provided is a method for operating a nonvolatile memory device. In the method, read data is read by means of a read level and logic values for erasure-decoding the read data are set. The bits of the read data corresponding to the range of the set logic values is set as erasure bits, and an erasure decoding operation is performed.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jaehong Kim, Heeseok Eun
  • Publication number: 20130097475
    Abstract: Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Inventors: Chung-Li Wang, Zongwang Li, Shaohua Yang
  • Publication number: 20130091404
    Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 11, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Publication number: 20130091376
    Abstract: A method, system, and computer program product include generating a database copy from a database of a primary virtual machine (VM), provisioning a standby VM with the database copy, detecting a failure associated with the database, and promoting the standby VM to replace the primary VM.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Steve RASPUDIC, Matthew David Patrick Van Dijk
  • Publication number: 20130080854
    Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Richard Nicholas
  • Publication number: 20130080864
    Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.
    Type: Application
    Filed: November 19, 2012
    Publication date: March 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: MICRON TECHNOLOGY, INC.
  • Publication number: 20130073928
    Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.
    Type: Application
    Filed: July 12, 2012
    Publication date: March 21, 2013
    Inventors: Micha Anholt, Naftali Sommer
  • Publication number: 20130067270
    Abstract: Aspects of the subject matter described herein relate to querying and repairing data. In aspects, a component may detect that data on storage has become corrupted. In response, the component may request data from one or more redundant copies of the data and may determine which of the redundant copies, if any, are not corrupted. If a non-corrupted copy is found, the component may send a request that the corrupted data be repaired and may identify the non-corrupted copy to use to repair the corrupted data.
    Type: Application
    Filed: November 23, 2011
    Publication date: March 14, 2013
    Applicant: Microsoft Corporation
    Inventors: Chesong Lee, Thomas J. Miller, Neal R. Christiansen, Matthew S. Garson
  • Publication number: 20130061110
    Abstract: For facilitating data verification using a checksum in conjunction with a sidefile by a processor device in a computing environment, first block signatures having a first size are calculated for first blocks of a first volume stored on a storage device. The first block signatures are stored to a sidefile. Second block signatures having a second size different from the first size are calculated for second blocks of a second volume stored on the storage device. The second block signatures are stored to the sidefile.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Liran ZVIBEL
  • Publication number: 20130061101
    Abstract: A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: SMART STORAGE SYSTEMS, INC.
    Inventors: James Fitzpatrick, Bernardo Rub, James Higgins, Ryan Jones, Robert W. Ellis
  • Publication number: 20130055047
    Abstract: A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: ERAN SHARON, IDAN ALROD
  • Publication number: 20130042147
    Abstract: The disclosed fault analysis rule extraction device includes: an event preprocessing section and a fault analysis rule extraction section. The event preprocessing section merges, with respect to event groups each of which is grouped every certain time period, event groups that can be presumed to occur from the same fault by a cluster analysis. The fault analysis rule extraction section extracts a fault analysis rule useful for a fault analysis by relating event logs to clusters. By the fault analysis rule extraction device of the above configuration, highly accurate fault analysis rule are automatically provided from the event logs of a system.
    Type: Application
    Filed: March 3, 2011
    Publication date: February 14, 2013
    Applicant: NEC CORPORATION
    Inventor: Toshio Tonouchi
  • Publication number: 20130042148
    Abstract: A malfunction analysis apparatus (100) is provided with a malfunction-analysis processor (107), an attribute-extraction processor (108), and an outputter (105). The malfunction-analysis processor (107) obtains a malfunction-contribution degree, which indicates a degree that individual malfunctions (to be called malfunctioning elements, hereafter) contribute to the malfunctioning of the object being analyzed, on the basis of the relative relationship between the data to be analyzed that has, as elements thereof, values generated on the basis of a plurality of indicator values of the object being analyzed, and representative values for the plurality of indicators corresponding to each of the plurality of malfunctions. Then, the malfunctioning elements being generated is specified, on the basis of the obtained malfunction-contribution degree.
    Type: Application
    Filed: April 26, 2011
    Publication date: February 14, 2013
    Applicant: NEC CORPORATION
    Inventors: Ryohei Fujimaki, Hidenori Tsukahara
  • Publication number: 20130031402
    Abstract: A method begins by a dispersed storage (DS) processing module identifying a performance anomaly within a dispersed storage network (DSN). The method continues with the DS processing module identifying a set of collections of records corresponding to the performance anomaly, wherein one of the set of collections of records includes an event record including information regarding an event, a first record including information regarding a dispersed storage (DS) processing module processing an event request to produce a plurality of sub-event requests, and a plurality of records including information regarding a set of DS units processing the plurality of sub-event requests. The method continues with the DS processing module determining whether a reliable significance indication of the performance anomaly is determinable, and when the reliable significance indication of the performance anomaly is not determinable, modifying data collection criteria for one or more of the sets collections of records.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 31, 2013
    Applicant: CLEVERSAFE, INC.
    Inventors: Greg Dhuse, Yogesh Ramesh Vedpathak
  • Publication number: 20130031430
    Abstract: A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Inventor: Eran Sharon
  • Publication number: 20130024741
    Abstract: The present invention provides a data processing method, a data processing system and a receiver. The method includes: performing optical-to-electrical conversion processing on a received current optical data signal, to generate a current electric data signal; performing analog-digital conversion processing on the current electric data signal, to generate a current data block; performing equalization processing on the current data block according to a previous second output data block, to generate a current first output data block, where the previous second output data block is generated by performing forward error correction decoding processing on a previous first output data block, and the previous first output data block is generated by performing equalization processing on a previous data block of the current data block; and performing forward error correction decoding processing on the current first output data block, to generate a current second output data block.
    Type: Application
    Filed: September 26, 2012
    Publication date: January 24, 2013
    Applicant: Huawei Technologies Co., Ltd.
    Inventor: Huawei Technologies Co., Ltd.
  • Publication number: 20130024722
    Abstract: Techniques involving replication of virtual machines at a target site are described. One representative technique includes an apparatus including a virtual machine configured to provide storage access requests targeting a virtual disk. A storage request processing module is coupled to the virtual machine to receive the storage access requests and update the virtual disk as directed by the storage access requests. A replication management module is coupled to the virtual machine to receive the storage access requests in parallel with the storage request processing module, and to store information associated with the storage access requests in a log file(s). The log file may be transferred to a destination as a recovery replica of at least a portion of the virtual disk.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: Microsoft Corporation
    Inventors: Sriravi Kotagiri, Rahul Shrikant Newaskar, Palash Kar, Shreesh Rajendra Dubey