Abstract: A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

Abstract: Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.

Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family comprising a first set of blocks, wherein the first block family comprises a plurality of blocks that have been programmed within at least one of a specified time window or a specified temperature window; identify a second block family comprising a second set of blocks; and responsive to a determining that a threshold criterion is satisfied, combine the first block family and the second block family by appending, to first block family metadata of the first block family, a record referencing the second set of blocks.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Abstract: Storage management techniques involve: acquiring target data in a target storage page in a memory; determining, based on the target data, check information and identification information associated with the target data, the check information being used to verify whether the target data is correct and the identification information being used to identify the target data; and determining, based on the identification information, storage information associated with the target data and the check information, the storage information indicating whether to store the target data and the check information to a persistent storage device. Therefore, the processing efficiency can be improved, and the input/output (I/O) performance can be improved.

Abstract: A system and methods for bandwidth-efficient cryptographic data transfer, utilizing an encoding endpoint device, a decoding endpoint device, a reference codebook, and a plurality of data to encode and decode, which may use specific algorithms on top of block cipher encryption to achieve higher data security and ease the burden on users with regards to computational power, complexity, and bandwidth for communication.

Abstract: Examples described herein include systems and methods for multi-tenant event sourcing and audit logging in a cloud-based computing infrastructure. In an example method, an event package can be received from a first microservice of an application. The event can describe any action performed within the computing infrastructure and can include various types of information. For example, it can include an event type, event ID, object type, object ID, and parent event ID. The event package can be associated with a tenant and only provided to tenant-approved recipients. The recipient can use the event package to automatically carry out steps to recreate and configure an object, or to determine the source of an event or failure within the system.

Abstract: A system and method for data storage, transfer, synchronization, and security using automated system efficacy monitoring and model training, wherein statistical analyses of test datasets are used to determine if the probability distribution of two datasets are within a pre-determined range, and responsive to that determination new encoding and decoding algorithms may be retrained in order to produce new data chunklets. The new data chunklets may then be processed and assigned new codewords which are compiled into an updated codebook which may be distributed back to encoding and decoding systems and devices.

Abstract: A storage system including first storage devices constituting a first logical storage area, second storage devices constituting a second logical storage area; and a storage control apparatus. The storage control apparatus manages the first and second logical storage areas so that the data stored in the first and second logical storage areas have redundancy, and parity data for the data stored in the second logical storage area are stored in parity storage areas arranged in part of the second storage devices. When part of the first storage devices constituting part of the first logical storage area fail, the storage control apparatus generates part of the data stored, before the failure, in the part of the first storage devices, and stores the generated part of the data in at least part of the second parity storage areas in the second logical storage area.

Abstract: A method and device are provided for transmitting a digital signal intended for a network having at least four nodes including two transmitters, a relay and a receiver separated from one another by non-orthogonal links, except between the relay and the destination, between which the link is orthogonal, implementing a spatially distributed network code. The method includes: encoding, in each transmitter, supplying a code word for every block of K bits of information; transmitting, in the transmitters, the code word during ?N transmission intervals, ??[0,1]; jointly, iteratively detecting/decoding, in the relay, in order to separate interfering streams from the transmitters and to determine, for each stream, a vector representing the K bits of information associated with the code word; jointly encoding, in the relay, the two vectors in order to determine redundancy information, and scheduling the relays to transmit the redundancy information during the (1??)N following transmission intervals.

Abstract: According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.

Abstract: A method for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults. A complete set of analytical redundancy relations of the system is built from a set of intermediate relations established between observable and non-observable variables of the system, wherein each intermediate relation is generated by combining two predetermined relations Rj, Rk, each of which is expressed in an implicit form as a tuple (i) of a subset Sj of system variables, (ii) of the set Cj of the support components for said relation, and (iii) of the set Tj of the primary relations used to derive said intermediate relation.

Abstract: Various systems and methods for media defect detection.

Abstract: An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for real-time error correction and decoding by dividing the linear programming problem into independent parallelizable problems so that separate independent portions of the electronic circuit may simultaneously address solutions related to individual bits and/or parity rules. Linear programming is believed to avoid error floors inherent in conventional belief propagation error detection and correction techniques providing a decoding system suitable for high reliability applications.

Abstract: The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable node by using check node to variable node (C2V) messages from a previous iteration that are likely to be correct when generating variable node to check node (V2C) messages.

Abstract: A data storage device includes a non-volatile memory and a controller including a first error correction coding (ECC) engine configured to generate a first codeword corresponding to data to be stored at the non-volatile memory. The data storage device also includes a second ECC engine coupled to the controller and to the non-volatile memory. The second ECC engine is configured to receive a representation of the first codeword from the controller and to perform a decode operation of the representation of the first codeword to correct transmission errors prior to storage of the data in the non-volatile memory.

Abstract: The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit.

Abstract: A computer-implemented method for test case result processing includes receiving, by a test case result processing logic in a processor of a computer, a test result from a test case that executes on the computer; determining, by the test case result processing logic based on a result description file, whether a result description corresponding to the received result exists in the result description file; based on the result description corresponding to the received result existing in the result description file, determining an action description associated with the result description based on an action definition file; and executing an action corresponding to the determined action description.

Abstract: An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.

Abstract: Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.

Abstract: Methods, apparatuses, and computer program products for administering incident pools for incident analysis in a distributed processing system are provided. Embodiments include an incident analyzer receiving a plurality of incidents from an incident queue. The incident analyzer also assigns each received incident to an incident pool having a predetermined initial period of time. The predetermined initial period of time is the time within which the incident pool is open to the assignment of incidents. The incident analyzer calculates an arrival rate that incidents are assigned to the incident pool. The incident analyzer also extends based on the arrival rate, for each incident assigned to the incident pool, the predetermined initial period of time by a particular period of time.

Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.

Abstract: A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.

Abstract: A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.

Abstract: A digital broadcasting system and method of processing data therein are disclosed. According to one embodiment, a digital broadcasting system includes an RS (Reed-Solomon) encoder configured to encode mobile service data for FEC (Forward Error Correction) to build RS frames including the mobile service data and a signaling information table, a signaling encoder configured to encode signaling information including fast information channel (FIC) data, and transmission parameter channel (TPC) data, a group formatter configured to form data groups, wherein at least one of the data groups includes encoded mobile service data, known data sequences, the FIC data and the TPC data, and a transmission unit configured to transmit the broadcast signal including a parade of the data groups.

Abstract: In an electronic apparatus, a soft decision likelihood value is generated and subject to a decoding process supporting a convolutional code; and a data series is interleaved, subjected to an error correction process, and decoded data is generated. A detecting unit, based on information concerning the position of a symbol for which an error has been corrected successfully by the error correction process, estimates whether an error occurs in a symbol for which the error correction process failed and detects the position of a symbol estimated to have an error. A setting unit sets based on the decoded data and information concerning the position of the symbol estimated to have an error, a correction value of the soft decision likelihood value. The electronic device interleaves the order of a correction value series of the soft decision likelihood value and feeds the resulting correction value series back to the decoding process.

Abstract: A method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device. In one embodiment, a method of a custom hardware solution that includes a change in the CPU clock frequency dependency by using programmable logic and a highly parallel array of high capacity flash memory is shown.

Abstract: A transmitting/receiving system includes a first transmitting/receiving apparatus which includes a first transmitting unit and a first receiving unit, and a second transmitting/receiving apparatus which includes a second receiving unit, a detector, a second generator, and a second transmitting unit. The first transmitting unit transmits data with an error detecting code after a bit-number conversion. The first receiving unit receives a response to the data after a bit-number inverse conversion. The second receiving unit subjects the data to a bit-number inverse conversion. The detector detects an error from the error detecting code. The second generator generates a positive or negative acknowledgement depending on the error detection and uses a code which enables distinguishing between positive and negative acknowledgements when a 1-bit error occurs during transportation. The second transmitting unit transmits the acknowledgement after a bit-number conversion to the first transmitting/receiving apparatus.

Abstract: A method of checking the integrity of a dynamic link library (DLL) file called by an application being executed on a handheld medical device is described. The method includes loading a DLL from a read only memory (ROM) to a random access memory (RAM) beginning at a fixed location in the RAM. The DLL includes a first routine for performing a safety critical function of the handheld medical device and a second routine for performing a cyclical redundancy check (CRC) once the DLL is loaded to the RAM. The method includes selectively executing the first routine from the RAM. The method includes selectively executing the second routine from the RAM including: calculating a check value based on the DLL; comparing the check value with a predetermined check value; and indicating that an error is present when the check value is different than the predetermined check value.

Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: The present disclosure provides video transmission systems and methods with video data flows transmitted over a Carrier Ethernet Network at Layer 2 with redundancy in order to provide hitless protection switching and uninterrupted video service delivery, such as during periods of asymmetric congestion or hard network failures. In an exemplary embodiment, the video transmission systems and methods provide the redundancy in a manner similar to 1+1 linear protection with hit-less protection switching. In another exemplary embodiment, the video transmission systems and methods provide encapsulated video signals over Ethernet using standardized Carrier Ethernet frames with additional sequencing information. Optionally, the video transmission systems and methods may also include packet-based forward error correction information for additional resiliency.

Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.

Abstract: A block management method for managing physical blocks of a rewritable non-volatile memory module, and a memory controller and a memory storage device using the same are provided. The method includes maintaining an error information table for recording one or more error correctable physical blocks among the physical blocks and an error bit number corresponding to the one or more error correctable physical blocks. The method further includes selecting a physical block for writing data according to the one or more error correctable physical blocks and the error bit number thereof recorded in the error information table. Accordingly, the data stability of the memory storage device can be improved.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is discussed that includes: a data detector circuit, a symbol selective scaling circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data input guided by a first data set derived from a decoded output to yield a detected output. The symbol selective scaling circuit is operable to selectively scale one or more symbols of a second data set derived from the detected output to yield a scaled data set. The data decoder circuit operable to apply a data decode algorithm to a third data set derived from the scaled data set to yield the decoded output.

Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.

Abstract: A memory system and a method for recording/reproducing data thereof, the memory system including a flash memory, and a memory controller configured control an operation to record data on the flash memory or to reproduce the recorded data from the flash memory, wherein the memory controller includes an encoder configured to generate an Error Correction Code (ECC) from data that is to be recorded in the flash memory and to convert the generated ECC by using a particular ECC, a memory interface configured to record the data and the converted ECC to the flash memory, and a decoder configured to restore the converted ECC, which is read from the flash memory, by using the particular ECC and to detect and correct an error of the data, which is read from the flash memory, by using the restored ECC, and the particular ECC is an ECC with respect to 0xff data.

Abstract: Provided is a method for operating a nonvolatile memory device. In the method, read data is read by means of a read level and logic values for erasure-decoding the read data are set. The bits of the read data corresponding to the range of the set logic values is set as erasure bits, and an erasure decoding operation is performed.

Abstract: Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.

Abstract: A method, system, and computer program product include generating a database copy from a database of a primary virtual machine (VM), provisioning a standby VM with the database copy, detecting a failure associated with the database, and promoting the standby VM to replace the primary VM.

Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.