Adding Special Bits Or Symbols To The Coded Information, E.g., Parity Check, Casting Out 9's Or 11's, Etc. (epo) Patents (Class 714/E11.032)

  • Patent number: 9003153
    Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 7, 2015
    Assignee: Greenliant LLC
    Inventor: Siamak Arya
  • Patent number: 8958330
    Abstract: The present invention discloses a de-rate matching method and device for a downlink traffic channel in a Long Term Evolution (LTE). The method comprises: at a terminal side, dividing a received Transport Block (TB) of a downlink traffic channel, i.e., Physical Downlink Shared Channel (PDSCH), into a plurality of different code blocks; for the first code block, de-rate matching of data is implemented by a segmented copy method; and for the other code blocks, de-rate matching is implemented by a table lookup method. By applying the method and device provided in the embodiments of the present invention, the execution speed of the de-rate matching can be improved, and the overall processing speed of the downlink traffic channel can be improved.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 17, 2015
    Assignee: ZTE Corporation
    Inventor: Xiaojing Ling
  • Patent number: 8949702
    Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 3, 2015
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Jun Xiao, Ming Jin
  • Patent number: 8924829
    Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Eliya Babitsky, Noam Zach
  • Patent number: 8898539
    Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
  • Patent number: 8874987
    Abstract: Systems and methods for data transport, comprising encoding one or more streams of input data with one or more low density parity check (LDPC) encoders, corresponding to one or more polarization/spatial mode branches. One or more encoded data streams are mapped to symbols, wherein the mapper is configured to assign bits of the symbols to a signal constellation and to associate the bits of the symbols with signal constellation points. A signal constellation is formulated which minimizes a mean-square error of the signal constellation representing the source. The optimum signal constellation size is adjusted to improve transmission quality by adjusting the signal constellation an optical signal to noise ratio (OSNR), wherein the signal constellation is selected using a look-up table (LUT); and the symbols are modulated in accordance with the output of the mapper onto a transmission medium.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: October 28, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Ivan B. Djordjevic, Lei Xu, Ting Wang
  • Patent number: 8775899
    Abstract: An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Limited
    Inventor: Shiro Kamoshida
  • Patent number: 8775902
    Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventor: Takeshi Ootsuka
  • Patent number: 8744071
    Abstract: A computing system securely stores data to a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an encryptor and error encoder to encrypt and encode the data for dispersal utilizing a write command to the storage units. The storage units store the encrypted and encoded data when receiving the write command and the encrypted and encoded data.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: June 3, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Wesley Leggette, Jason K. Resch
  • Publication number: 20140136917
    Abstract: Devices and/or methods for managing a buffer containing failed data may utilize side information related to the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors and/or a local host requested status for buffered or unbuffered failed data.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Hieu Nguyen
  • Publication number: 20140136930
    Abstract: Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Hieu Nguyen
  • Publication number: 20140129908
    Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: Texas Instruments, Incorporated
    Inventors: Prohor Chowdhury, Alexander Tessarolo
  • Publication number: 20140122959
    Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Inventors: Lei Chen, Fan Zhang
  • Publication number: 20140122979
    Abstract: A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: LSI CORPORATION
    Inventors: Lei Chen, Johnson Yen, Zongwang Li, Chung-Li Wang
  • Publication number: 20140115416
    Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.
    Type: Application
    Filed: November 2, 2012
    Publication date: April 24, 2014
    Inventor: Laurence H. Cooke
  • Publication number: 20140115419
    Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Inventors: Se-Jin Ahn, Yong-Hyeon Kim, Sung-Up Choi, Yong-Kyeong Kim
  • Publication number: 20140115418
    Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: LSI CORPORATION
    Inventors: Ramprasad Raghavan, Nitin Satishchandra Kabra, Gurvinder Pal Singh
  • Publication number: 20140115430
    Abstract: Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: LSI Corporation
    Inventor: Fan Zhang
  • Publication number: 20140108880
    Abstract: systems and methods for data processing particularly related local iteration randomization in a data decoding circuit.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: LSI Corporation
    Inventors: Fan Zhang, Wu Chang, Shaohua Yang, Ming Jin
  • Publication number: 20140108881
    Abstract: In one embodiment, a system for encoding data includes logic adapted for receiving data having one or more sub data sets, a C1 encoder module adapted for generating a plurality of C1 codewords during C1 ECC encoding of the one or more sub data sets, logic adapted for interleaving the plurality of C1 codewords into C1 codeword interleaves (CWIs), each CWI having a predetermined number of C1 codewords interleaved therein, a C2 encoder module adapted for generating a plurality of C2 codewords during C2 ECC encoding of the one or more sub data sets, wherein each C2 codeword has at most one symbol from each C1 codeword in each CWI, and wherein each C2 codeword has one symbol from at least two different C1 codewords in each CWI, and logic adapted for writing the one or more encoded sub data sets to a storage medium.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mario Blaum, Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer
  • Publication number: 20140101509
    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Shaohua Yang, Fan Zhang, Jun Xiao
  • Publication number: 20140095954
    Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: LSI CORPORATION
    Inventors: Chung-Li Wang, Lei Chen, Fan Zhang, Shaohua Yang, Qi Qi
  • Publication number: 20140095956
    Abstract: Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Serkan Ozdemir, Qiong Cai
  • Publication number: 20140089767
    Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: LSI CORPORATION
    Inventors: Wu Chang, Fan Zhang, Yang Han, Ming Jin
  • Publication number: 20140089758
    Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Zion S. Kwok, Scott Nelson
  • Publication number: 20140075272
    Abstract: A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v?)) based on a coded binary word (v?). The error syndrome bit sequence (s(v?)) indicates whether the coded binary word (v?) is a code word of an error correction code (C) used for coding the coded binary word (v?). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v?)), if the error syndrome bit sequence (s(v?)) indicates that the coded binary word (v?) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)?)—caused by the test bit sequence (Ti)—of the circuit.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt
  • Publication number: 20140075261
    Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: LSI CORPORATION
    Inventors: Zongwang Li, Chung-Li Wang, Shaohua Yang
  • Publication number: 20140075264
    Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
  • Publication number: 20140068357
    Abstract: Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: AOPTIX TECHNOLOGIES, INC.
    Inventors: Eric Saint Georges, Joseph Shiran, Scott Alan Young
  • Publication number: 20140068397
    Abstract: A partial outer parity management system generates a product code based on a partial data block write to a data block and partial outer parity generated by a previous partial data block write to the data block. In one implementation, a storage device includes cache storage circuit accessible by the parity generator, the cache storage circuit being configured to cache the partial outer parity generated by the previous partial data block write to the data block in a partial outer parity cache designated for association with the product code.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventor: Timothy Richard Feldman
  • Publication number: 20140063637
    Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Lu Pan, Seongwook Jeong, Haitao Xia
  • Publication number: 20140068375
    Abstract: The present invention provides a low density parity check (LDPC) code system and method of using such a system. A transmitted LDPC code block size may be chosen such that the minimum transmitted block size is minimized. Further, the system provides for intermediate LDPC code block size support. Finally, a common decoder architecture may be used to decode different LDPC code rates and block sizes.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: Hughes Network Systems, LLC
    Inventors: Mustafa Eroz, Lin-Nan Lee
  • Publication number: 20140068389
    Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: LSI CORPORATION
    Inventors: Ngok Ning Chu, Lei Chen, Herjen Wang, Johnson Yen
  • Publication number: 20140068394
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Fan Zhang, Yang Han, Xuebin Wu, Shaohua Yang
  • Publication number: 20140068368
    Abstract: The present inventions are related to systems and methods for calculating data quality metrics for an LDPC decoder, and particularly for calculating a fractional unsatisfied check quality metric.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Fan Zhang, Ming Jin, Wu Chang, Haitao Xia
  • Publication number: 20140068367
    Abstract: The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Fan Zhang, Anatoli A. Bolotov, Lav D. Ivanovic
  • Publication number: 20140059403
    Abstract: In some embodiments, a method includes accepting a code word of a composite Error Correction Code (ECC), which was produced by encoding data with multiple component ECCs, and which was received with one or more reception parameters. One or more of the component ECCs are decoded, but without fully decoding the code word. The one or more reception parameters are estimated based on the decoded component ECCs. In other embodiments, a method includes accepting a code word of an ECC, which encodes data and which was received with one or more reception parameters. An Error Locator Polynomial (ELP), having one or more roots that indicate respective locations of one or more errors in the code word, is derived from the accepted code word. The one or more reception parameters are estimated based on the ELP.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventors: Naftali Sommer, Micha Anholt
  • Publication number: 20140053038
    Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
    Type: Application
    Filed: November 8, 2012
    Publication date: February 20, 2014
    Applicant: LSI CORPORATION
    Inventors: Alexander Alexandrovich Petyushko, Anatoli Aleksandrovich Bolotov, Yang Han, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov
  • Publication number: 20140053049
    Abstract: The present disclosure describes methods and apparatuses for improved transport block decoding in devices capable of wireless communication, which may include user equipment and network entities. For example, the present disclosure presents methods and apparatuses for decoding a code block from a plurality of code blocks corresponding to a transport block, obtaining a reliability indicator that identifies a reliability of the decoding of the code block, comparing the reliability indicator to a reliability threshold, and determining whether to decode a subsequent code block from the plurality of code blocks based on the comparing. Furthermore, these methods and apparatuses may include determining not to decode at least one subsequent code block of the transport block where the comparing indicates that the reliability indicator is less than the reliability threshold. As such, device power is not unnecessarily consumed by decoding likely superfluous code blocks.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Jinghu CHEN, Wanlun Zhao, Michael Mingxi Fan, Fuyun Ling, Peter John Black, Krishna Kiran Mukkavilli, Weihong Jing, Jia Tang
  • Publication number: 20140053047
    Abstract: A method for receiving and storing a packet of symbols. The method decodes the packet of symbols using a first decoding algorithm, and if the first decoding algorithm fails to correctly decode the packet of symbols, then the method decodes the packet of symbols using a second decoding algorithm. If the second decoding algorithm fails to decode the packet of symbols, then a third decoding algorithm is used. The third decoding algorithm can be sub-packet decoding, where a first sub-packet is part of the packet of symbols. If the first sub-packet is decoded successfully, then the method generates a channel estimate using the properly decoded information, and then uses that channel estimate to decode a subsequent sub-packet using the channel estimate, where the second sub-packet is a set of symbols that are a portion of the packet of symbols.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicants: CARNEGIE MELLION UNIVERSITY, GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zheng Li, Fan Bai, Vijaykumar Bhagavatula
  • Publication number: 20140040697
    Abstract: A system for detecting an address or data error in a memory system. During operation, the system stores a data block to an address by: calculating a hash of the address; using the calculated hash and data bits from the data block to compute ECC check bits; and storing the data block containing the data bits and the ECC check bits at the address. During a subsequent retrieval operation, the memory system uses the address to retrieve the data block containing the data bits and ECC check bits. Next, the system calculates a hash of the address and uses the calculated hash and the data bits to compute ECC check bits. Finally, the system compares the computed ECC check bits with the retrieved ECC check bits to determine whether an error exists in the address or data bits, or if a data corruption indicator is set.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventor: Paul N. Loewenstein
  • Publication number: 20140040709
    Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Inventors: Mark Pereira, Ling Yang, Govendra Gupta
  • Publication number: 20140033001
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventors: Fan Zhang, Kevin G. Christian, Kaitlyn T. Nguyen, Weijun Tan
  • Publication number: 20140032997
    Abstract: A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: ?(n)=f1n?fnn2 mod K, where the QPP coefficients f1 and f2 are designed to provide good error performance for a given block length K.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Inventor: Jung-Fu Cheng
  • Publication number: 20140032989
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventors: Weijun Tan, Shaohua Yang, Kelly K. Fitzpatrick, Xuebin Wu, Fan Zhang
  • Publication number: 20140026021
    Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Inventors: Eric Lyell Hill, Richard L. Schober, JR., Hungse Cha
  • Publication number: 20140026022
    Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Inventors: Eric Lyell HILL, Richard L. SCHOBER, JR., Hungse CHA
  • Publication number: 20140026010
    Abstract: A method for decoding an ECC, in a decoder that includes at least first and second root search units, includes accepting at least first and second Error Locator Polynomials (ELPs) that have been computed over respective first and second code words of the ECC. A criterion depending on the ELPs is evaluated. One of first and second modes is selected based on the criterion. One or more first roots of the first ELP and one or more second roots of the second ELP are found using the selected mode, and the first and second code words are decoded using the first and second roots. In the first mode, the first and second root search units are combined and simultaneously find the first roots. In the second mode, the first and second root search units operate separately, and simultaneously identify the first roots and the second roots, respectively.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Inventor: Micha Anholt
  • Patent number: 8633838
    Abstract: Methods and apparatus for compressing data for network transport in support of continuous availability of applications are described. One computer-implemented method of compressing data includes receiving a current instance of data in an input buffer. A candidate chunk of data is selected from the input buffer. A signature hash is computed from a signature length range of data within the candidate chunk. A matching dictionary entry having a matching signature hash from a multi-tiered dictionary is identified. The matching dictionary entry prospectively identifies a location of a prior occurrence of a selected range of consecutive symbols including the signature length range of data within at least one of the current instance of data and a prior instance of data in the input buffer. A dedupe processed representation of the instance of data is formed wherein a dedupe item is substituted for the selected range of consecutive symbols if the selected range is verified as recurring.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 21, 2014
    Assignee: Neverfail Group Limited
    Inventors: Patrick Terence Falls, Lyndon John Clarke, Wouter Senf
  • Publication number: 20140019824
    Abstract: Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Chandra C. Varanasi