Abstract: In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: A method for determining a correctness of an actually received timestamp is provided. A communication network includes a master clock, a first ECU having a first slave clock, a validator having a second slave clock, and a first communication bus. The first ECU uses a first communication standard having a deterministic scheme. The method includes synchronizing, at the first ECU, a time of the first slave clock to a global time of the master clock, synchronizing, at the validator, a time of the second slave clock to the global time of the master clock, predicting, at the validator, a timestamp to be received in an actual communication cycle from the first ECU based on the deterministic scheme of the communication standard used by the first ECU, and comparing, at the validator, the predicted timestamp with the actually received timestamp from the first ECU.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

Abstract: Systems and devices can include forward error correction (FEC) logic to identify a correctable error in the first flit, and correct the correctable error using three error correcting code (ECC) groups. System and devices can also include an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit; and a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.

Abstract: A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

Abstract: A display circuit device includes a CPU, a display control circuit, and a drive signal generation circuit. The drive signal generation circuit includes a generation circuit that generates a first CRC value that is a CRC value of command data received from the CPU, and a transmission circuit that transmits the first CRC value to the CPU. The CPU includes an expected value generation circuit that generates a second CRC that is a CRC value of command data before being input to the drive signal generation circuit, a reception circuit that receives the first CRC value, a comparison circuit that compares the first CRC value with the second CRC value, and a control circuit that executes control based on a comparison result obtained by the comparison circuit.

Abstract: Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

Abstract: A method for accessing a data source is described. A communication for the data source is received from a proxy at a sidecar. The proxy mirrors the communication so that the communication is provided to the data source and the sidecar. The sidecar includes a dispatcher and service(s). The dispatcher receives the communication, is data agnostic, and provides the communication to the data source and service(s). The service(s) inspect the communication. In some embodiments, the dispatcher is an open systems interconnection (OSI) Layer 4 dispatcher and the service(s) include OSI Layer 7 service(s). The service(s) perform function(s) based on the communication.

Abstract: Systems and methods for performing open-loop quantum error mitigation using quantum measurement emulations are provided. The open-loop quantum error mitigation methods do not require the performance of state readouts or state tomography, reducing hardware requirements and increasing overall computation speed. To perform a quantum measurement emulation, an error mitigation apparatus is configured to stochastically apply a quantum gate to a qubit or set of qubits during a quantum computational process. The stochastic application of the quantum gate projects the quantum state of the affected qubits onto an axis, reducing a trace distance between the quantum state and a desired quantum state.

Abstract: An apparatus comprising: a memristor; means for wirelessly receiving, from another apparatus, a time-varying signal; means for enabling, responsive to the received time-varying signal, provision of one or more pulses to the memristor to change an electrical characteristic of the memristor; means for wirelessly signalling to the other apparatus when the electrical characteristic of the memristor reaches a threshold value; and means for re-setting the electrical characteristic of the memristor.

Abstract: An autonomous vehicle (AV) implements a health protocol that may reduce pathogen transmission between users of the AV. The AV is equipped with a thermal sensor that captures a body temperature of a user. The AV compares the user's temperature to a threshold temperature, and if the user's temperature exceeds the threshold temperature, the AV performs checks to ensure that the user's planned trip follows current regulations or recommendations. For example, the AV confirms that the user is traveling between the user's home and a healthcare facility. If the trip is permitted, the AV enables the user to enter the AV. The AV may include a disinfectant system for disinfecting the passenger compartment or surfaces after the user exits the AV.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Data communication is made more efficient by removing the need to copy data in the networking stack, using hardware accelerated end-to-end checksum calculation, and supporting transmission formatting of data and header for special cases.

Abstract: A vehicle display apparatus has a display and a control unit. The control unit detects whether or not an error recognizable by users of the vehicle has occurred in an image on the display on the basis of the result of matching between a first error detection code, which is generated on the basis of image data transmitted to a display drive unit, and a second error detection code, which is generated on the basis of the image data received by the display drive unit, to determine whether notification is required or not, and provides notification on deterioration in the reliability of the image on the display by controlling light-emitting elements and sound output units provided on the vehicle display apparatus or by way of a superordinate device.

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

Abstract: A method and apparatus for processing stream data are provided. The method may include: acquiring a to-be-adjusted number of target execution units, the target execution unit referring to a unit executing a target program segment in a stream computing system; adjusting a number of the target execution units in the stream computing system based on the to-be-adjusted number; determining, for a target execution unit in at least one target execution unit after the adjustment, an identifier set corresponding to the target execution unit, an identifier in the identifier set being used to indicate to-be-processed data; and processing, through the target execution unit, the to-be-processed data indicated by the identifier in the corresponding identifier set.

Abstract: A communication device and a data collection system that, when lower connection devices are connected to a communication device, improve efficiency of communication between the communication device and an upper connection device. There is an acquirer that acquires data from the lower connection devices, and a transmission setter that sets a transmission period, which is a time interval in which the data acquired by the acquirer from the lower connection devices is compiled and the compiled data is transmitted to the upper connection device as transmission data, to be equal to or longer than a communication period that is the longest among communication periods of the lower connection devices. Further, there is a transmitter that transmits the transmission data to the upper connection device with the transmission period that is set by the transmission setter.

Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.

Abstract: The present invention discloses a de-rate matching method and device for a downlink traffic channel in a Long Term Evolution (LTE). The method comprises: at a terminal side, dividing a received Transport Block (TB) of a downlink traffic channel, i.e., Physical Downlink Shared Channel (PDSCH), into a plurality of different code blocks; for the first code block, de-rate matching of data is implemented by a segmented copy method; and for the other code blocks, de-rate matching is implemented by a table lookup method. By applying the method and device provided in the embodiments of the present invention, the execution speed of the de-rate matching can be improved, and the overall processing speed of the downlink traffic channel can be improved.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.

Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

Abstract: Systems and methods for data transport, comprising encoding one or more streams of input data with one or more low density parity check (LDPC) encoders, corresponding to one or more polarization/spatial mode branches. One or more encoded data streams are mapped to symbols, wherein the mapper is configured to assign bits of the symbols to a signal constellation and to associate the bits of the symbols with signal constellation points. A signal constellation is formulated which minimizes a mean-square error of the signal constellation representing the source. The optimum signal constellation size is adjusted to improve transmission quality by adjusting the signal constellation an optical signal to noise ratio (OSNR), wherein the signal constellation is selected using a look-up table (LUT); and the symbols are modulated in accordance with the output of the mapper onto a transmission medium.

Abstract: An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.

Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.

Abstract: A computing system securely stores data to a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an encryptor and error encoder to encrypt and encode the data for dispersal utilizing a write command to the storage units. The storage units store the encrypted and encoded data when receiving the write command and the encrypted and encoded data.

Abstract: Devices and/or methods for managing a buffer containing failed data may utilize side information related to the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors and/or a local host requested status for buffered or unbuffered failed data.

Abstract: Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data.

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract: A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.

Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated.

Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.

Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.

Abstract: Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.

Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

Abstract: In one embodiment, a system for encoding data includes logic adapted for receiving data having one or more sub data sets, a C1 encoder module adapted for generating a plurality of C1 codewords during C1 ECC encoding of the one or more sub data sets, logic adapted for interleaving the plurality of C1 codewords into C1 codeword interleaves (CWIs), each CWI having a predetermined number of C1 codewords interleaved therein, a C2 encoder module adapted for generating a plurality of C2 codewords during C2 ECC encoding of the one or more sub data sets, wherein each C2 codeword has at most one symbol from each C1 codeword in each CWI, and wherein each C2 codeword has one symbol from at least two different C1 codewords in each CWI, and logic adapted for writing the one or more encoded sub data sets to a storage medium.

Abstract: systems and methods for data processing particularly related local iteration randomization in a data decoding circuit.

Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

Abstract: A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v?)) based on a coded binary word (v?). The error syndrome bit sequence (s(v?)) indicates whether the coded binary word (v?) is a code word of an error correction code (C) used for coding the coded binary word (v?). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v?)), if the error syndrome bit sequence (s(v?)) indicates that the coded binary word (v?) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)?)—caused by the test bit sequence (Ti)—of the circuit.

Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

Abstract: Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments.

Abstract: The present inventions are related to systems and methods for calculating data quality metrics for an LDPC decoder, and particularly for calculating a fractional unsatisfied check quality metric.

Abstract: The present invention provides a low density parity check (LDPC) code system and method of using such a system. A transmitted LDPC code block size may be chosen such that the minimum transmitted block size is minimized. Further, the system provides for intermediate LDPC code block size support. Finally, a common decoder architecture may be used to decode different LDPC code rates and block sizes.

Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.

Abstract: The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder.

Abstract: A partial outer parity management system generates a product code based on a partial data block write to a data block and partial outer parity generated by a previous partial data block write to the data block. In one implementation, a storage device includes cache storage circuit accessible by the parity generator, the cache storage circuit being configured to cache the partial outer parity generated by the previous partial data block write to the data block in a partial outer parity cache designated for association with the product code.