Abstract: A method and an apparatus for diagnosing an electronic apparatus are provided. The device for diagnosing an electronic device includes a master diagnosis block that generates a control signal when a diagnosis mode is started, a multiplexer that sequentially outputs a diagnosis power through a diagnosis power path based on the control signal, a slave diagnosis block that is sequentially supplied the diagnosis power through the diagnosis power path and generates diagnosis data of a power management circuit of the electronic device by using the diagnosis power, a modulator that transmits the diagnosis data by modulating a power signal of the diagnosis power path, and a demodulator that receives the diagnosis data by demodulating the power signal of the diagnosis power path and provides the diagnosis data to the master diagnosis block.

Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.

Abstract: Methods and apparatuses are provided for MRAM devices utilizing spin transfer torque. A device includes a substrate; an MTJ formed over the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; and a PSM layer formed over the free layer of the MTJ. The PSM layer, i.e., a chiral material layer, may be formed adject to a free layer (or adjacent to a TBL, which is adjacent to the free layer) of the MTJ, providing an additional source of spin-transfer-torque, and providing MTJ devices that are operable with lower switching current.

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Error correction in network packets using lookup tables are disclosed herein. The method can include extracting soft information from copies of a network packet, using the soft information to select positions in a payload of the network packet with uncertain values of bits, changing values at the positions to a combination of values to obtain a modified payload of the network packet, and calculating the CRC for the modified payload. When the modified payload matches an error detection code in the network packet, errors in the payload are corrected.

Abstract: Methods and systems described herein are directed to encoding information bits for transmission. The methods can include receiving a set of information bits (900) and determining a set of parity check bits (910). The set of information bits is concatenated with the set of parity check bits (920), and the information bits are polar encoded into a set of information bits and frozen bits (930). The encoded set of information bits is transmitted to a wireless receiver (940). In particular embodiments, each parity check bit in the set of parity check bits is the binary sum of the values of all bits in front of it. Other embodiments include generating a set of parity check bits based on a systematic block code on the least reliable bits of the set of information bits. The methods and systems described herein may be applied to 3GPP 5G mobile communication systems.

Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.

Abstract: Methods and devices for recovering data stored in a non-volatile storage device are provided. Data may be recovered for memory cells associated with a word line that cannot be read using ECC that was calculated based on the data stored on that word line. This allows recovery for situations such as a word line shorting to the substrate or two adjacent word lines shorting together. When programming memory cells associated with a group of word lines, parity bits may be calculated and stored in memory cells associated with an additional word line in the memory device. When reading memory cells associated with one of the word lines in the group, an otherwise unrecoverable error may occur. By knowing which word line is defective, its data may be recovered using the parity bits and the data of all of the other word lines in the group.

Abstract: Performing packet forward error correction on received data, including: receiving packets including parity packets from a data stream; reading identifier information in a packet header to determine if there were at least one dropped packet in the data stream; processing remaining packets of the received packets when it is determined that there were at least one dropped packet, wherein the remaining packets including the parity packets are processed to recover the at least one dropped packet; and inserting the at least one recovered packet back into another data stream.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation.

Abstract: An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (Npad) of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad?1)th bit groups indicated by a shortening pattern with zeros, mapping information bits to bit positions which are not padded in Bose Chaudhuri Hocquenghem (BCH) information bits, BCH encoding the BCH information bits to generate Low Density Parity Check (LDPC) information bits, and LDPC encoding the LDPC information bits to generate a zero-padded codeword, wherein the shortening pattern is defined as an order of bit groups defined as 6, 5, 4, 9, 3, 2, 1, 8, 0, 7, 10 and 11.

Abstract: This invention relates to field of cloud storage technology and especially relates to a cloud storage data access method, apparatus and system.

Abstract: Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (?)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (?)}(0)(x).

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

Abstract: Embodiments of the invention provide a packet encoding scheme to ensure unequal error protection to different bits in a packet or in multiple packets. In one embodiment, a method to process bits in a bit stream comprises scrambling the bit stream; separating the scrambled bit stream into a high priority bit stream with an order of high priority bits from left to right and a low priority bit stream with an order of low priority bits from left to right; rearranging the bits by embedding the high priority bits in the low priority bit stream while preserving the two orders, the rearranged bit stream including blocks of bits, each block including one or more high priority bits disposed left of corresponding one or more low priority bits to provide protection for the high priority bits against noise which is at least equal to protection for the low priority bits; and modulating the rearranged bit stream using Gray encoding method to produce an encoded bit stream.

Abstract: The present disclosure relates generally to data decoding, and more particularly to non-binary iterative decoders. Non-binary LDPC codes and LDPC decoders that may be used to decode non-binary LDPC codes are disclosed. Systems and methods are also disclosed that compute messages related to non-binary LDPC codes, in a LLRV form and in a metric vector form and to process these messages in non-binary LDPC decoders. Systems and methods are additionally disclosed that convert messages between the LLRV form and the metric vector form. The implementation and use of non-binary low density parity check code decoders, the computation of messages in the LLRV and metric vector forms, and the use of message conversion systems and methods, according to this disclosure, may provide increased information relating groups of codeword bits, increased computational efficiency, and improved application performance.

Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.

Abstract: It is an object of the present invention to provide a low density parity check codes decoder that can decode an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder according to the present invention is configured to enable decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix.

Abstract: Disclosed is an effective high-speed encoding method using a parity-check matrix proposed in an IEEE 802.1x standard for high-speed low-density parity-check encoding. In the prior art, encoding was performed by blocking and dividing the parity-check matrix of the LDPC code and through relevant matrix equations, or encoding was performed by an encoding apparatus that divides a matrix multiplication operation of a generated matrix acquired by using an arbitrary parity-check matrix of a quasi-cyclic (QC) LDPC code and information vectors into two sequential steps and implements each step as a cyclic shift-register.

Abstract: A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups; determining an order of the plurality of groups to be shortened, based on a ratio of a number of bits to be shortened to a number of bits to be punctured; determining a length of an information word to be obtained by shortening the plurality of groups; shortening the plurality of groups on a group basis in the determined order based on the determined length of the information word; and LDPC-encoding a shortened information word.

Abstract: Auto-detection and configuring systems and methods for interconnected, position dependent control devices are disclosed. Embedded identification and configuration keys are associated with each of the control devices in a network, such that specific connection nodes for each controller may be determined by electronically reading the identification as the control devices are installed. Hardware and software compatibility issues may be detected and resolved, including self configuring of the control devices with the proper software where possible. Otherwise, error conditions are signaled.

Abstract: Disclosed are an apparatus and a encoding method using a turbo code and a unit and a method of permutation. The apparatus for encoding using a turbo code according to an exemplary embodiment of the present invention includes: a first encoder that encodes 3 bits inputted from first to third blocks each of which is formed of N bits respectively, with recursive systematic convolutional codes to output a first parity bit; a permutation unit that permutates the 3 bits; a second encoder that encodes the permutated 3 bits with the recursive systematic convolutional codes to output a second parity bit; and a puncturing unit that optionally removes the first parity bit and the second parity bit in consideration of a coding rate of a predetermined turbo code to control the coding rate.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

Abstract: A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory.

Abstract: A memory includes an internal data block and a temporary storing unit. The internal data block stores internal data of the memory. The temporary storing unit temporarily stores the internal data of the memory after the memory is powered on.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

Abstract: Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM symbol, transmitting the base LDPC code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, and transmitting the base LDPC code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data signal. The first signal line electrically couples the transmitter with the receiver. A second signal line carries a second data signal redundant to the first signal. The second signal line electrically couples the transmitter with the receiver. The receiver evaluates the first data signal to determine the presence of an error and the second node uses the second data signal if an error is detected in the first data signal.

Abstract: A continuous redundancy check method and apparatus receives (110) at least one data bit of a block's payload, calculates (120) a partial redundancy check value using the at least one data bit, compares (130) the partial redundancy check value with a reference value, and stores (134, 138) in an index an indication of whether the calculated redundancy check value matched the reference value. Meanwhile, the at least one data bit is also stored (140) in a data memory. As additional data bits of the payload are received, cumulative partial redundancy check values are calculated and compared to the reference value. When the complete payload has been stored (140), the index is analyzed (160, 165) to determine if a block error has been detected by the redundancy check functions. This continuous redundancy check method and apparatus allows a receiver to quickly determine whether a block error has occurred, especially when there may be padding (or dummy) bits in the block's payload.

Abstract: A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

Abstract: A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A sensor device for an electronic apparatus, is provided with: a sensing structure generating a first detection signal; and a dedicated integrated circuit, connected to the sensing structure, detecting, as a function of the first detection signal, a first event associated to the electronic apparatus and generating a first interrupt signal upon detection of the first event. The dedicated integrated circuit detects the first event as a function of a temporal evolution of the first detection signal, and in particular as a function of values assumed by the first detection signal within one or more successive time windows, and of a relation between these values.

Abstract: Redundant information may be stored separately and contiguously with encoded user data such that all redundant information is co-located. Boundaries may be defined as to how error correction coding is processed such that redundant information may be corrected independently from encoded user data. By providing this ability many controller related issues are addressed and the propagation of errors and the effects thereof may be reduced.