Control Processors, E.g., For Sensors, Actuators, Etc. (epo) Patents (Class 714/E11.059)
  • Publication number: 20120124417
    Abstract: A display apparatus and a method for updating a micom code thereof are provided. According to the display apparatus, if an error occurs while a CPU is updating a micom code, a micom may drive the CPU using a system code. Accordingly, even if an error occurs in the process of updating the micom code, the display apparatus may be restored automatically without a jig apparatus.
    Type: Application
    Filed: July 13, 2011
    Publication date: May 17, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: In-beom KIM
  • Publication number: 20110271141
    Abstract: Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
  • Publication number: 20110191638
    Abstract: A parallel computer system includes a first, a second, and a third apparatuses. The first apparatus includes a first arithmetic processing unit that stores first information regarding execution of a first program stored in a first area of a first storage device in a second area of the first storage device, outputs the first information, and sends a first notification of output of the first information. The second apparatus includes a second arithmetic processing unit that stores second information regarding execution of a second program stored in a third area of a second storage device in a fourth area of the second storage device, receives the first notification from the first apparatus, and outputs the second information. The third apparatus includes a third arithmetic processing unit that stores the first information and the second information in a third storage device.
    Type: Application
    Filed: January 18, 2011
    Publication date: August 4, 2011
    Applicant: Fujitsu Limited
    Inventors: Jun Moroo, Masahiko Yamada