Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.

Abstract: Systems and methods are provided for arbitrating sensor and actuator signals in various devices. One system includes input/output (I/O) circuitry, redundant computation circuits coupled to the I/O circuitry, and an arbitration circuit coupled between the I/O circuitry and the redundant computation circuits. The I/O circuitry is configured to be coupled to multiple non-redundant systems, and the redundant computation circuits are configured to be coupled to one of multiple system buses. One such device is an aircraft including multiple non-redundant systems and a plurality of system buses that are configured to transmit redundant messages to the non-redundant systems.

Abstract: The flight control system comprises: at least one actuator (13) for a mobile surface of the said aircraft; a flight control module (12) in communication with the said actuator (13), the said module comprising at least a first and a second computer (14-1, 14-2, 14-3, 15-1, 15-2, 15-3), each computer being adapted for calculating a control command established according to at least one predetermined law for control of the said flight surface; the said actuator (13) comprising logical means (18, 19) adapted for comparing the commands of the said computers (14-1, 14-2, 14-3, 15-1, 15-2, 15-3) and for determining on the basis of these commands the action to be executed on the said mobile surface. The aircraft comprises such a system.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: A method of storing system data, and a memory controller and a memory storage apparatus using the same are provided. The method includes determining whether the unused storage space of a system physical erase unit is enough for storing updated system data. The method further includes, if the unused storage space of the system physical erase unit is not enough for storing the updated system data, selecting an empty physical erase unit, writing the updated system data into at least one first physical program unit of the selected physical erase unit and writing dummy data into a second physical program unit of the selected physical erase unit.

Abstract: A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed.

Abstract: When writing data to a first-type FM part, an FM controller of a flash memory device (A1) generates a redundant code, and (A2) writes the data and the redundant code. when reading the written data, the flash memory controller (B1) reads the data and the redundant code, (B2) corrects any bit errors based on the redundant code, (B3) generates error correction information including positions of the bit errors occurring and values before the bit errors occurred, and (B4) writes the error correction information to a second-type FM part.

Abstract: A system maintains a plurality of system logs and a plurality of system traces. The system extracts data from the plurality of system logs and system traces, and combines the extracted data into a centralized history of system logs and system traces. The system examines the centralized history of system logs and system traces to identify issues and problems in the system, and further identifies the issues and problems that require attention. The system also identifies a person or a group that is responsible for the identified issues and problems, and transmits a message to the identified person or group informing the identified person or group of the identified issues and problems.

Abstract: An example system includes a bus, a logic device, a controller, and a non-volatile memory. The bus is configured to propagate data including at least system console output data. The logic device is configured to monitor the data on the bus and to store the system console output data in a buffer. The controller is configured to detect a system error, and, in response to the system error, to acquire at least a portion of the system console output data from the buffer. The non-volatile memory is configured to store the portion of the system console output data acquired by the controller.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block.

Abstract: In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

Abstract: Systems and methods are disclosed for handling unclean shutdowns for a system having non-volatile memory (“NVM”). In some embodiments, the system can leverage from information obtained from index pages in order to efficiently reconstruct logical-to-physical mappings after an unclean shutdown event. In other embodiments, the system can reconstruct logical-to-physical mappings by leveraging from context information stored in a NVM. In further embodiments, context information can be used in conjunction with index pages to reconstruct logical-to-physical mappings after an unclean shutdown.

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract: A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory.

Abstract: A method begins by a dispersed storage (DS) processing module receiving an access request for a customized preview of multi-media content from an accessing device that possesses first sub-sets of encoded data slices, wherein the multi-media content is segmented into data segments, wherein each data segment is encoded to produce a plurality of sets of encoded data slices and wherein the plurality of sets of encoded data slices includes the plurality of first sub-sets of encoded data slices and a plurality of second sub-sets of encoded data. The method continues with the DS processing module identifying a set of data segments corresponding to the customized preview of the multi-media content. The method continues with the DS processing module sending, to the accessing device, at least one encoded data slice of a second sub-set of encoded data slices that corresponds to a data segment of the set of data segments.

Abstract: A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

Abstract: Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.

Abstract: An information processing apparatus which includes at least two controllers and is capable of positively detecting a startup error. Memory devices are connected to the controllers, respectively. A CPU of each controller accesses the memory device connected to the other controller via a bus bridge, identifies a startup stage to which the startup process has proceeded during the start of the self-controller, writes the identified startup stage as startup information into the memory device connected to the other controller, and detects whether or not an abnormality occurs during the startup of the other controller with reference to the startup information written into the memory device connected to the self-controller.

Abstract: For coordinated disaster recovery, a reconciliation process is performed for resolving intersecting and non-intersecting data amongst disaster recovery systems for takeover operations. An ownership synchronization process is coordinated for replica cartridges via the reconciliation process at the disaster recovery systems. The disaster recovery systems continue as a replication target for source systems and as a backup target for local backup applications.

Abstract: Disclosed is a method of detecting a product data error in a storage system. First and second vital product data (VPD) EEPROMs are read. Indicators of whether wither or both reads failed are received. Based on these indicators, the contents of the VPD EEPROMs may be compared. Based on a result of the comparing indicating a match, an arbitrary one of the VPD EEPROMS is used. Based on an indicator indicating an error with the first VPD EEPROM, the second VPD EEPROM is used.

Abstract: A data writing method for writing page data into a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages. The data writing method includes grouping the physical pages into a plurality of physical page groups according to write speed of each physical page. The data writing method also includes compressing the page data to generate compressed data and calculating a data compression ratio corresponding to the compressed data. The data writing method further includes writing the compressed data into one of the physical pages in a corresponding physical page group among the physical page groups according to the data compression ratio. Accordingly, the data writing method can effectively ensure the accuracy of data stored in the rewritable non-volatile memory module.

Abstract: A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract: Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data.

Abstract: A flash controller reliably stores data in NAND FLASH by encoding data using an encoding algorithm, and storing that data across multiple pages of the memory. In one embodiment, true data is accepted by the controller, and the controller in turn creates coded data that is the bit-for-bit complement of the true data. The true data and the coded data are then written to the NAND FLASH on a page by page basis. A property of the coding techniques used is that, in at least some cases, detected errors can be corrected.

Abstract: A method and system for redundancy management is provided for a distributed and recoverable digital control system. The method uses unique redundancy management techniques to achieve recovery and restoration of redundant elements to full operation in an asynchronous environment. The system includes a first computing unit comprising a pair of redundant computational lanes for generating redundant control commands. One or more internal monitors detect data errors in the control commands, and provide a recovery trigger to the first computing unit. A second redundant computing unit provides the same features as the first computing unit. A first actuator control unit is configured to provide blending and monitoring of the control commands from the first and second computing units, and to provide a recovery trigger to each of the first and second computing units. A second actuator control unit provides the same features as the first actuator control unit.

Abstract: A method of partitioning a page of an electronic memory includes creating a first sub-page by interleaving a first user data section of the page with another section of a spare area of the page excluding a specified address in a section of the spare area that stores a bad block marker. The method also includes creating the sub-pages by interleaving the user data sections with sections of the spare area excluding the specified address until a last sub-page is to be created. Further, the method includes creating the last sub-page by interleaving a last user data section with the section of the spare area that includes the specified address in an interleaving sequence that retains the bad-block marker at the specified address.

Abstract: This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: A method for object tracking of resource objects with acquire and release semantics can include instrumenting both an acquisition method and a release method of a resource object to write a reference to the resource object to an open object set upon acquiring the resource object, and to remove the reference to the resource object in the open object set upon releasing the resource object. The method also can include determining whether the resource object both has been flagged for garbage collection in the virtual machine and also remains referenced in the open object set. Finally, the method can include generating an error record in the virtual machine responsive to determining the resource object to have been both flagged for garbage collection in the virtual machine and also remaining referenced in the open object set.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer unit, an error correction unit, a data transfer unit, a memory unit, a data input/output unit, a data bus, and a control unit. The control unit controls a first operating mode in which the memory unit is used and a second operating mode in which the memory unit is not used. In the second operating mode, the data transfer unit transfers the data supplied to the input/output unit through the data bus, to the data buffer unit, transfers the data transferred to the data buffer, to the error correction unit and transfers parity data generated in the error correction unit, to the buffer unit.

Abstract: There is provided a data transmission device including a data information storage area including a plurality of areas for storing a first memory address of the first memory device of a data transmission source, a second memory address of the second memory device of a data transmission destination, an error signal indicating whether or not an error is detected in transmission data, and an validity signal indicating whether or not data stored in the second memory device are valid after completing the error correction; and a control unit that outputs a second memory validity address which is a memory address in which data are valid out of data stored in the second memory device, reads data from the second memory validity address of the second memory device, and transmits an address of the first memory device corresponding to the second memory validity address along with the read data.

Abstract: A computing system stores actual memory usage data in a user memory space. The actual memory usage data represents memory usage of a plurality of device drivers that are loaded by a first kernel. The computing system generates an estimate of memory space to be reserved for a second kernel based on the actual memory usage data for the plurality of device drivers that are loaded by the first kernel and reserves memory space for the second kernel using the estimate.

Abstract: Detecting system component failures in a computing system, including: capturing, by a digital imaging device, an image of a component in the computing system; comparing, by a digital imaging comparator, the image of the component in the computing system to a graphical template for the component in the computing system; determining, by the digital imaging comparator, whether the image matches the graphical template for the computing system within a predetermined threshold; and sending, by a notification system, a failure event notification upon determining that the image does not match the graphical template for the computing system within the predetermined threshold.

Abstract: The present invention discloses a method and device for reading a memory card comprising a primary partition and at least one backup partition. The method comprises the following steps that: after writing a first file into the primary partition of the memory card, a read/write device writes the first file into the at least one back partition; and when reading a second file from the memory card, the read/write device reads the second file from the at least one backup partition or from the primary partition if an error occurs in the reading of the second file from the backup partition. The method and device provided herein address the problems existing in the prior art that an embedded system is unstable because of the low error tolerance of a memory card.

Abstract: An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm.

Abstract: A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout.

Abstract: Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host.

Abstract: A method of extraction of a key from a physical unclonable function exploiting the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state.

Abstract: The SSD performs to encode input data from the host device into BCH code having data length Sdr and code length Scr sequentially (step S100 and step S110) and controls RRAM to stores the encoded data (step S120) when the write requesting signal is input from the host device. When the number of BCH code that becomes data of one page of the flash memory after being decoded is stored to RRAM (step S130), the SSD controls RRAM to read out data stored in RRAM (step S140), performs error correction and decoding to the read data as BCH code having the data length Sdr and the code length Scr, and controls the flash memory to store the encoded data.

Abstract: Various embodiments for automated error recovery in a computing storage environment by a processor device are provided. In one embodiment, pursuant to performing one of creating a new and rebuilding an existing logical partition (LPAR) operable in the computing storage environment by a hardware management console (HMC) in communication with the LPAR, at least one failure scenario is evaluated by identifying error code. If a failure is caused by an operation of the HMC and a malfunction of a current network connection, a cleanup operation is performed on at least a portion of a current HMC configuration, an alternative network connection to the current network connection is made, and a retry operation is performed.

Abstract: A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a copy command from the host using the interface, read data from a source memory device in response to the copy command, write the data to a destination memory device in response to the copy command and communicate results to the host using the interface.

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract: According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.

Abstract: A method begins by a processing module identifying a plurality of dispersed storage networks (DSNs) for storing copies of dispersed storage encoded data based on global data retrieval accesses of the copies of the dispersed storage encoded data. The method continues with the processing module determining a set of error coding dispersal storage parameters for at least one of the plurality of DSNs based on local data retrieval accesses allocated to the at least one of the plurality of DSNs. The method continues with the processing module encoding data in accordance with the set of error coding dispersal storage parameters to produce a copy of the copies of the dispersed storage encoded data and outputting the copy of the copies of the dispersed storage encoded data to the at least one of the plurality of DSNs.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller. The memory has a plurality memory blocks each including memory cells capable of holding data. The data in each of the memory blocks is erased simultaneously. The data is written simultaneously in pages in each of the memory blocks. Each of the pages is a set of a plurality of memory cells. The controller transfers write data and a first row address to the memory and issues a change instruction for the transferred first row address and a second row address differing from the first row address. The memory writes the write data into the memory cells corresponding to the first row address when the change instruction has not been issued, and writes the write data into the memory cells corresponding to the second row address when the change instruction has been issued.

Abstract: The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code.

Abstract: A method begins with a processing module sending a plurality of dispersed storage write commands to plurality of dispersed storage (DS) units for storing a plurality of encoded data slices. The method continues with the processing module receiving, within a time period, acknowledgements from at least some of the plurality of DS units to produce received acknowledgements. The method continues with the processing module determining whether a number of received acknowledgements compares favorably to a write threshold. The method continues with the processing module changing at least one of the write threshold and at least one of the plurality of DS units when the number of received acknowledgements does not compare favorably to the write threshold.