Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

Abstract: A graphics processing system includes a plurality of processing units for processing tasks, each processing unit being configured to process a task independently from any other processing unit of the plurality of processing units; a check unit operable to form a signature which is characteristic of an output of a processing unit on processing a task; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is configured to process each task of a first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs, wherein the check unit is configured to form first and second signatures which are characteristic of, respectively, the first and second processed outputs, and wherein the fault detection unit is configured to compare the first and second signatures and raise a fault signal if the first and second signatures do not match.

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.

Abstract: A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network.

Abstract: Methods, apparatuses, and computer program products for managing a storage device using a hybrid controller are provided where the storage device comprises an internal peripheral component interconnect express (PCIe) interface to control solid state memory within the storage device. In particular embodiments, the storage device includes a first external interface configured to establish an external PCIe link and a second external interface configured to establish at least one of an external serial attached small computer system interface (SAS) link and an external serial advanced technology attachment (SATA) link. Embodiments include receiving from an external source, by the hybrid controller, a first command at the first external interface and a second command at the second external interface; and concurrently implementing, by the hybrid controller, the first command using a PCIe protocol and the second command using one of a SAS protocol and a SATA protocol.

Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Abstract: A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.

Abstract: A method and system for providing an improved compliance clock service are described. An example method comprises establishing a system compliance clock (SCC) for a storage system that provides a compliant storage service, and establishing, for a volume in the storage system, a volume compliance clock (VCC). A current value of the SCC may be periodically updated based on hardware ticks monitored at the associated storage node. The volume compliance clock is to update its value based on a current value of the SCC.

Abstract: A method begins by a processing module receiving a write request message from a dispersed storage (DS) processing module, wherein the write request message includes a slice name, a DS processing module most-recent slice revision, a new slice revision, and an encoded directory slice of directory information regarding storage of data. The method continues with the processing module obtaining, from local memory, a DS unit most-recent slice revision based on the slice name. The method continues with the processing module storing the new slice revision as the DS unit most-recent slice revision and storing the encoded directory slice when the DS unit most-recent slice revision compares favorably to the DS processing module most-recent slice revision.

Abstract: A storage system includes first and second expanders for connecting storage units, each of the first and second expanders being connected cascade each other, a first controller connected one of the first and one of the second expanders and a host, a second controller connected the one of the second expanders, the one of the first expanders and the host, the second controller detecting a failure of at least one of the first controller, the first expanders and the second expanders, the second controller selectively controlling a first boot sequence which boots the first controller after the first expanders have been booted and a second boot sequence which boots the first controller before the first expanders have been booted, determining one of the first boot sequence and the second boot sequence on the basis of a place where a failure has occurred in a recovery process.

Abstract: A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.

Abstract: A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.