Abstract: In a network of mobile agents, data integrity can be improved by providing an agent server that can migrate between devices operating in the region of interest (ROI). The agent server distributes agent clients onto devices in the ROI and provides agent server services to the agent clients, including receiving and storing data from the agents. When the agent server device is to leave the ROI, the agent server can migrate to any device executing an agent client and continue to provide the agent server services, including data collection and aggregation, from the device to which the agent server has migrated.

Abstract: In a network of mobile agents, data integrity can be improved by providing an agent server that can migrate between devices operating in the region of interest (ROI). The agent server distributes agent clients onto devices in the ROI and provides agent server services to the agent clients, including receiving and storing data from the agents. When the agent server device is to leave the ROI, the agent server can migrate to any device executing an agent client and continue to provide the agent server services, including data collection and aggregation, from the device to which the agent server has migrated.

Abstract: Systems and methods are provided for arbitrating sensor and actuator signals in various devices. One system includes input/output (I/O) circuitry, redundant computation circuits coupled to the I/O circuitry, and an arbitration circuit coupled between the I/O circuitry and the redundant computation circuits. The I/O circuitry is configured to be coupled to multiple non-redundant systems, and the redundant computation circuits are configured to be coupled to one of multiple system buses. One such device is an aircraft including multiple non-redundant systems and a plurality of system buses that are configured to transmit redundant messages to the non-redundant systems.

Abstract: Scheduling workloads based on detected hardware errors is provided. In response to determining that a hardware error is detected, it is determined whether the hardware error is a cache error. In response to determining that the hardware error is a cache error, it is determined whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a threshold value. In response to determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the threshold value, it is determined whether the cache associated with the cache error is private to a core in the processor. In response to determining that the cache associated with the cache error is private to a core, the execution of the workload is scheduled on a different core of the processor.

Abstract: A computer node includes an integrated management module, a field-programmable gate array, and a plurality of individual hardware devices. The integrated management module receives a user identification and identifies an associated hardware configuration, wherein the hardware configuration identifies hardware devices to be powered off. The integrated management module may instruct the field-programmable gate array to use switches to power off the identified hardware devices without powering off other hardware devices.

Abstract: A first processing element can run within a first operating range. A second processing element can run within a second operating range. A third processing element can be activated if the second processing element fails or can be refrained from being run unless the first or second processing element fails.

Abstract: For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.

Abstract: For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.

Abstract: Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

Abstract: A method includes detecting a channel path error event on an identified channel path; recording channel path error data associated with the detected channel path error event; identifying an scope of the channel path error associated with the identified channel path; determining if the identified channel path is a defective channel path based on the scope of the channel path error; and removing the defective channel path from one or more devices.

Abstract: A channel path error correction system includes a processor with one or more channels and a switch operatively coupled to the one or more channels of the processor. The system also includes an I/O device including one or more ports, the I/O device being operatively coupled to the switch by the one or more ports; a plurality of control units. Each control unit includes at least one of the channels and at least one of the ports and a memory operable for storing information relating to detected channel path errors associated with each of the plurality of control units.

Abstract: An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbors. The rules used by each device to self-determine its behavior are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behavior of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array.

Abstract: A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section.

Abstract: Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card.

Abstract: Via a processor, receiving a power off alert indicating a power off condition of a first processing system on which a first storage provider is installed, the first storage provider managing at least one storage controller. The method further can include, responsive to the power off alert, issuing a first command to a second storage provider installed on a second processing system, the first command indicating to the second storage provider to assume management of the storage controller.

Abstract: Presented are methods and apparatus for protecting a plurality of High Availability (HA) Service Instances (SIs) with a plurality of Service Units (SUs) with an Nway redundancy model. Any of the SUs associated with the Nway redundancy model can simultaneously be assigned an active HA state for some of the SIs and a standby HA state for other SIs. However, only one SU can have the active state for any given SI. The Nway redundancy model is a configured prior to runtime operation.

Abstract: A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.

Abstract: As regards a hardware fault which has occurred in a computer, a hypervisor notifies an LPAR which can continue execution, of a fault occurrence as a hardware fault for which execution can be continued. Upon receiving the notice, the LPAR notifies the hypervisor that it has executed processing to cope with a fault. The hypervisor provides an interface for acquiring a situation of a notice situation. It is made possible to register and acquire a situation of coping with a hardware fault allowing continuation of execution through the interface, and it is made possible to make a decision as to the situation of coping with a fault in the computers as a whole.

Abstract: A method, apparatus, and computer program product for realizing application high availability are provided. The application is installed on both a first node and a second node, the first node being used as an active node, and the second node being used as a passive node. The method includes: monitoring access operations to files by an application during its execution on the active node; replicating the monitored updates to the file by the application from the active node to a storage device accessible to the passive node if the application performs updates to a file during the access operations; sniffing the execution of the application on the active node; and switching the active node to the second node and initiating the application on the second node in response to sniffing a failure in the execution of the application on the active node.

Abstract: A mechanism is provided for saving power in redundant service processors of the data processing system. A redundant service processor places a plurality of components into a low power state in response to receiving a primary control signal from a primary service processor within a first predetermined time period. The redundant service processor monitors for a signal within a second predetermined time period from the primary service processor. The redundant service processor determines whether the signal is a heartbeat signal or an activate signal in response to receiving the signal from the primary service processor within the second predetermined time period. Responsive to receiving the activate signal, the redundant service processor wakes-up the plurality of components that are in the low-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure.

Abstract: An ambient condition monitoring system includes a common control unit, at least one primary communications bus and at least one supplemental communications bus. The control unit communicates with a plurality of supplemental units, which could include ambient condition detectors, using the primary communications bus in a normal operating environment. In the event of a sensed failure of the primary bus, or one of the supplemental units, communications can be automatically implemented using the supplemental communications bus.

Abstract: A transparent high-availability solution utilizing virtualization technology is presented. A cluster environment and management thereof is implemented through an automated installation and setup procedure resulting in a cluster acting as a single system. The cluster is setup in an isolated virtual machine on each of a number of physical nodes of the system. Customer applications are run within separate application virtual machines on one physical node at a time and are run independently and unaware of their configuration as part of a high-availability cluster. Upon detection of a failure, traffic is rerouted through a redundant node and the application virtual machines are migrated from the failing node to another node using live migration techniques.

Abstract: A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.

Abstract: Disclosed is a system comprising: a reconfigurable hardware platform; a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has ceased to perform its function, and then the self-organisation is performed again in order to provide that a second cell

Abstract: A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes allocating two or more processor cores from a plurality of processor cores to form a group of management interrupt handling processor cores. Generated management interrupts are directed to this first group of processor cores and not to remaining processor cores, which forma second group. At least one of the processor cores in the first group handles the management interrupt without disrupting the current operation of the processor cores in the second group.

Abstract: An apparatus, method, and computer readable storage medium are disclosed to recover from lost resources in a distributed server environment. A status monitor module receives, at a first computer, periodic status messages from a peer computer. Each periodic status message indicates that the peer computer is providing a service for which the first computer serves as a backup service provider. A failure detection module determines, based on the periodic status messages, that the peer computer has stopped providing the service. An advancement module provides the service, at the first computer, in response to determining that the peer computer has stopped providing the service.

Abstract: In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.

Abstract: A control apparatus controls a first and a second power supply units having a redundant configuration and converters connected to respective outputs of the power supply units. The power supply units generate a plurality of voltages and supply a storage device with the generated voltages through the respective converters. The control apparatus includes a determination unit for determining whether an abnormality occurs in a first voltage that the first power supply unit generates, upon the second power supply unit failing, and an instruction unit for instructing the converter connected to the first power supply unit to generate the first voltage on the basis of a second voltage that the first power supply unit generates, upon the abnormality occurring in the first voltage of the first power supply unit.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: A network system having duplicate lines of a primary system and a backup system between a transmitter apparatus and a receiver apparatus is provided. Each of the transmitter apparatus and the receiver apparatus includes an arithmetic operator for conducting a BIP-8 arithmetic operation and a CRC arithmetic operation on an input signal and thereby detecting a bit error. The transmitter apparatus transmits data to both lines. The receiver apparatus includes a switcher. When a bit error is detected in received data of the primary system. the switcher switches control of the primary system and the backup system.

Abstract: The fault-tolerant network management system is a hierarchical system having two Manager-of-Managers (MoM) that are implemented at the highest layer in an active-passive mode. A middle layer includes Mid-Level Managers (MLMs), which are used to manage agents disposed throughout different areas of the network at the lowest layer. The MLMs relieve the MoM from dealing with individual agents, and hence enhance the scalability of the whole Network Management Systems. MLMs are configured to work in pairs, where each pair includes two MLMs working in an active-active mode. The MoMs and MLMs have the capability of backing each other up in the case of a failure.

Abstract: A data processing system for performing stuck-at control includes system boards that process data, a crossbar unit having control units to control communication between each system board, and a system controller without causing an availability ratio of a computer system to fall. When a control unit fails, the crossbar unit sends, among IDs uniquely attached to each system board, the ID of each system board under the control of the failed control unit to the system controller. The system controller determines to which of partitions that logically divide a system each system board corresponding to the ID received from the crossbar unit belongs and sends a stop command to stop driving of each system board belonging to the determined partition.

Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.

Abstract: Techniques for transparently replacing a processor, that receives interrupts in a partitioned computing device, with a replacement processor, are disclosed. In at least some embodiments, methods are discussed for directing the interrupts to an unchangeable identifier mapped to the processor's identifier and replacing the processor with the replacement processor. An intermediary, such as an I/O APIC, is used for storing the unchangeable identifier. The mapping may use logical mode delivery, physical mode delivery, or interrupt mapping.

Abstract: A particularly simple and simultaneously fail-safe control system has a control computer for interchanging data with at least one peripheral, and at least one further control computer connected to the first-mentioned control computer via a communication channel. The further control computer is configured to assume at least part of the functionality of the control computer. The control computer is designed, in the event of partial failure thereof, to forward data received by the further control computer via the communication channel to the peripheral and/or to forward data received by the peripheral to the further control computer via the communication channel. There is also provided such a control computer and a method for operating a control system.

Abstract: A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs.

Abstract: An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbours. The rules used by each device to self-determine its behaviour are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behaviour of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array.

Abstract: A process-level troubleshooting architecture (PLTA) configured to facilitate substrate processing in a plasma processing system is provided. The architecture includes a process module controller. The architecture also includes a plurality of sensors, wherein each sensor of the plurality of sensors communicates with the process module controller to collect sensed data about one or more process parameters. The architecture further includes a process-module-level analysis server, wherein the process-module-level analysis server communicates directly with the plurality of sensors and the process module controller. The process-module-level analysis server is configured for receiving data, wherein the data include at least one of the sensed data from the plurality of sensors and process module and chamber data from the process module controller.

Abstract: An I/O device management table that manages the types of I/O devices connected to an I/O switch is provided, and one or plural unallocated I/O devices are defined and registered as standby I/O devices. When a failure occurs in any of I/O devices, the I/O device management table is used to select an I/O device of the same type as the failed I/O device from the standby I/O devices, and the selected I/O device is allocated to a computer to which the failed I/O device is connected. I/O device management can be eased at failure in a computer including an I/O switch device.

Abstract: A method, system, and media for monitoring and healing a computing system. Monitoring agents are deployed to a computing system to be monitored. The monitoring agents collect performance and non-performance counter data of computing devices in the computing system. The data include any recordable information about the monitored computing system. The data is stored in a performance database. A master controller monitors the data for an occurrence of an alert condition that indicates degradation in the health of the computing system. The health of the computing system includes the health of the system, individual components therein, and interactions with other systems. The master controller performs a resolution process to resolve issues causing degradation of the computing system. The collection of data and the monitoring thereof is customizable for an individual computing device, for a cluster of computing devices, or for the computing system as a whole.

Abstract: The invention in particular has as an object a method and a device for reconfiguration of an avionic system comprising at least two computers and a software application, in an aircraft, each of the said computers being adapted for running the software application, the aircraft further comprising a module for detection of failure of at least one of the said computers as well as a loading module making it possible to load the software application into each of the computers. After an information item relating to the state of one of the computers has been received from the detection module, a failure of one of the computers is detected according to the information item received. A configuration according to which at least one application run by the faulty computer is run by another of the computers then is determined.

Abstract: A method for providing multiple media access control (MAC) addresses in a device of a master/slave system may include providing a first MAC address in a MAC address storage of the device. The method may also include providing a second MAC address in a multicast table entry of a multicast hash filter of the device.

Abstract: An image forming apparatus that can be used even when an access error occurs due to replacement of component elements. When replacement of a component element of the image forming apparatus is detected, it is determined whether or not a predetermined process has been normally carried out on the component element. When it is determined that the predetermined process has not been normally carried out, another process different from the predetermined process is carried out. When the other process has been normally carried out, the predetermined process for the component element is changed to the other process.

Abstract: Degree of freedom of a device structure is increased to equalize processor loads by separating the function of executing data read and write processing from the host interface and the disk interface. A disk array device including a disk enclosure and a disk control unit, wherein the disk control unit includes a host interface connected to a host computer which accesses the disk array device, a disk interface connected to the disk enclosure, a plurality of processors that execute data read and write processing between the host computer and the disk enclosure, and a switch which connects the host interface and the disk interface, and the plurality of processors, wherein the switch having a function of selecting a processor which executes the data read and write processing.

Abstract: A method for data protection includes accepting data for storage from one or more data sources (24). The data is sent for storage in a primary storage device (28) and in a secondary storage device (32). While awaiting an indication of successful storage of the data in the secondary storage device, a record associated with the data is temporarily stored in a disaster-proof storage unit (48) adjacent to the primary storage device. When an event damaging at least some of the data in the primary storage device occurs, the data is reconstructed using the record stored in the disaster-proof storage unit and at least part of the data stored in the secondary storage device.

Abstract: A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specific processor core to which control having a higher priority order than control to be allocated to processor cores other than the specific processor core is allocated. When the monitoring processor detects the abnormal operation in the specific processor core, the monitoring processor allocates the control having the higher priority order to one of the processor cores other than the specific processor core.

Abstract: System(s) and method(s) are provided for peer-to-peer exchange of data in a control system. Decentralized storage and multi-access paths provide complete sets of data without dependence on a specific or pre-defined data source or access paths. Data is characterized as data resources with disparate granularity. The control system includes a plurality of layers that act as logic units communicatively coupled through access network(s). Server(s) resides in a service layer, whereas client(s) associated with respective visualization terminal(s) are part of a visualization layer. Peer-to-peer distribution of data resource(s) can be based on available access network(s) resources and optimization of response time(s) in the control system. When client requests a data resource, all the locations of the data resource and the quickest source to retrieve it are automatically determined. The client stores copy of data resource.

Abstract: System and methods of use are discloses that default routing of an ID read by an ID reader as part of a purchase transaction in a retail store, to a first computer system (MCS) instead of the POS computer system for the retail store, the first computer system processes the ID, and the POS computer system receives the results of the processing in the form of a IDs recognizable by the POS computer system and for which the POS computer system has associated costs.

Abstract: A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.

Abstract: A fault-tolerant processor device including a master processor and a plurality of operationally coupled slave processors. The master processor sends a command to each of the slave processors to initiate operation to each control a different one of a plurality of operations during fault-free operation. The master processor monitors each of the operations to confirm the fault-free operation. In a case wherein fault-free operation is not confirmed, the master processor identifies a faulty one of the slave processors, disables the faulty slave processor and initiates operation of a fault-free one of the slave processors to control the operations of the faulty slave processor in addition to the operations of the fault-free slave processor. If the master processor determines that both of the slave processors are faulty, the master processor may disable both of the slave processors and control each of the operations independent of the faulty slave processors.