Abstract: The reliability is improved at a low cost even in a virtualized server environment. The number of spare servers is reduced for improving the reliability and for saving a licensing fee for software on the spare servers. A server system comprises a plurality of physical servers on which a plurality of virtual servers run, a single standby server, a module for detecting an active virtual server, and a module for switching the correspondence of boot disks of virtualization modules for controlling virtual servers to the physical servers. When a physical server fails, the boot disk of the associated virtualization module is connected to a spare server to automatically activate on the spare server those virtual servers which have been active upon occurrence of the failure.

Abstract: A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of data or signals between the functional units. At least one functional unit of the system is programmable and/or configurable such that it performs a particular function out of a number of different functions. The connection matrix is programmed and/or configured such that the functional units are connected with each other in a particular configuration out of a number of different configurations.

Abstract: A system and method to deflect DNS inquires to a new IP address for a website prior to or after the occurrence of a natural disaster that damages the computer infrastructure of an organization, thereby interrupting the organization's ability to continue to offer its website information. An automated process is included that alters a zone file on a controlling DNS server in a manner that provides a minimum of disruption to resolver programs attempting to resolve names of deflected computers via Internet DNS. An intelligent monitor program continually, but periodically, surveys the organization's web server to confirm its operations status and intervenes in the DNS resolution structure for that web server in the event that a sustained disruption occurs.

Abstract: In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error handler program stored in a first memory that is one of a number of memories. If the first processor fails in correctly operating the error handler program, a second processor different from the first processor executes an error handler program stored in a second memory different from the first memory.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: An information processing apparatus includes a domain configured by plural system boards, and a pair of service processors, wherein when one of the pair of service processors fails during the execution of domain dynamic reconfiguration processing for the domain, the other of the pair of service processors takes over and executes the domain dynamic reconfiguration processing under execution.

Abstract: A multi-CPU system including plural CPUs, comprising a failure state detection unit for detecting a failure in an operating program, and a recovery unit for determining, when the failure state detection unit has detected a failure, whether or not recovery of data involved in the failure is possible on the basis of content of the detected failure, and for recovering the data when recovery is determined to be possible.

Abstract: An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

Abstract: A method of booting a multi-processor data processing device includes establishing a link between a first processor and a memory. The link is monitored to determine if, in response to a request from the processor, expected initialization data is communicated between the memory and the first processor. If unexpected data is detected on the link, the link is severed and a new link established between a second processor and the memory to allow the second processor to initiate the boot process. This ensures that, in the event of an error in the boot process at the first processor, the device can complete the boot process, thereby reducing device downtime.

Abstract: A computer device that includes a plurality of processor boards each provided with a processor, a memory, and a chipset, includes a first processor board that makes data in a cache, which have become unfixed as a result of an uncorrectable failure, invalid when the uncorrectable failure occurs on the first processor board in operation, and switches from the first processor board to a second processor board for replacement, and the second processor board that re-executes an instruction that was being executed in the first processor board when the failure occurred.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes transmitting content to a location for presentation across a plurality of display devices that each present a portion of the content. The method includes receiving an indication that a first portion of the content managed by a first computing device is unable to be presented on a first display device. The method also includes transmitting a command to display the first portion on a second display device (where the second display device is configured to present a second portion of the content) if the received indication specifies that the first display device experienced a failure or transmitting a command that the first portion be displayed on the first display device using a second computing device if the received indication specifies that the first computing device experienced a failure.

Abstract: An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational mode back to the operational mode, the spare microprocessor component configured to be switched from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and multiplexing circuitry configured to map the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode.

Abstract: Disclosed are a method and system for parallel execution of recovery in a non-homogeneous multi-processor environment. The method defines criteria how to decide which recovery actions are to be performed, and on which processor. If multiple recovery actions are pending, the goal is to execute them in parallel on multiple processors. This is much more efficient than the traditional approach of one processor doing all the required recovery. In addition, in large, non-homogeneous systems such a single processor capable of doing the complete recovery might not be existing at all due to technical limitations. The method of this invention also defines rules and mechanisms how multiple processors executing recovery in parallel can access shared resources while avoiding deadlock situations. This includes accessing resources that are currently owned by another processor.

Abstract: In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.

Abstract: Replacing a failing physical processor in a computer supporting multiple logical partitions, where the logical partitions include dedicated partitions and shared processor partitions, the dedicated partitions are supported by virtual processors having assigned physical processors, and the shared processor partitions are supported by pools of virtual processors. The pools of virtual processors have assigned physical processors.

Abstract: A method is provided of assigning processors in a multiprocessor environment to a plurality of processes that are executed in the multiprocessor environment. Each process has a process pair defined by a primary process that executes on a first processor, and a backup process that executes on a second processor. There are a plurality of process pairs. The processors are in communication with one another via a communication network. The processors are associated with a plurality of predefined processor pairs. First, a plurality of process pairs are provided that are initially assigned to a respective plurality of pairs of processors, wherein at least one of the processors in the plurality of pairs of processors is initially assigned to more than one processor pair. Each processor is then assigned to only one of the predefined processor pairs so that no processor belongs to more than one processor pair.

Abstract: Redundant application network appliances using a low latency lossless interconnect link are described herein. According to one embodiment, in response to receiving at a first network element a packet of a network transaction from a client over a first network for accessing a server of a datacenter, a layer 2 network process is performed on the packet and a data stream is generated. The data stream is then replicated to a second network element via a layer 2 interconnect link to enable the second network element to perform higher layer processes on the data stream to obtain connection states of the network transaction. In response to a failure of the first network element, the second network element is configured to take over processes of the network transaction from the first network element using the obtained connection states without user interaction of the client. Other methods and apparatuses are also described.

Abstract: A processor having a plurality of hardware resources can perform separate controls within a proper range according to the dependent relations of hardware resources troubled. In case a notification is made of the failure of the hardware resources constituting the processor, a processor control method decides the range of the hardware resources, which cannot be used because of that failure, as a failure range, on the basis of the dependencies of the individual hardware resources predetermined, and stops the use of the hardware resources of the failure range on the basis of that decision result. When the use of the hardware resources indicated by the failure range is stopped, the hardware is not stopped before a predetermined operation is performed not to affect the instruction processing procedure outside of the failure range.

Abstract: Either a complete overhaul for replacing with recommended devices the entire number of devices in a large group of managed devices T, or a partial overhaul for repairing or replacing with recommended devices only those managed devices T that are malfunctioning is selectively performed as an initial overhaul. A complete test involving the entire number of the managed devices T is then periodically performed to determine whether the devices are operating normally or have a malfunction. Any devices found to be malfunctioning during any complete test are repaired or replaced with recommended devices.

Abstract: A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in an array. Preferably, a pipeline failure causes data to be shifted one position within the array of pipelines, to by-pass the failing pipeline, so that each pipeline has only two sources of data, a primary and an alternate. Preferably, selection logic controlling the selection between a primary and alternate source of pipeline data is integrated with other pipeline operand selection logic.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: A method and system are provided for enabling replacement of a failed processor without requiring redundancy of hardware. The system is a multiprocessing computer system that includes one or more processor chips. Each processor chip may include one or more logical processors. During system initialization, one or more logical processors may be reserved in an inactive state. In the event an error is detected on a logical or physical processor, one or more reserved logical processors may have execution context transferred from the processor experiencing the error. Thereafter, the active processor is designated as inactive and replaced by the inactive processor to which the execution context has been transferred.

Abstract: A data processing system (or server) is designed with redundant service processors and a hypervisor. Both service processors are capable of performing the full set of service processor functions, with one service processor (SP) registering itself as a primary SP with the system firmware/hypervisor and the other SP registering as the backup SP. The primary SP performs the initialization, monitoring and control of system resources. The backup SP and hypervisor monitor the primary SP for indications that the primary SP is failing. In the event of a failure of the primary SP, any one of the three components, the backup SP, hypervisor, or even the primary SP itself, is able to initiate a failover to the backup SP.

Abstract: Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.