Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract: Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread.

Abstract: A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

Abstract: Aspects of the subject matter described herein relate to auditing operations. In aspects, operations may be audited synchronously and/or asynchronously to one or more audit targets. When auditing synchronously, audit records may be written synchronously to an audit target. When auditing asynchronously, a buffer may be used to store audit records until the audit records are flushed to an audit target. If an error occurs in auditing, a policy may be evaluated to determine how to respond. One exemplary response includes failing an operation that triggered a subsequent audit record. Furthermore, if a buffer was unable to be copied to an audit target, the contents of the buffer may be preserved and one or more retries may be attempted to copy the buffer to the audit target.

Abstract: Methods, systems, and programming for distributing tasks to a network of machines are disclosed. A plurality of tasks is received, each task having an associated priority level. Each of the plurality of tasks is assigned to a priority line of a plurality of priority lines based on the associated priority level of each of the plurality of tasks. A distribution strategy is determined for the plurality of tasks based on an analysis of at least one worker machine. A group of tasks is scheduled from the plurality of priority lines to a gateway line based on the distribution strategy. Tasks are pushed from the gateway line to the at least one worker machine to process the tasks. The progress of tasks processed by worker machines is monitored and results of tasks are fetched and delivered to users of user devices.

Abstract: Data consistency between a primary virtual machine and a recovery virtual machine may employ a resync engine to detect differences in data blocks stored on both virtual machines. For example, the resync engine may calculate a signature (e.g., hash value) for a primary data block and a corresponding signature for a recovery data block, and compare the signature and the corresponding signature to identify a difference between the primary data block and the recovery data block. In some instances, by identifying a difference between the primary data block and the recovery data block, a data block (e.g., primary data block or recovery data block) may be identified to be transferred from a virtual machine to another virtual machine.

Abstract: Techniques for rescheduling a failed backup job are described in various implementations. A method that implements the techniques may include identifying a failed instance of a backup job, and determining an estimated amount of time to complete a rescheduled execution of the failed instance. The method may also include determining an available window of time in a backup schedule that equals or exceeds the estimated amount of time to complete the rescheduled execution, and rescheduling the failed instance for execution during the available window of time.

Abstract: An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.

Abstract: A method, computer-readable storage medium, and computer system are provided. In an embodiment, a detection is made that at least one thread, in a plurality of threads executing in a computer, has hung. A lock order of a plurality of locks used by the plurality of threads is determined. A determination is made that a first thread in the plurality of threads violates the lock order. After the determination that the first thread violates the lock order, the computer is restarted and the first thread that violates the lock order is scheduled on a reduced-speed processor.

Abstract: A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component.

Abstract: The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).

Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.

Abstract: A computer architecture allows for simplified recovery after mis-speculation during speculative execution by controlling speculation to occur within idempotent regions that may be recovered by re-execution of the region without the need for restoring complex state information from checkpoints. A compiler for increasing the size of idempotent regions is also disclosed.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A reset method performs a software reset in a state in which data in a volatile memory is retained, when an abnormality is generated in a monitoring apparatus. Hardware of the monitoring apparatus may include a function to perform a hardware reset in a state in which the data in the volatile memory is retained, but the software reset is performed with respect to the hardware that does not include such a hardware reset function. The volatile memory may store control information for controlling a host computer monitored by the monitoring apparatus, in addition to data including fault check materials to be retained when the fault is generated. The monitoring apparatus may read the fault information from the hardware to judge whether an abnormal value is reached.

Abstract: A server having a plurality of system boards, comprising: a panic processing unit configured to stop (panic) the server; a system board information storage unit configured to store information to identify a system board having a memory used by a kernel; a system board detaching processing unit configured to detach the system board having the memory used by the kernel before server stoppage; and a reboot processing unit configured to reboot the server using system boards other than the separated system board among the plurality of system boards, after detaching the system board having the memory used by the kernel.

Abstract: In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

Abstract: A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.

Abstract: In a distributed computing system, a processing device executing a caveat enabled transaction manager registers one or more transaction participants with the transaction manager. To register a transaction participant, the caveat enabled transaction manager records an address of the transaction participant. The caveat enabled transaction manager additionally determines whether the transaction participant is associated with any transaction caveats. If the transaction participant is associated with a transaction caveat, the caveat enabled transaction manager records the transaction caveat.

Abstract: An application programming interface (API) that leverages operating system instrumentation to provide a chain of threads and processes may alleviate some debugging complications. Specifically, the chain may start with the first thread in the process that experienced the original failure and end with the last thread upon which the first thread directly or indirectly depends. The API may aid debugging efforts by classifying all threads related or dependent upon an original failed thread into specific categories of failures, requesting further information from the originating OS concerning specific failed threads, and using that information to debug the failed application or process more thoroughly.

Abstract: Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more embodiments, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more embodiments, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing.

Abstract: A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.

Abstract: A method to enable an adaptive fault tolerance in a data system is provided. The method includes communicatively coupling a radiation hardened hardware element to at least one interrupt service routine application in a respective at least one processing element, triggering an interrupt service routine by an interrupt signal received from the radiation hardened hardware element at the interrupt service routine application after an execution of a code block by the at least one processing element, and inspecting the internal state of the at least one processing element to determine if an error occurred.

Abstract: A method for recovering a basic input output system (BIOS) and a computer device thereof are disclosed. The computer device includes a motherboard, a power button, a BIOS storage unit, and an embedded controller. The BIOS storage unit is disposed on the motherboard, and it stores a first boot block code and a second boot block code. When the computer device is connected with a power supply to supply standby power to the motherboard, and the power button is not pressed, the embedded controller detects whether the first boot block code is damaged. If the first boot block code is damaged, the embedded controller recovers the first boot block code via the second boot block code.

Abstract: Embodiments of the present invention provide techniques, including systems, methods, and computer readable medium, for dynamic atomic arrays. A dynamic atomic array is a data structure that provides an array that can grow or shrink in size as required. The dynamic atomic array is non-blocking, wait-free, and thread-safe. The dynamic atomic array may be used to provide arrays of any primitive data type as well as complex types, such as objects.

Abstract: A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

Abstract: A system is designed for processing instructions in real time during a session. This system comprises: a preloader for obtaining reference data relating to the instructions, the reference data indicating the current values of each specified resource account data file, and the preloader being arranged to read the reference data for a plurality of received instructions in parallel from a master database; an enriched instruction queue for queuing the instructions together with their respective preloaded reference data; an execution engine for determining sequentially whether each received instruction can be executed under the present values of the relevant resource account files and for each executable instruction to generate an updating command; and an updater, responsive to the updating command from the execution engine (for updating the master database with the results of each executable instruction, the operation of the plurality of updaters being decoupled from the operation of the execution engine.

Abstract: A method for tuning memory parameter values and a computer system using the same are disclosed. In the invention, the computer system provides an embedded controller which may accumulate a counting value and send a reset signal to reboot the computer system. Firstly, the embedded controller reloads a memory parameter value corresponding to the counting value. Then, the computer system executes a memory test procedure. When the memory test procedure successes, a BIOS stores the memory parameter value. On the contrary, when the memory test procedure fails, the embedded controller accumulates the counting value and sends the reset signal to reboot the computer system. The BIOS reloading another memory parameter value corresponding to the accumulated counting value and re-executes the memory test procedure.

Abstract: A computer system with a damaged BIOS data recovering function is disclosed. When BIOS data in the computer are damaged, the computer system may update and recover the BIOS of the storage unit of the computer system in a standby mode via an external electronic device (another computer or a USB flash disk). The computer system includes a storage unit, a data transferring interface, a power supply unit, and a control unit. The computer system is electrically connected with the external electronic device via the data transferring interface. The power supply unit provides standby power (in the standby mode) when the computer system is shut down. The control unit is electrically connected with the power supply unit and the data transferring interface, respectively. The control unit is actuated via the standby power, receives the external BIOS stored in the external electronic device.

Abstract: A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs.

Abstract: A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

Abstract: A processor predicts predicted slack which is a predicted value of local slack of an instruction to be executed and executes the instruction using the predicted slack. A slack table is referred to upon execution of an instruction to obtain predicted slack of the instruction and execution latency is increased by an amount equivalent to the obtained predicted slack. Then, it is estimated, based on behavior exhibited upon execution of the instruction, whether or not the predicted slack has reached target slack which is an appropriate value of current local slack of the instruction. The predicted slack is gradually increased each time the instruction is executed, until it is estimated that the predicted slack has reached the target slack.

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: According to one embodiment, a memory interface module is configured to read one of instructions stored in a memory in accordance with a memory address designated by a fetch request issued from a processor. An error detection module is configured to detect an error in the read instruction. An instruction transmission module is configured to send to the processor, upon detection of an error in the read instruction, a first instruction to hold on a stack the same memory address as the one designated by the fetch request and a second instruction to jump to an error correction routine for correcting an error of the read instruction.

Abstract: A data processor system is described comprising a first and a second data processor unit (PU1, PU2). The first data processor unit (PU1) has a data source (SW1, IP11, IP 12) for providing data units for transmission to the second data processor unit (PU2) and a retry buffer (RBUF) for temporarily storing transmitted data units. It is provided with a data selector (RSEL) for selecting data units from the data source or from the retry buffer, and a controller (RCTRL) for controlling the data selector, as well as an output (T1x) for providing data selected for transmissions. The second data processor unit (PU2) has an input (R1x) for receiving the transmitted data and an output (PU20) for further transmitting the received data to a third data processor unit. It also has an input buffer (IBUF) coupled to the input, for temporarily storing the received data.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.