Abstract: Modern Standby is enabled for unsupported applications. An enabler driver can be included on a system that supports Modern Standby and can be configured to detect when applications are loaded on the system. When an unsupported application is loaded, the enabler driver can interface with an enabler service to determine whether the unsupported application is Modern Standby capable. If so, the enabler driver can add the unsupported application to a throttle job object that the operating system uses to determine which applications should remain active during Modern Standby. In instances where an application is deployed in a container, an enabler container service can be leveraged to determine whether the containerized application is Modern Standby capable. If so, the enabler driver can add the container to the throttle job object.

Abstract: A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

Abstract: A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation circuit which generates a syndrome bit for correcting an error in read data which are read from the first area, has the first number of data bits and corresponds to the parity bit read from the second area, based on the parity bit and the read data, and a parity correction circuit which corrects the parity bit generated by the parity generation circuit. The parity generation circuit generates the parity bit for data which includes input data and a part of the read data.

Abstract: A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit.