Abstract: A volatile/non-volatile memory device access provisioning system includes a processing system and a controller coupled to a memory device. The controller provides an access key to the memory device and causes memory device communications to be passed to the processing system when the access key is available. The controller simply causes memory device communications to be passed to the processing system when the access key is not available. The memory device masks non-volatile memory subsystem access information in the memory device to prevent the processing system from accessing non-volatile memory subsystem(s) in the memory device, and then determines whether the access key has been received from the controller. The memory device will unmask the non-volatile memory subsystem access information such that the processing system can access non-volatile memory subsystem(s) in response to determining that the access key has been received from the controller.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: Systems and methods for state based test case generation for software validation are disclosed. One embodiment includes determining a first input and a first input type for a program block of vehicle software for creating a test case, wherein the first input type includes a state based input, determining permutations of values for the first input, based on the first input type, and running the test case with the state based input, wherein running the test case comprises applying the permutations of values for the first input to the program block. Some embodiments include determining, by a test computing device, whether the test case meets a predetermined level of modified condition/decision coverage (MC/DC) and providing an indication of whether the test case meets the predetermined level of MC/DC.

Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.

Abstract: System and method for testing a radio frequency (RF) device under test (DUT) communicating using multiple radio access technologies (RATs). Single data signal sequences having characteristics of multiple RATs as prescribed by signal standards are exchanged between a tester and DUT. The tester and DUT process received signal sequences substantially in parallel with their reception. A pattern of contemporaneous signal sequence reception and processing continues for as many RATs as the DUT is capable of supporting.

Abstract: The present disclosure describes computer implemented methods, computer systems, and computer readable mediums for recursively testing an OData service. One method may include extracting resource identifiers from an initial service document, and for each of the resource identifiers, retrieving a respective response document from the OData service. The method may further include applying a test function to each of the resource identifiers and respective response documents and recording a result of the test function for each of the resource identifiers. The method may further include recursively extracting new resource identifiers from the response documents and retrieving respective new response documents for each new resource identifier from the OData service until no additional resource identifiers are extracted from the new response documents.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.

Abstract: Based on a seed value held by a managing apparatus for a plurality of information processing apparatuses, the same number of seed values as the total number of times of tests conducted by one or more processing units included in an information processing apparatus are generated so as not to overlap with another information processing apparatus. Then, a processing unit of the one or more processing units generates the same number of test instruction sequences as the number of times of tests performed by the processing unit based on the same number of seed values as the number of times of tests performed by the processing unit among the generated seed values, and executes the generated test instruction sequences.

Abstract: An integrated circuit includes a set of cells for operation in a functional mode and in a scan testing mode, and a spare cell. The cells are connected in a scan chain with scan data inputs connected to the outputs of preceding cells in the scan chain and respond to assertion of a scan enable signal. A clock gating element applies a functional clock signal to clock inputs of the cells in response to a gating enable signal in functional mode and a test clock signal in response to a test mode signal in scan testing mode. A functional data input of the spare cell latches the gating enable signal during the scan testing mode in response to de-assertion of the scan enable signal. The output of the spare cell is connected to the scan data input of one of the cells in response to the scan enable signal.

Abstract: A computing system resource recovery method can include identifying a resource manager associated with a computing transaction, classifying the computing transaction to determine a predetermined metric, measuring an actual metric of the computing transaction, comparing the predetermined metric to the actual metric to detect abnormal behavior in the transaction and modeling the abnormal behavior to determine how the resource manager is affected by the abnormal behavior.

Abstract: A control server is electronically connected with a number of test servers via a number network interfaces. The control server records a network interface number and an IP address of a baseboard management controller (BMC) of each test server, sets an IP address of a network card of the control server, and generates a test command. The test command comprises information in relation to a number of times for powering on a test server, a number of times for powering off the test server, and a time interval between a power-on operation and a power-off operation. The test command is sent to each test server by the control server according to the network interface number and the IP address of the test server. After receiving the test command, the BMC of the test server performs power-on/power-off operations of the test server according to the test command.

Abstract: An exemplary system and method for testing the configuration of a computer system includes detecting a function which is executed by the computer system; and testing whether the detected function contravenes a configuration rule of the computer system.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.

Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.

Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Abstract: According to various illustrative embodiments, a method and system for toggling a scan enable signal are described. In one aspect, the method comprises setting a scanin seed and resetting a monitor, generating random shift patterns, and resetting the monitor a second time. The method also comprises generating the random shift patterns a second time and strobing an activity flag. The method also comprises resetting the monitor a third time and enabling the scan enable signal toggling mechanism, and generating random shift/capture patterns repeatedly at least a predetermined number of times.

Abstract: A method, apparatus and computer program product are provided for implementing self-optimizing initial program load (IPL) diagnostics. A control flag is set to identify a self-optimizing IPL diagnostics mode. The self-optimizing IPL diagnostics mode includes collecting a list of new parts and collecting a list of identified failed parts. Hardware is identified and initialized for running diagnostics on the collected list of flagged parts. Diagnostics are run only on the initialized flagged hardware.

Abstract: A data displacement bypass system is disclosed, wherein the data displacement bypass system comprises a CPU (Central Processing Unit), a first memory, a plurality of address lines, a plurality of data lines, an OE (Output Enable) line, a CS (Chip Select) line and a data displacement unit. The CPU could output a plurality of address characters, an OE signal and a CS signal, and receive a plurality of data characters. The first memory and the data displacement unit could output the plurality of data characters according to the plurality of address characters, the OE signal and the CS signal received by the first memory and the data displacement unit, wherein the data displacement unit could govern the plurality of data characters inputting to the CPU by outputting high or low voltage.

Abstract: A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group comprises single or plural core circuits. The test control flag register enables a set of test signals to input in one of the test groups, testing the core circuits in the test group.

Abstract: A hardware health evaluation module is associated with a hardware module or device and employs a linked list of error records to continually evaluate the state of the hardware module to determine whether or not it is currently operating with or without errors. In the event that the health evaluation module determines that the hardware module is not operating in an error free manner, it detects and stores, for a specified period of time, an indication of the error and associates this detected error or errors with one or more of the error records. The error records are designed to provide assistance in diagnosing the cause of a hardware error.

Abstract: This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

Abstract: An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In response, the DUT produces a response waveform. The response waveform is compressed before transferring it to a storage device or over a data transfer interface. If the response waveform is analog, it is converted to digital before compression. The compressed waveform is decompressed for further analysis or display by a host computer. Features of the response waveform can be calculated from the compressed or uncompressed waveform data. Several configurations that include compression and decompression of stimulus and/or response waveforms in test systems are described.

Abstract: A network device, such as a router or switch, has a CPU and a memory operable to receive, store and output computer code. The code includes device configuration files, traffic pattern files, and standard-behavior-output template files adapted for detecting network device functional defects and bottlenecks. The device is operable in a testing mode to act as either a Device Testing Doctor (DTD) or a Device Under Test (DUT), in which it loads into or accepts from a related, interconnected and similarly configured and operable network device selected ones of the device configurations, transmits to or receives from the other device selected ones of the input traffic patterns, compares its own output or that of the other device in response to the input traffic pattern with selected ones of the standard-behavior-output templates, and detects a network device defect or bottleneck in itself or in the other device based on the comparison.

Abstract: A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the computing system's memory containing the binary code that was executing at the time of the exception. The exception-causing code from the system memory may be compared to an original version of the code from a non-volatile source. If the comparison identifies a hardware corruption pattern, the computing system may communicate information about the process and the exception to an error analysis server. Using historical exception data, the error analysis server may determine if the identified corruption pattern is most likely the result of corrupt hardware at the computing system. If corrupt hardware was the most likely result of the exception, then the server may communicate with the computing system to recommend or initiate a hardware diagnostic routine at the computing system to identify the faulty hardware.

Abstract: A computer-implemented method is provided for determining a corrective action. The method may include obtaining diagnostic data and calculating, using the diagnostic data, a prognostic. The method may also include retrieving, when the prognostic is above an alarm level, historical records and calculating a Bayesian posterior probability using the diagnostic data and the historical records. Further, the method may include calculating a prognostic prescience metric using the diagnostic data and the historical records and determining, based on the Bayesian posterior probability and the prognostic prescience metric, the corrective action.

Abstract: A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a test operation to be performed by the first test algorithm on the memory. The BIST system also includes an execution module that applies the first test algorithm to the memory.

Abstract: A computerized method, program product, and an autonomic data processing system that oversees real-time log data acquired by a logging application of an executing computer program. In response to an event occurring, the logging application communicates the occurrence of the event to an event correlation engine, and invokes a window-resizing module. If the event is part of a symptom of processing problems developing, then the window-resizing module immediately expands the amount of real-time log data that is retained in temporary memory to include not log data including the event but also log data during the time duration of the symptom. In conjunction with a information level module, the granularity or level of information of the log data that is archived increases immediately upon the event so that not only is more time of the log-data but also a higher information level of the log data is saved for symptom analysis and verification.

Abstract: A method and apparatus is provided for detecting random access memory (RAM) failure for data with a plurality of addresses. The method comprises generating a plurality of RAM test patterns in a predetermined order, implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, rotating the RAM test patterns sequentially to prepare for a new testing pass, and implementing the RAM test patterns on different data addresses in the new testing pass. The apparatus comprises means for generating a plurality of RAM test patterns in a predetermined order, means for implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, means for rotating the RAM test patterns sequentially to prepare for a new testing pass, and means for implementing the RAM test patterns on different data addresses in the new testing pass.

Abstract: An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In response, the DUT produces a response waveform. The response waveform is compressed before transferring it to a storage device or over a data transfer interface. If the response waveform is analog, it is converted to digital before compression. The compressed waveform is decompressed for further analysis or display by a host computer. Features of the response waveform can be calculated from the compressed or uncompressed waveform data. Several configurations that include compression and decompression of stimulus and/or response waveforms in test systems are described.

Abstract: Our invention presents an effective method and system which are used to perform side-channel testing of computing devices, as well as to improve resistance of computing devices against side-channel attacks.

Abstract: The analyzer according to the present invention is an analyzer having a scan test function, and including scan paths each having flip-flops which function as a shift register when a scan test is performed, and a switching unit operable to switch between a first connection state, and a second connection state where the scan paths are connected in series to each other and further an output from the last stage of the scan path is connected to the input of the first stage of the scan path.

Abstract: An image forming apparatus including: a registration section which registers information on a diagnostic mode, where an operation mode to diagnose inside the image forming apparatus based on error information is assumed to be the diagnostic mode; an error detecting section which detects an error in the apparatus and outputs error information; and a control section which, when the error detecting section outputs error information, receives the information on the diagnostic mode corresponding to the error information from the registration section, and executes problem solution and recovery of the apparatus.

Abstract: A system and method for configuration of general purpose test equipment is provided. According to various examples of the invention, performance specification documents in electronic form are input using mark-up language and a mark-up language reader converts the performance specification document into, selectively, a human readable document and a delimited configuration file for input into configurable test equipment having a common object request broker architecture.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of