Test Trigger Logic (epo) Patents (Class 714/E11.153)
  • Patent number: 8730747
    Abstract: The semiconductor device including a memory circuit is configured to include a mode switching circuit additionally provided with a data comparison circuit which detects that a serial signal supplied to an input terminal for communication and a serial signal supplied to an input terminal used for a purpose other than communication are reversed from each other, a decoder circuit which detects that a serial signal carries predetermined data and which outputs a detection signal, a control signal generating circuit which generates a control signal, and a circuit which outputs a signal for switching to a test mode on the basis of the signals.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 20, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Nakamura
  • Publication number: 20100281301
    Abstract: A method for testing a circuit for a transponder, and transponder circuit, is provided, in which the circuit is operated in a passive mode in that the circuit is supplied with energy from a field, in which, during the passive mode, the circuit receives a command via the field to activate a test routine, in which memory content is stored by the test routine as test data in a memory area of a memory of the circuit predetermined by the test routine, in which, during the passive mode, the test data are transmitted via the field.
    Type: Application
    Filed: April 23, 2010
    Publication date: November 4, 2010
    Inventors: Paul Lepek, Detlef Dieball