Testing Of Logic Operation, E.g., By Logic Analyzers, Etc. (epo) Patents (Class 714/E11.155)
  • Publication number: 20140143621
    Abstract: An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Vijay Sharma
  • Publication number: 20140136912
    Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: Oracle International Corporation
    Inventors: Robert P. Masleid, Ali Vahidsafa
  • Publication number: 20140129887
    Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Hwong-Kwo Lin, Ge Yang, Xi Zhang, Jiani Yu, Ting-Hsiang Chu
  • Publication number: 20140129888
    Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: International Business Machines Corporation
    Inventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette, Nancy H. Pratt, Michael A. Ziegerhofer
  • Publication number: 20140122949
    Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ilyas Elkin, Ge Yang
  • Publication number: 20140122951
    Abstract: A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: DUKE UNIVERSITY
    Inventors: Krishnendu Chakrabarty, Brandon Noia
  • Publication number: 20140108876
    Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Akshay K. Pathak, Rakesh Pandey
  • Publication number: 20140108877
    Abstract: The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Inventors: Glen Earl Hush, Jeffrey P. Wright
  • Publication number: 20140101505
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises a clock tree having clock signal lines, and clock control elements arranged in respective selected ones of the clock signal lines of the clock tree, where the clock control elements are configured to separate at least one synchronous clock domain into multiple asynchronous clock domains during scan testing. The clock control elements may be configured to reduce a number of timing exceptions produced during scan testing relative to a number of timing exceptions that would otherwise be produced if scan testing were performed using the synchronous clock domain.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Vijay Sharma
  • Publication number: 20140101500
    Abstract: Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes scan chains with scan cells interspersed throughout the core circuitry. The scan control circuitry controls the scan test circuitry to scan test the core circuitry. The debug control circuitry utilizes the scan test circuitry and controls the scan control circuitry to debug failure conditions of the integrated circuit during normal use. The scan control circuitry applies a debug clock signal to a clock port of each scan cell of a given scan chain to store data values that are generated by the core circuitry into the scan cells. The scan control circuitry controls the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Sachin Shivanand Bastimane, Komal N. Shah, Ramesh C. Tekumall, Allentown Madhani
  • Publication number: 20140095951
    Abstract: A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: Texas Instruments, Incorporated
    Inventors: Nisar Ahmed, Corey Jason Goodrich, Xiao Liu, Chris Therrien
  • Publication number: 20140089752
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Publication number: 20140089748
    Abstract: Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Inventors: Sylvain Garnier, Anthony Rouaux, Sebastien Jouin, Frode Milch Pedersen
  • Publication number: 20140068325
    Abstract: A computer-implemented method for test case result processing includes receiving, by a test case result processing logic in a processor of a computer, a test result from a test case that executes on the computer; determining, by the test case result processing logic based on a result description file, whether a result description corresponding to the received result exists in the result description file; based on the result description corresponding to the received result existing in the result description file, determining an action description associated with the result description based on an action definition file; and executing an action corresponding to the determined action description.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel L. Masser, David C. Reed, Max D. Smith
  • Publication number: 20140053034
    Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael W. Harper, Mack W. Riley
  • Publication number: 20140053036
    Abstract: A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (DSM). The DSM includes multiple programmable storage elements for storing parameter values corresponding to multiple contexts. Each context is associated with a given one of multiple instruction sequences, such as at least threads and power-performance states. The DSM detects a sequence identifier (ID) and selects a context based on the sequence ID. The corresponding parameter values are used by transition conditions (triggers) and taken debug actions in a finite state machine (FSM) within the DSM. Each state and transition in the FSM is used by each one of the multiple contexts. The programmable DSM shares many resources, rather than replicating them, while being used for multiple sequences.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Inventors: Scott P. Nixon, Eric M. Rentschler
  • Publication number: 20140040688
    Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
    Type: Application
    Filed: November 21, 2012
    Publication date: February 6, 2014
    Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang
  • Publication number: 20140032985
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry. The portion of the additional circuitry that provides the potentially non-deterministic value may comprise, for example, at least one of a mixed signal logic block and a memory block of the additional circuitry. The given scan cell may be controlled by configuring the scan cell such that it is unable to capture data in a scan capture mode of operation in which it would otherwise normally be able to capture data.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy
  • Publication number: 20140032986
    Abstract: A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.
    Type: Application
    Filed: November 19, 2012
    Publication date: January 30, 2014
    Inventors: Guoping WAN, Shayan ZHANG, Wanggen ZHANG
  • Publication number: 20140019818
    Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: FREESCALE SEMICONDUCTOR
    Inventors: Amit Jindal, Nitin Singh
  • Publication number: 20140013171
    Abstract: Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Cheow Guan Lim, Giovanni Ferrara
  • Publication number: 20140013173
    Abstract: A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: Ravi K. Ramaswami, Samy R. Makar, Anh T. Hoang
  • Publication number: 20140006889
    Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the one or more save and restoring LFSR registers upon reaching a predetermined number of test loops; performing a signature stability test by loading said initial seed to said LFSR, executing the predetermined number of BIST test loops, and comparing the resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Raymond J. Kurtulik, John D. Parker
  • Publication number: 20130346814
    Abstract: A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Inventors: Timothy Zadigian, Jonathan Stroud, Michael Moriarty
  • Publication number: 20130346815
    Abstract: Techniques related to remotely boundary scanning of an integrated circuit embedded in a target computing system are disclosed herein. In an example, a host computing system includes a first peripheral port and a second peripheral port. A port-to-port boundary scan assembly is to interface boundary scan data between the first and the second peripheral ports. Thereby the boundary scan data can be routed from the second peripheral bus to the target computing system via a network port at the host computing system.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Inventors: Kamran H. CASIM, Russ W. Herell, Martin Goldstein
  • Publication number: 20130346816
    Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventors: Sankaran M. Menon, Robert R. Roeder, Liwei E. Ju
  • Publication number: 20130339812
    Abstract: An operating system independent JTAG debugging system implemented to run in a web browser. The software executing in the browser identifies the JTAG enabled components in the target system that is to be tested, and automatically downloads the latest versions of the appropriate software, JTAG drivers and configuration information from a test server.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stephen Yee Shun Lau, Vikas Varshney
  • Patent number: 8612809
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: December 17, 2013
    Assignee: Intel Corporation
    Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
  • Publication number: 20130318410
    Abstract: A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Hongshin Jun, William Eklow, Sun-Gyu Kim
  • Publication number: 20130311843
    Abstract: An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input interface in conjunction with testing of the additional circuitry utilizing said at least one scan chain. For example, the scan controller may control signal values applied to respective address input and write enable signal lines in a manner that ensures that data written to a memory in a write operation of a given memory cycle can be read from the memory in a read operation of a subsequent memory cycle.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Priyesh Kumar
  • Publication number: 20130305106
    Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Rajesh Mittal, Puneet Sabbarwal, Prakash Narayanan, Rubin Ajit Parekhji
  • Publication number: 20130290799
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may include, for example, at least a launch-on-shift mode and a launch-on-capture mode. These transition launch modes provide different manners of launching a given signal transition via at least one of the scan cells in a corresponding one of the clock domains. The transition launch mode selection circuitry may be configured to generate from a common shift enable signal multiple independently controllable shift enable signals for respective ones of the clock domains of the integrated circuit.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: LSI Corporation
    Inventor: Ramesh C. Tekumalla
  • Publication number: 20130275824
    Abstract: An integrated circuit comprises a memory or other type of circuit core having an input interface and an output interface, built-in self-test circuitry configured for testing of the circuit core between its input and output interfaces in a built-in self-test mode of operation, and at least one scan chain having a plurality of scan cells. The scan cells of the scan chain are coupled to respective signal lines at the input and output interfaces and configured to allow capture of functional signal values from those signal lines in a functional mode of operation and shifting out of the captured functional signal values in a scan shift mode of operation. This allows detection of faults associated with functional paths of the interface that would otherwise not be detectable using the built-in self-test circuitry.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Avinash Mendhalkar, Parag Madhani
  • Publication number: 20130262943
    Abstract: According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: RAVI LAKSHMIPATHY, BALAJI UPPUTURI
  • Publication number: 20130262945
    Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Eugene Saghi, Jeffrey K. Whitt, Joshua P. Sinykin
  • Publication number: 20130262946
    Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Paul J. Smith, Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin
  • Publication number: 20130219238
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy
  • Publication number: 20130212445
    Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
  • Publication number: 20130198578
    Abstract: At least one external pin of an integrated circuit (IC) is coupled to receive a first configuration signal used in configuring an internal circuit block for a test designed to uncover faults in the circuit block, and to receive a first test signal during the test. Configuration logic in the IC is designed to generate control data by decoding configuration signals that include the first configuration signal. A test configuration register stores the control data and applies the control data during the test, but is decoupled from the configuration logic prior to commencement of the test. A sequence detector in the IC is designed to detect a reset sequence signifying an end of the test and in response to re-couple the test configuration register to the configuration logic. The number of external pins needed for testing the IC is reduced.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramesh Kumar Chandel, Prasanth ViswanathanPillai
  • Publication number: 20130185607
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: lSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Niranjan Anant Pol, Vineet Sreekumar
  • Publication number: 20130185608
    Abstract: Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access block including a base chain select multiplexor and a base bypass multiplexor. The secondary component has a secondary scan chain and a secondary chain access block including a secondary chain select multiplexor and a secondary bypass multiplexor. The secondary chain select multiplexor is configured to receive input directly from the base component and another component. The base and secondary chain access blocks are configured to selectively access the base scan chain and/or the secondary scan chain.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 18, 2013
    Applicant: QUALCOMM Incorporated
    Inventor: Sudipta Bhawmik
  • Publication number: 20130179742
    Abstract: A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: LSI Corporation
    Inventor: Ramesh C. Tekumalla
  • Publication number: 20130179741
    Abstract: Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: LSI CORPORATION
    Inventor: Joshua P. Sinykin
  • Publication number: 20130179745
    Abstract: A test interface circuit couplable between a source driver and test equipment is disclosed. The test interface circuit includes a plurality of test interface modules and a logic circuit. Each of the test interface modules receives an output signal from one of a plurality of output pins of the source driver, judges whether the received output signal falls in a specified range or not, and generates a deviation signal accordingly. The logic circuit generates a deviation test output signal according to the deviation signals generated by the test interface modules.
    Type: Application
    Filed: July 3, 2012
    Publication date: July 11, 2013
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventor: Chiu-Huang Huang
  • Publication number: 20130173971
    Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventor: David J. Zimmerman
  • Publication number: 20130173977
    Abstract: A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 4, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Girishankar Gurumurthy, Mehesh Ramdas Vasishta
  • Publication number: 20130173976
    Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 4, 2013
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy
  • Publication number: 20130166974
    Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.
    Type: Application
    Filed: August 29, 2012
    Publication date: June 27, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Angel SOCARRAS
  • Publication number: 20130166979
    Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.
    Type: Application
    Filed: July 11, 2012
    Publication date: June 27, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Angel SOCARRAS
  • Publication number: 20130166975
    Abstract: An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks.
    Type: Application
    Filed: June 1, 2012
    Publication date: June 27, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jun-Young SON, Yun-Koo LEE, Sang-Woon YANG, Bong-Soo LEE