Abstract: A virtual hard disk drive includes at least one test transmission interface and a processing unit, wherein the test transmission interface is used for electrically connecting with the processing unit. The test transmission interface can electrically connect with a transmission interface under test of a computer. The processing unit includes an obtaining module and a simulation module. When an access instruction is received through the test transmission interface from the transmission interface under test of the computer, the obtaining module obtains a number of accessed blocks from the access instruction. The simulation module simulates a step of accessing a set of accessed data with the number of accessed blocks with respect to the transmission interface under test via the test transmission interface.

Abstract: The invention concerns a procedure and a device for emulating a programmable unit using an external emulation device. The method comprises transferring a signal to the external emulation device, which allows deriving the original CPU clock signal of the target programmable unit, and, in a defined relationship with the CPU clock signal (8), emulation data, which are formed by those data, which cannot be calculated on the basis of a given model of the target programmable unit and on the basis of the program code. The target programmable unit is emulated by the external emulation device (1) using the transferred emulation data, and respective trace data are ascertained from the emulation. The invention further concerns an apparatus for emulation, comprising a target programmable unit, which has at least one CPU, and comprising an emulation device, which, as an external unit (14), is connected via an emulation port as a communication link with the target programmable unit.

Abstract: A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells.

Abstract: A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module.

Abstract: A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module socket, but from the reverse (solder) side of the motherboard. The adapter pins connect to the test adapter board either directly, through a connector plug, or through an intervening adapter board. The test adapter board has soldered onto it additional memory chips and buffer chips on a memory module, such as an Advanced Memory Buffer (AMB) for a fully-buffered memory module. The built-in-self-test (BIST) feature of the AMB may be used to test the memory chip under test in the chip test socket, or the processor on the motherboard may write and read the memory chip.