Functional Testing (epo) Patents (Class 714/E11.159)
  • Patent number: 11379134
    Abstract: A control apparatus for a vehicle includes a memory and a controller. The memory has a first storage area, which is a write restricted area storing one or more first control patterns out of a plurality of control patterns for the vehicle, and a second storage area, which is a write enabled area storing one or more second control patterns out of the plurality of control patterns for the vehicle. The controller determines whether a control condition for each of the plurality of control patterns is satisfied based on a state of the vehicle, to select one or more control patterns for each of which the control condition is satisfied, and to control the vehicle according to the selected one or more control patterns.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: July 5, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiko Nakano, Yu Nagata, Takashi Hayashi, Ryota Kondo
  • Patent number: 10509713
    Abstract: A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pipelines forming a cache arrangement, and a memory, comprises obtaining an instruction trace of the cache arrangement and a data trace for data being loaded from the memory into the cache. The instruction trace is synchronized with the data trace to generate a synchronized data trace and/or a synchronized instruction trace. A state of a memory model, representing a memory readable by the one or more processor cores via a respective instruction is updated using the synchronized data trace and the synchronized instruction trace.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 17, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Peter Svensson, Bengt Wikenfalk
  • Patent number: 9898563
    Abstract: Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: February 20, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Krishnamurthy Suresh, Mukesh Gupta, Sanjay Gupta, Charles W. Selvidge
  • Patent number: 8966348
    Abstract: A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar
  • Publication number: 20140115394
    Abstract: The technology disclosed relates to implementing a novel architecture of a finite state machine (abbreviated FSM) that can be used for testing. In particular, it can be used for testing communications devices and communication protocol behaviors.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Spirent Communications
    Inventor: Hossam Fattah
  • Publication number: 20140068338
    Abstract: A diagnostic system provides identification of symptoms in a distributed network and an engine for providing recommended rectification of error sources that correspond to the symptoms. The distributed network may be accessed for current statistics. Symptoms may be identified that correspond to the current statistics. A recommended course of action for the distributed network may be provided based on a predetermined list of courses of actions that correspond to rectifying the performance in the error sources.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: KESHAV KAMBLE, NANDAKUMAR PEETHAMBARAM, ABHIJIT PRABHAKAR KUMBHARE, VIJOY A. PANDEY
  • Publication number: 20140068344
    Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Gary L. Miller
  • Publication number: 20140068359
    Abstract: A memory device includes a command decoder for generating a test selection code and a test setup data by decoding an external command and an external address, a non-volatile memory for storing an internal setup data, a counter for generating an internal selection code by counting a clock, a first selector for selecting the test selection code during a test mode operation, selecting the internal selection code during a boot-up operation, and transferring the selected selection code through a selection code transfer bus, a second selector for selecting the test setup data during the test mode operation, selecting the internal setup data that is outputted from the non-volatile memory during the boot-up operation, and transferring the selected selection code through a setup data transfer bus; and setup circuits for performing a setup operation based on the information transferred through the selection code transfer bus and the setup data transfer bus.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Kwanweon KIM, Hyunsu Yoon, Jeongtae Hwang
  • Publication number: 20140047284
    Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Robert P. Masleid, Ali Vahidsafa
  • Publication number: 20140040668
    Abstract: Method and system for a test process. The method may include performing tests on one or more units under test (UUTs). At least one test on one or more UUTs may be performed. A signal may be acquired from the UUT. A reference signal may be retrieved. The reference signal may be derived from a transmitted signal characteristic of the UUT. The signal may be analyzed with respect to the reference signal. Results, useable to characterize the one or more UUTs, from performing the at least one test on the one or more UUTs may be stored. The reference signal may be derived from an initial test and may be stored for subsequent retrieval. A respective reference signal may be retrieved for all UUTs of the one or more UUTs for a respective test. The signal may be a radio frequency signal. The UUT may be a wireless mobile device.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Inventors: Craig E. Rupp, Gerardo Orozco Valdes, I. Zakir Ahmed, Vijaya Yajnanarayana
  • Publication number: 20130332783
    Abstract: A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Inventor: Alberto Troia
  • Publication number: 20130326293
    Abstract: An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: Naveen Muralimanohar, Norman Paul Jouppi, Melvin K. Benedict, Andrew C. Walton
  • Publication number: 20130326295
    Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.
    Type: Application
    Filed: September 14, 2012
    Publication date: December 5, 2013
    Applicant: SK Hynix Inc.
    Inventors: Tae Ho JEON, Junw Seop JUNG, Sung Hyun JUNG
  • Publication number: 20130290797
    Abstract: A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chen He, Kelly K. Taylor
  • Publication number: 20130238937
    Abstract: A display device is coupled to a computer, and the computer accommodates a motherboard. The display device includes an interface unit connected to the motherboard, a display panel, and a processor electrically coupled to the interface unit. The processor is used to: receive a power-on self test (POST) code from the motherboard via the interface unit, convert the POST code into a debug code, and control the display panel to display the debug code.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 12, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD
    Inventors: YI-XIN TU, ZHENG-QUAN PENG, ZHAO-YANG CAI, HAI-QING ZHOU
  • Publication number: 20130227366
    Abstract: Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof.
    Type: Application
    Filed: August 20, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: Tessa A. LAU, Jalal U. Mahmud, Pablo Pedemonte
  • Publication number: 20130212444
    Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif
  • Publication number: 20130205178
    Abstract: A system and method for auditing memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A determination is made whether content in the memory card is acceptable or unacceptable. A first volume name of the memory card is rewritten to the second volume name in response to determining the content in the memory card is acceptable.
    Type: Application
    Filed: October 31, 2012
    Publication date: August 8, 2013
    Applicant: ATC & Logistics & Electronics, Inc.
    Inventor: ATC & Logistics & Electronics, Inc.
  • Publication number: 20130205177
    Abstract: A system and method for verifying memory cards. A memory card is received in a card reader in communication with a computing device. The memory card is scanned utilizing a computing device. A visual indicator is displayed on the computing device indicating whether the card is functioning correctly and whether the memory card passed or failed the scanning. An identifier associated with the memory card is stored in response to determining the memory card passed the scanning. A first volume name of the memory card is rewritten to the second volume name in response to storing the identifier.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 8, 2013
    Inventor: Jimmie Paul Partee
  • Publication number: 20130191690
    Abstract: A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.
    Type: Application
    Filed: November 19, 2012
    Publication date: July 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Publication number: 20130173972
    Abstract: A system and method for early detection and reporting of an impending NAND Flash device plane failure. Each time that a data unit is retrieved from a NAND Flash array the number of bits in error and the memory location associated with the errors is observed. if the number of bits in error or the error rate for a memory location exceeds a threshold of the number of bits in error per data, retrieval, or number of bits in error per data unit per unit time, a NAND Flash plane failure Patrol Read operation is performed at the memory location, regardless of where in the cycle the Patrol Read function is in a scrub of the overall NAND Flash device. The NAND Flash plane failure Patrol Read is repeated for a number of cycles on the NAND Flash plane in question.
    Type: Application
    Filed: February 14, 2012
    Publication date: July 4, 2013
    Inventor: Robert Kubo
  • Publication number: 20130166960
    Abstract: A method and an apparatus for testing a network. A source port unit may generate a packet including a payload, the payload comprising a content identifier and content data in accordance with the content identifier, and transmit the packet via the network. A destination port unit may receive the packet and extract the content identifier and received content data from the received packet. The destination port unit may obtain expected content data in accordance with the extracted content identifier and compare the expected content data and the received content data.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Soumava Das, Sumit Panda, Pratik Ganguly
  • Publication number: 20130159773
    Abstract: An information processing apparatus includes a plurality of controller modules capable of performing communications with each other, and a memory included in each controller module to be stored with status information reflecting a status of an error occurring during the communications with other controller modules with respect to the controller module of a communication partner apparatus and/or the controller module of the self-apparatus, wherein, when determining whether or not a fault occurs in a certain controller module in the plurality of controller modules, the controller module different from a determination target controller module determines, based on status information of the determination target controller module that is stored on the memories of two or more controller modules different from the determination target controller module, whether the fault occurs in the determination target controller module.
    Type: Application
    Filed: October 24, 2012
    Publication date: June 20, 2013
    Inventor: FUJITSU LIMITED
  • Publication number: 20130159798
    Abstract: A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation.
    Type: Application
    Filed: August 31, 2012
    Publication date: June 20, 2013
    Applicant: SK hynix Inc.
    Inventor: Hea Jong YANG
  • Publication number: 20130117612
    Abstract: During starting of a field device for pressure measurement, flow measurement and/or fill level measurement, which field device including a memory that includes a boot memory region in which a boot function is stored, and an operating memory region in which an operating function is stored, the following steps are carried out: carrying out the boot function; determining whether a memory check of the operating memory region is to be carried out; carrying out a memory check of the operating memory region when it has been determined that a memory check is to be carried out; and carrying out the operating function.
    Type: Application
    Filed: October 18, 2012
    Publication date: May 9, 2013
    Applicant: VEGA Grieshaber KG
    Inventor: VEGA Grieshaber KG
  • Publication number: 20130097460
    Abstract: A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130091388
    Abstract: A method for transparent debug of a hardware queue and recreation of an operational scenario comprising: use of a computer device to: monitor a plurality of inputs and outputs from a plurality of hardware queues associated as parts of a design; receive a request to save from an external source; pause one or more hardware queues upon command; receive hardware queue information from at least one of the paused hardware queues; dump said hardware queue information from at least one paused hardware queue; store the hardware queue information in a data storage connected to the computing device; compare the received information to stored data representative of a functional hardware queue; identify errors and failures in each monitored hardware queue from the comparing and; restore the hardware queue to a previous state.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: LSI CORPORATION
    Inventors: Carl E. Gygi, Craig R. Chafin
  • Publication number: 20130086430
    Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a diagnostic test should be performed on a hardware component of a plurality of hardware components, wherein the plurality of hardware components support a plurality of agent devices and at least one agent device of the plurality of agent devices is assigned to at least one of the plurality of hardware components; ensuring that no agent device of the plurality of agent devices is assigned to the hardware component; and after ensuring that no agent device of the plurality of agent devices is assigned to the hardware component, performing the diagnostic test on the hardware component, wherein at least one other hardware component of the plurality of hardware components continues operation during performance of the diagnostic test.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Alcatel-Lucent USA, Inc.
    Inventors: Eric J. Bauer, Randee S. Adams, William D. Reents, Mark M. Clougherty
  • Publication number: 20130080838
    Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.
    Type: Application
    Filed: November 19, 2012
    Publication date: March 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Patent number: 8407410
    Abstract: Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, John P. Karidis, Luis A. Lastras-Montano
  • Publication number: 20130073905
    Abstract: A method includes instantiating a cloned network that includes a second set of virtual service nodes. The second set of virtual service nodes includes at least one cloned virtual service node that is a clone of a corresponding virtual service node in a first set of virtual service nodes. The at least one cloned virtual service node has access to a history of events that occurred at the corresponding virtual service node in the first set of virtual service nodes. The method includes initiating an interactive debugging session that includes processing of the events of the history of events.
    Type: Application
    Filed: October 31, 2012
    Publication date: March 21, 2013
    Applicant: AT&T Intellectual Property I, L.P.
    Inventor: AT&T Intellectual Property I, L.P.
  • Publication number: 20130067284
    Abstract: A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 14, 2013
    Applicant: MIPS TECHNOLOGIES, INC.
    Inventors: Thomas Benjamin Berg, Ryan C. Kinter, Jaidev Prasad Patwardhan, Radhika Thekkath
  • Publication number: 20130055024
    Abstract: A central processing unit (CPU) test system includes a CPU socket, a CPU core controller, and a CPU test device. The CPU core controller stores a start voltage message. The CPU test device includes a voltage detection pin, an analog to digital (A/D) converter, and a microcontroller. The voltage detection pin detects a voltage of an electronic device connected to the CPU socket. The A/D converter converts the detected voltage into a digital signal. The microcontroller controls the CPU core controller to output the start voltage to the CPU socket according to the digital signal. The microcontroller stores a predetermined start voltage message. The microcontroller reads the start voltage message after controlling the CPU core controller to output the start voltage, and determines whether the CPU core controller supplies the start voltage to the CPU socket by comparing the read start voltage message with the predetermined start voltage message.
    Type: Application
    Filed: September 22, 2011
    Publication date: February 28, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD LTD.
    Inventors: YING-BIN FU, TING GE, YA-JUN PAN
  • Publication number: 20130042144
    Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.
    Type: Application
    Filed: October 18, 2012
    Publication date: February 14, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20130042143
    Abstract: The invention relates to a circuit arrangement and to a method for testing same. A circuit arrangement is provided that includes a plurality of functional units which are coupled by at least one streaming data bus. Each of the functional units includes a plurality of hardware modules and a switch matrix. At least one of the streaming data busses is provided with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement. The switch matrices are configurable to establish a streaming data path between and through the plurality of functional units which is used as a test link for any of the hardware modules of the circuit arrangement. The invention provides for non-intrusive real-time tracing in SoCs with a minimum of additional hardware resources and at low cost in terms of die size and power consumption.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 14, 2013
    Applicant: Intel Mobile Communications Technology Dresden GmbH
    Inventors: Lars Melzer, Volker Aue
  • Publication number: 20130024738
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Application
    Filed: September 27, 2012
    Publication date: January 24, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: TEXAS INSTRUMENTS INCORPORATED
  • Publication number: 20130024736
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Application
    Filed: October 2, 2012
    Publication date: January 24, 2013
    Applicant: MICRON TECHNOLOGY, INC
    Inventor: MICRON TECHNOLOGY, INC
  • Publication number: 20130013968
    Abstract: A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Robert Hetzler, William John Kabelac
  • Publication number: 20130007545
    Abstract: At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert E. Galbraith, Adrian C. Gerhard, Daniel F. Moertl
  • Publication number: 20120331345
    Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.
    Type: Application
    Filed: December 7, 2011
    Publication date: December 27, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: JIE-JUN TAN, YU-LONG LIN, HUA DONG
  • Publication number: 20120324288
    Abstract: A computing device and method tests a redundant array of independent disks (RAID) device. The computing device controls a power supply device to cut off power of the RAID device, and controls the power supply device to provide the power to the RAID device after a predetermined time. The computing device reads an original test file from the RAID device and determines if the read file is identical to the original test file stored in the computing device. The computing device displays a test result of the RAID device on a display device of the computing device.
    Type: Application
    Filed: April 26, 2012
    Publication date: December 20, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chin-Jui HSU
  • Publication number: 20120324301
    Abstract: A method for checking the functional ability of a memory element having a stack memory, wherein the stack memory occupies a defined region within the memory element. A stack memory pointer is defined, which displays, in the form of an address, a stack memory position, from which data are currently being removed or to which data are currently being written. In the memory element, a section of defined length arranged outside a memory region to be checked is delimited and used as an auxiliary memory; the current address of the stack memory pointer is stored before the start of a test program for checking the memory element and the stack memory pointer is then assigned an address associated with the auxiliary memory, so that during the test program the auxiliary memory is used as working memory; and after terminating the test program the stack memory pointer is reassigned the address of that position, which it displayed before the start of the test program.
    Type: Application
    Filed: January 28, 2011
    Publication date: December 20, 2012
    Applicant: Endress + Hauser GmbH + Co. KG
    Inventor: Franco Ferraro
  • Publication number: 20120317452
    Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20120304017
    Abstract: Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Kenneth Lee Martin
  • Publication number: 20120272108
    Abstract: A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
    Type: Application
    Filed: December 28, 2011
    Publication date: October 25, 2012
    Inventor: Dae-Suk Kim
  • Publication number: 20120266027
    Abstract: Deterioration of performance due to diagnosis processing performed when a failure occurs is prevented. A storage apparatus 10 includes a controller 11A and a plurality of expanders 112A, 121A coupled to the controller 11A to form a first system, and includes a controller 11B and a plurality of expanders 112B, 121B coupled to the controller 11B to form a second system. The controller 11A accesses the storage drive 171 through the expanders 112A, 121A, and the second controller 11B accesses the storage drive through the expanders 112B, 121B. In the storage apparatus 10, the controller 11A stores a maximum number (concurrently-executable maximum number) of communication ports 80 that are concurrently diagnosable in the first system, and repeatedly executes a process of selecting the communication ports 80 not exceeding the concurrently-executable maximum number and a process of causing the expanders 112A, 121A to diagnose the selected communication ports 80.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Applicant: HITACHI, LTD.
    Inventors: Takashi Itoyama, Ikuya Yagisawa, Yoshifumi Mimata
  • Publication number: 20120266034
    Abstract: A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 18, 2012
    Inventor: Sang-Hoon SHIN
  • Publication number: 20120260137
    Abstract: Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 11, 2012
    Applicant: DELL PRODUCTS L.P.
    Inventor: Stuart Allen Berke
  • Publication number: 20120254679
    Abstract: Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 4, 2012
    Inventors: Weijun Tan, Hongwei Song, Shaohua Yang
  • Publication number: 20120254680
    Abstract: Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 4, 2012
    Inventors: Eun Chu Oh, KyoungLae Cho, Mankeun Seo, Junjin Kong