Abstract: A memory initialization apparatus and method, and a computer system are provided. The memory initialization apparatus includes a first processor core and a memory controller that includes at least one second processor core. In a memory initialization process, the first processor core may invoke the second processor core to perform memory initialization. This helps to shorten memory initialization duration.

Abstract: A memory repair circuit of a memory module including a plurality of memory packages, the memory repair circuit including: a test circuit configured to test the plurality of memory packages to obtain fail information in each of the plurality of memory packages; and a redundancy analysis circuit configured to: obtain a redundant address count in each of the plurality of memory packages, determine a repair order of the plurality of memory packages based on the fail information and the redundant address count, and perform a virtual repair on the plurality of memory packages in the repair order to determine an address to be repaired in each of the plurality of memory packages.

Abstract: Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device is configured to receive a command (e.g., a write command or a read command) from a host device over a first set of pins and is configured to perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device is configured to exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device is configured to exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Abstract: The present invention discloses a verification device for verifying a field device. The verification device comprises a repository and verification module. The repository comprises a plurality of verification definition data sets, each verification definition data set associated with a type of field device and comprises one or more sets of threshold values of one or more corresponding operational parameters for the corresponding type of field device. The verification module obtains a corresponding verification definition data set associated with the field device under verification; measures values of the operational parameters of the field device under verification in accordance with the corresponding verification definition data set and compares the measured values of the operational parameters with corresponding threshold values of the operational parameters from a set of threshold values of the operational parameters from the corresponding verification definition data set.

Abstract: A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.

Abstract: An eFuse one-time programmable (OTP) memory is provided. The eFuse OTP memory supports inter integrated circuit (I2C) communication, and an operation method thereof. The eFuse OTP memory includes: an eFuse intellectual property (IP) which data writes once and data reads multiple times for a plurality of addresses; and an I2C slave which communicates with an I2C master based on a serial clock line and a serial data line, and performs the data write and the data read to and from the eFuse IP.

Abstract: In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the propagation of faults through the graph elements. Propagation of a known fault backward through the graph is modeled using the propagation model. This results in a causality ranking of the graph elements as possible causes of the known fault. Information indicative of the causality ranking is displayed in a user interface that shows the design of the integrated circuit.

Abstract: Methods and apparatuses for controlling a switch are provided. The method comprises: generating second control data, which is for controlling the switches, in a second cycle; determining whether a first control signal based on first control data, which has been generated in a first cycle, is being output to the charging system; and storing the second control data in a first register if it is determined that the first control signal is being output to the charging system.

Abstract: A method of operating a host device according to the present technology includes determining an area to be tested among a mapped area and an unmapped area included in a storage area of a storage device, generating a test request corresponding to the determined area, and transmitting the generated test request to the storage device.

Abstract: Provided herein are an error detection device and an error detection method to intuitively identify the reason for a handshake failure. An entire state transition flow including each state based on the communication standard and a state transition condition to be executed between states is displayed as a state transition setting screen, and an immediately preceding state in which the state transition fails and the failed state transition condition are highlighted on the state transition setting screen, when the handshake with the device under test ends.

Abstract: The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

Abstract: A method, device and computer program product for securing access to an encoded variable in a computer program with a plurality of encoded variables that each having its own dynamic signature, wherein when the encoded variable is accessed, the dynamic signature of the variable is modified, where the sum value for all dynamic signatures of all other encoded variables is controlled in an encoded tracer variable, the sum value being controlled in the tracer variables is adapted if a dynamic signature of one of the encoded variables is modified, the encoded variable is compared with the sum value stored in the encoded tracer variable to monitor the sum of the dynamic signatures, and where an error handling process is initiated in the event of a discrepancy such that all signatures in an arithmetically encoded program can be managed in a high-performance manner regardless of the complexity of the program.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor instructions into one or more registers of the second emulation processor, in response to a selection of a first programming mode associated with the second emulation processor.

Abstract: An automatic testing method includes obtaining a positioning image, analyzing position of a plurality of slots of the test motherboard in the positioning image to generate route information for insertion and testing of components; wherein photographing test motherboard and obtaining positioning image focused on the test motherboard, controlling the clamping device to insert a plurality of the components into the slots according to the route information, controlling the test motherboard to test the components, determining if there is a faulty component, controlling the clamping device to withdraw and insert the components into other slots according to the route information and controlling the test motherboard to retest the components again if there is no faulty component. An automatic testing device and a non-volatile storage medium performing the above-described method are also disclosed.

Abstract: A device for transmitting commands with a circuit of a circuit board to test a connection interface, a system and a method thereof are disclosed. In the system, an inter-integrated circuit (I2C) of the circuit board under test is used to transmit an control command to a test device, which is connected to the inter-integrated circuit via a memory connection interface of the circuit board under test, the test device converts the control command to test the memory connection interface connected thereto, so as to achieve the technical effect of improving test efficiency in testing the memory connection interface of the circuit board under test without using an external connection line.

Abstract: The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.

Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device receives a command (e.g., a write command or a read command) from a host device over a first set of pins and performs data transfer over a second set of pins with the host device according to the command. The memory device exchanges a first parity bit associated with the command with the host device, and generates a second parity bit based on the command. A parity result bit is subsequently generated based, at least in part, on the first parity bit and the second parity bit.

Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

Abstract: A method of testing an integrated circuit device, that operates at a clock frequency and that has at least one scan chain that includes a plurality of registers separated by combinatorial logic, includes establishing a respective scan chain test pattern for testing the scan chain where the scan chain test pattern includes a respective bit for each register in the plurality of registers of the scan chain, determining in advance a respective timing delay for each pair of adjacent registers in the scan chain, and, within a single clock period of the clock frequency, applying, in parallel, each bit of the respective scan chain pattern to a respective register in the plurality of registers in the scan chain, each bit of the respective scan chain pattern being applied to its respective register at a respective temporal offset, within the single clock period, based on the respective timing delay.

Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

Abstract: Various embodiments relate to a circuit system, including: an original circuit; a dual circuit, wherein the dual circuit is a dual of the original circuit; an input inverter connected the dual circuit, wherein the input inverter inverts system inputs; an output inverter connected to one of the original circuit and the dual circuit, wherein the output inverter inverts the output of the connected original circuit or dual circuit; and a comparator receiving and comparing the output of the invertor and the output of one of the original circuit and the dual circuit not connected to the inverter, wherein the comparator indicates an error when the received outputs are not identical and indicating no error when the received outputs are identical.

Abstract: Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

Abstract: A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Abstract: Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die.

Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

Abstract: A processor unit includes a memory and an ALU coupled with the memory. The processor unit also comprises a test controller, a test control register, and a signature register. The test controller manages a series of steps to test the processor unit. It overrides an ALU control signal with a replacement ALU control signal, stored in the test control register. It generates a test pattern and writes it to a memory address. It reads memory output data from the memory address, and forwards it to the ALU. The ALU executes an operation on the memory output data based on the replacement ALU control signal. The ALU output provides a test result, which is compressed to obtain a test signature, and stored in the signature register.

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

Abstract: A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

Abstract: A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

Abstract: A non-bussed control module that receives an audio code is provided. The non-bussed control module includes a tone processing module, a self-diagnostic module, and a reporting module. The tone processing module receives the audio code, and sends a trigger signal if the audio code is received. The self-diagnostic module performs a self-diagnostic test for the non-bussed control module if the trigger signal is received, and generates a diagnostic signal indicative of the self-diagnostic test. The reporting module receives the diagnostic signal and determines a type of fault based on the diagnostic signal.

Abstract: A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.

Abstract: Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.

Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.

Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

Abstract: A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.

Abstract: A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a triggering event. The debug controller reads data from memory device and provides the debug mode information external to the SoC device. The memory may include a first memory block and a second memory block, which store debug mode information. The first memory block may store debug mode information, and the second memory block may store normal mode information. A corresponding method and computer-readable medium are also disclosed.

Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.

Abstract: Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.

Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.