Built-in Tests (epo) Patents (Class 714/E11.169)
  • Patent number: 11449397
    Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 20, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Glenn David Gilda, Thomas E. Miller, Arthur O'Neill
  • Patent number: 11449404
    Abstract: A processor unit includes a memory and an ALU coupled with the memory. The processor unit also comprises a test controller, a test control register, and a signature register. The test controller manages a series of steps to test the processor unit. It overrides an ALU control signal with a replacement ALU control signal, stored in the test control register. It generates a test pattern and writes it to a memory address. It reads memory output data from the memory address, and forwards it to the ALU. The ALU executes an operation on the memory output data based on the replacement ALU control signal. The ALU output provides a test result, which is compressed to obtain a test signature, and stored in the signature register.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: September 20, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Thomas Alan Ziaja, Dinesh Rajasavari Amirtharaj
  • Patent number: 11410713
    Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Di Wu, Debra M. Bell, Anthony D. Veches, James S. Rehmeyer, Libo Wang
  • Patent number: 11360870
    Abstract: A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Maurizio Iacaruso, Gabriele Paoloni
  • Patent number: 10250281
    Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Omer Fainzilber, Ariel Navon, Alexander Bazarsky, Eran Sharon
  • Patent number: 8947957
    Abstract: A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiunn-Der Yu, Tsung-Hsiung Li
  • Patent number: 8803716
    Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Ravindranath Ramalingaiah Munnan, Raghu Ravindran, Ravi Shekhar
  • Publication number: 20140143619
    Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin W. GORMAN, Michael R. OUELLETTE, Patrick E. PERRY
  • Publication number: 20140129883
    Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
  • Publication number: 20140115392
    Abstract: A non-bussed control module that receives an audio code is provided. The non-bussed control module includes a tone processing module, a self-diagnostic module, and a reporting module. The tone processing module receives the audio code, and sends a trigger signal if the audio code is received. The self-diagnostic module performs a self-diagnostic test for the non-bussed control module if the trigger signal is received, and generates a diagnostic signal indicative of the self-diagnostic test. The reporting module receives the diagnostic signal and determines a type of fault based on the diagnostic signal.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Frank C. Valeri, Scott M. Reilly, Pawel W. Sleboda, Ian R. Singer
  • Publication number: 20140089739
    Abstract: A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.
    Type: Application
    Filed: October 30, 2012
    Publication date: March 27, 2014
    Inventors: XIAO-GANG YIN, GUO-YI CHEN
  • Publication number: 20140040685
    Abstract: Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague
  • Publication number: 20140019817
    Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Inventors: Brian S. Park, Gregory S. Scott, Anh T. Hoang
  • Publication number: 20140006885
    Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Po-Hao Huang, Chiun-Chi Shen, Jie-Hau Huang
  • Publication number: 20130326294
    Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.
    Type: Application
    Filed: October 19, 2012
    Publication date: December 5, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Yen Lo, Ding-Ming Kwai, Jin-Fu Li, Yun-Chao Yu, Che-Wei Chou
  • Publication number: 20130275822
    Abstract: A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.
    Type: Application
    Filed: April 14, 2012
    Publication date: October 17, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raguram Damodaran, Naveen Bhoria
  • Publication number: 20130275821
    Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: George M. BRACERAS, Albert M. CHU, Kevin W. Gorman, Michael R. OUELLETTE, Ronald A. PIRO, Daryl M. SEITZER, Rohit SHETTY, Thomas W. WYCKOFF
  • Publication number: 20130198566
    Abstract: A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a triggering event. The debug controller reads data from memory device and provides the debug mode information external to the SoC device. The memory may include a first memory block and a second memory block, which store debug mode information. The first memory block may store debug mode information, and the second memory block may store normal mode information. A corresponding method and computer-readable medium are also disclosed.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: LSI CORPORATION
    Inventors: Sachin Shivanand Bastimane, Hemang Rajnikant Desai
  • Publication number: 20130191695
    Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20130151913
    Abstract: Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Louie, Adam Roberts
  • Publication number: 20130151914
    Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, Thomas J. Griffin, Archana Shetty, Gary A. Tressler, Dustin J. Vanstee
  • Publication number: 20130080847
    Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
  • Publication number: 20130073906
    Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.
    Type: Application
    Filed: December 30, 2011
    Publication date: March 21, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-TSANG HSIEH, YUNG-PO CHANG
  • Publication number: 20130047049
    Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Jan CHEN, Nan-Hsin Tseng, Chin-Chou Liu
  • Publication number: 20130042144
    Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.
    Type: Application
    Filed: October 18, 2012
    Publication date: February 14, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20130019130
    Abstract: Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Publication number: 20120246527
    Abstract: According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.
    Type: Application
    Filed: September 13, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichi Anzou, Chikako Tokunaga
  • Publication number: 20120226942
    Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: TEXAS INSTRUMENTS, INCORPORATED
    Inventors: Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa B S Chakravarthy, Padmini Sampath, Rubin Ajit Parekhji
  • Publication number: 20120198291
    Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 2, 2012
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
  • Publication number: 20120179946
    Abstract: A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Inventor: Sreejit Chakravarty
  • Publication number: 20120137168
    Abstract: A method for protecting data in damaged memory cells by dynamically switching memory mode is provided. The method is adapted to an electronic device having a memory, which has a memory controller and at least one memory module, each of which is consisted of a plurality of memory cells, and the memory cells are divided into a plurality of pages. A power-on self test is executed and a mirror memory mode is activated to protect the data in the memory modules. An uncorrectable error of each page of the memory modules is detected by the memory controller when an operating system reads the memory. If the uncorrectable error in one page is detected, the memory module having the page is determined as a damaged memory module, and the mirror memory mode is switched to a spare memory mode, so as to protect the data in the memory modules.
    Type: Application
    Filed: April 1, 2011
    Publication date: May 31, 2012
    Applicant: INVENTEC CORPORATION
    Inventor: Ying-Chih Lu
  • Publication number: 20120137185
    Abstract: A method and apparatus are described for performing a memory built-in self-test (MBIST) on a plurality of memory element arrays. Control packets are output over a first ring bus to respective ones of the arrays. Each of the arrays receives its respective control packet via the first ring bus, and reads commands residing in a plurality of fields within the respective control packet. Each of the arrays performs at least one self-test based on the commands, and outputs a respective result packet over a second ring bus. Each result packet indicates the results of the self-test performed on the array. Each control packet is transmitted in its own individual time slot to a respective one of the arrays.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ganesh Venkataramanan, Wei-Yu Chen
  • Publication number: 20120110304
    Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 3, 2012
    Inventors: Christopher D. Bryant, David Kaplan
  • Publication number: 20120096314
    Abstract: Exemplary embodiments include a sequential and concurrent status detection and evaluation method for multiple processor cores, including receiving data from a plurality of processor cores, for each of the plurality of processor cores, simultaneously running a built-in self test to determine if each of the plurality of cores has failed, checking the data for a dominant logic state and recording a subset of the plurality of processor cores that have failed.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, John D. Parker
  • Publication number: 20120089879
    Abstract: A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and failure test patterns are identified from the plurality of test patterns by comparing the test result with the predicted test result. A switching activity count is obtained for each of the plurality of test patterns. Based on the switching activity count, ranks for each of the plurality of test patterns are provided. A correlation analysis is performed between the failure test patterns and the ranks of the switching activities. When there is a high correlation between the failure test pattern and the ranks of the switching activities, it is determined that the circuit likely contains a power defect. A power defect analysis is performed under the presence of the high correlation.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 12, 2012
    Inventors: Thomas Webster Bartenstein, Patrick Wayne Gallagher
  • Publication number: 20120084603
    Abstract: Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mack Wayne Riley
  • Publication number: 20120072791
    Abstract: A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Hong S. Kim, Paul F. Policke, Paul Douglas Bassett
  • Publication number: 20120069689
    Abstract: A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are compared. A repair method using either the redundant row block or the redundant column block is selected. The memory is repaired by replacing a row block having at least one faulty bit with the redundant row block or replacing a column block having at least one faulty bit with the redundant column block.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiunn-Der YU, Tsung-Hsiung LI
  • Publication number: 20120072788
    Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Wei-Yu Chen, Kevin Badgett, Kay Hesse
  • Publication number: 20120060058
    Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.
    Type: Application
    Filed: October 18, 2010
    Publication date: March 8, 2012
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventor: Suraj PRAKASH
  • Publication number: 20120036408
    Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.
    Type: Application
    Filed: December 16, 2010
    Publication date: February 9, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mujibur Rahman, Timothy Anderson, Alan Hales
  • Publication number: 20110320862
    Abstract: Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak
  • Publication number: 20110320871
    Abstract: An RS-485 port test apparatus includes an RS-485 connector, a micro control unit (MCU), a multiprotocol transceiver, and a display. The RS-485 connector receives a first test code signal from a test RS-485 port of an electronic device. The multiprotocol transceiver receives the first test code signal from the RS-485 connector, converts the first test code signal to a second test code signal which can be identified by the MCU, and transmits the second signal to the MCU. The MCU receives the second test code signal and displays the second test code signal by the display. The MCU sends back the second test code signal to the multiprotocol transceiver. The multiprotocol transceiver converts the second test code signal to the first test code and transmits the first test code to the test RS-485 port of the electronic device through the RS-485 connector.
    Type: Application
    Filed: July 14, 2010
    Publication date: December 29, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD .
    Inventor: ZHAO-JIE CAO
  • Publication number: 20110302471
    Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 8, 2011
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Hervé Le-Gall
  • Publication number: 20110296259
    Abstract: A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit are tested at speed.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bargav Balakrishnan, Pradip Patel, Antonio R. Pelella, Daniel Rodko
  • Publication number: 20110276829
    Abstract: A client server and a test monitoring method for the client server include receiving a customization Intelligent Platform Management Interface (IPMI) from the monitor server and parsing the customization IPMI command to be a command suitable for the client server. The monitor method further includes obtaining a test result of the customization IPMI command and transmitting a determined IPMI return value corresponding to the test result to the monitor server, with the monitor server recording a test of the customization IPMI command.
    Type: Application
    Filed: November 7, 2010
    Publication date: November 10, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: CHAO-DONG PENG, YANG ZHONG, JI-BAO CHEN
  • Publication number: 20110231718
    Abstract: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 22, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Klaus Oberlaender
  • Publication number: 20110231716
    Abstract: A system and a method for diagnosis flow for a read-only memory (ROM) includes determining whether a window of the ROM is faulty, based on a pre-computed signature and a computed signature corresponding to the window. Based on the determination, the size of the window is reduced to form at least two reduced windows. It is further ascertained whether the at least two reduced windows are faulty based on pre-computed signatures corresponding to the at least two reduced windows and computed signatures corresponding to the at least two reduced windows.
    Type: Application
    Filed: April 27, 2010
    Publication date: September 22, 2011
    Applicant: ST MICROELECTRONICS Pvt Ltd.
    Inventor: Suraj PRAKASH
  • Publication number: 20110209012
    Abstract: The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CMmax). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 25, 2011
    Inventors: Abhishek Kumar Tiwary, Anubhav Singh, Anuj Verma, Arnab Bhattacharya
  • Patent number: 7984352
    Abstract: A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Karl F. Greb