Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Abstract: Poly-bit cells and methods for forming the same are provided. In one example, a method for forming a poly-bit cell includes identifying layouts in a library of single-bit cells having one or more of a different functionality and a different drive that are combinable; storing, in memory, layouts that are combinable; and creating layouts of poly-bit cells from the stored combinable single-bit cells. Each poly-bit cell combined from layouts of at least two single-bit cells has one or more of a different functionality and a different drive.

Abstract: This invention is embodied in an energy yield optimization device that can be used to optimize energy yields for a utility-scale photovoltaic power plant. More specifically, this solution is directed to utility-scale photovoltaic power plants that have undulating (non-planar) topography. Because of the undulating topography, the rotating axles of the solar trackers will not necessarily be horizontal and would be expected to be different for each independent rotating axle in the field. The preferred solution claimed herein deploys a marching algorithm to find the preferred optimum solution.

Abstract: A method for calibrating a quantum-computing operation comprises: (a) providing a trial control-parameter value to the quantum computer; (b) receiving from the quantum computer a result of a characterization experiment enacted according to the trial control-parameter value; (c) computing a decoder estimate of an objective function evaluated at the trial control-parameter value based on decoding the result of the characterization experiment; (d) consuming the trial control-parameter value and the decoder estimate in a machine trained to return a model estimate of the objective function evaluated at the trial control-parameter value; and (e) selecting a new trial control-parameter value based on the model estimate.

Abstract: A graph data processing method includes: acquiring target graph data to be processed; compiling statistics on the target graph data according to a first preset rule, so as to divide the target graph data into a plurality of graph data blocks and determine a boundary value and weight of each of the plurality of graph data blocks; and storing the boundary value and weight of each of the plurality of graph data blocks in a corresponding memory according to a second preset rule, so as to schedule the target graph data during a graph calculation process by use of the boundary values and the weights.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

Abstract: Apparatuses, computer implemented methods and non-transitory computer-readable media storing instructions to implement simulating topological features of layout designs are disclosed. An example method includes: receiving information about the layout design including topological parameters in a verification area; defining a width and a length in first and second direction directions of one or more windows; defining first and second step sizes independently from the width and the length in the first and second directions for the one or more windows, the first step size being a distance between adjacent central points of the one or more windows in the first direction and the second step size being a distance between adjacent central points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window locations; and storing the information in a database.

Abstract: Aspects of the subject technology relate to systems and methods for constraints-based layout and control of user interface (UI) elements. The system receives a first user input indicating an instruction to position a first UI element on a page of the layout application. The system receives a second user input indicating an instruction to position a second UI element on the page. The system receives a third user input indicating an instruction to create a connection from the second UI element to the first UI element. The system generates a layout constraint indicating a spatial relationship between the first UI element and the second UI element based on the connection. The system provides the layout constraint in a layout data file associated with the UI.

Abstract: The disclosure provides an image processing method and apparatus. The method may include acquiring a target image having at least two division regions. The division region includes an annotation point, and the annotation point is corresponding to a target segmentation object. The method may further include performing iterative expansion on the annotation points to obtain an iterative expansion region. The method may further include determining a first loss result between the iterative expansion region and the division region and a second loss result between the iterative expansion region and the annotation point. The method may further include, when the first loss result and the second loss result meeting a termination condition, stopping the iterative expansion to obtain a resulting iterative expansion region. The method may further include determining the resulting iterative expansion region as a region where the target segmentation object is located in the target image.

Abstract: A metrology system may receive design data including a layout of fabricated instances of a structure on a sample. The system may further receive detection signals from the metrology tool associated within a field of view including multiple of the fabricated instances of the structure. The system may further generate design-assisted composite data for the structure by combining detection signals from one or more common features of the structure associated with the fabricated instances of the structure within the field of view using the design data. The system may further generate one or more metrology measurements of the structure based on the design-assisted composite data.

Abstract: Technologies directed to correcting terrestrial interference using narrowband adaptive filtering and beamforming technology are described. One method includes receiving a first and second radio frequency (RF) signal. The method includes generating first digital samples corresponding to the first RF signal using a first sample rate and generating second digital samples corresponding to the first RF signal using a second sample rate that is lower than the first sample rate. The method further includes generating third digital samples corresponding to the second RF signal using the second sample rate. The method further includes determining parameters associated with a filtering process using the second digital samples and the third digital samples. The method further includes generating fourth digital samples using the parameters of the filtering process. The method further includes removing a first portion from the first RF signal using the first digital samples and the fourth digital samples.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.

Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.

Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.

Abstract: An illustrative data storage management system relies on a specially configured proxy server to operate software containers on a proxy server, maintain resources needed by the software containers, and interwork with other system components. Illustratively, a catalog service on the proxy server maintains a software cache according to maintenance rules and also maintains an associated cache catalog. The software containers are generally managed and operated by an illustrative container manager also hosted by the proxy server. The illustrative software cache comprises contents needed by the software containers, such as pre-configured container templates, DBMS software components, lightervisors representing target operating systems, and storage management software for performing test and storage operations. The maintenance rules govern when cache contents should be purged and moved into offline archive copies.

Abstract: Machine assisted systems and methods for use in meshing a periodic pattern of a geometry that represents a physical structure in a simulation of the physical structure are described. The method can include operations: identifying a master region in a periodic pattern of a geometry that represents a physical structure in a simulation of the physical structure that has the periodic pattern; and generating a mesh based on the identified master region, the mesh including a non-planar boundary at a boundary between patterns in the periodic pattern, wherein the master region is only a portion of the representation of the physical structure.

Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

Abstract: A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.

Abstract: Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.

Abstract: A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.

Abstract: A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A method for selecting an optimal set of locations for a measurement or feature on a substrate, the method includes: defining a first candidate solution of locations, defining a second candidate solution with locations based on modification of a coordinate in a solution domain of the first candidate solution, and selecting the first and/or second candidate solution as the optimal solution according to a constraint associated with the substrate.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

Abstract: Embodiments for tuning parameters to a synthesis program are provided. At least one set of parameter settings for the synthesis program is selected. A plurality of identical synthesis jobs for the at least one set of parameter settings is run in an iteration of the synthesis program. Results of the iteration of the synthesis program are analyzed utilizing a tuning optimization cost function. Combinations of the parameter settings are created based on the analysis. At least one synthesis job for is run each of the combinations of the parameter settings in a subsequent iteration of the synthesis program. The analysis of the results, the creating of the combinations of parameter settings, and the running at the at least one synthesis job for each of the combinations of parameter settings are repeated until an exit criteria has been achieved.

Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: Example embodiments relate to a method for designing integrated circuit based on a computer program including at least one instruction performed by an integrated circuit design system including a processor, the method comprising mapping, by the processor, at least one netlist signal to at least one RTL signal, determining, by the processor, a target netlist signal among the at least one netlist signal, determining, by the processor, a target expression of the target netlist signal using the netlist signal mapped to the at least one RTL signal based on at least a part of the netlist circuit, simulating, by the processor, on the at least one RTL signal, calculating, by the processor, signal simulation predicting information for the target netlist signal using the target expression and generating, by the processor, a design model by designing an integrated circuit using the signal simulation predicting information.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.

Abstract: A method for forming an integrated circuit (IC) is provided. The method includes obtaining an IC design; generating a layout according to the IC design; calculating a score of a region in the layout based on voltage levels in the region; and fabricating a semiconductor device according to the layout when the score of the region in the layout is equal to or less than a threshold value.

Abstract: This invention is embodied in a cost-optimization device for the layout and construction of a utility-scale photovoltaic (“PV”) power plant. The optimization device employs a set of algorithms designed to find the most cost-effective solution under given conditions. The algorithms are written in computer machine readable code and are highly customizable for the specific tracker equipment requirements and owner/builder/maintainer specifications or preferences. The preferred optimization device comprises three principal stages (or “units”) of computing: (1) an objective-state unit, (2) an optimum-feasible unit, and (3) a grading unit. In the first stage, the objective-state unit cost-optimizes site grading by orienting a ruling line between a maximum and a minimum pile reveal length for each tracker in the project (the objective-state solution”). When compared to the existing site topography, the ruling line indicates cost-optimized cut and fill locations.

Abstract: An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation host system can configure the reprogrammable hardware emulation system to emulate the electronic circuits using the single PLE.

Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: This application is directed to methods and systems of verifying integrated circuit including an irregular shaped transistor device. The irregular shaped transistor device has a gate, a source, a drain, and a first channel connecting the source and drain and having an irregular shape. An equivalent resistance of the first channel is determined based on the irregular shape of the first channel. A length of the first channel is determined optionally based on locations of the source and drain. An equivalent width of the first channel of the irregular shaped transistor device is determined based on the equivalent resistance and length of the first channel, thereby enabling representation of the irregular shaped transistor device, by a regular shaped transistor device having a second channel, in analysis of the integrated circuit. The second channel optionally has a rectangular shape measured by the equivalent width and the length of the first channel.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

Abstract: A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ? t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

Abstract: In a system automatically processing data from a first computing device for use on a second computing device, a registry file including a plurality of filename parameters is read. Each filename parameter identifies a matching filename pattern, an extract script indicator, and a read file indicator. The extract script indicator indicates an extract script for a file having a filename that matches the matching filename pattern. The read file indicator indicates how to read the file having the filename that matches the matching filename pattern. One parameter of the plurality of filename parameters is selected by matching a filename of a source file to the matching filename pattern of the one parameter. The associated extract script is selected and used to read data from the source file using the associated read file indicator and the read data is output to a different file and in a different format.

Abstract: Apparatus and methods provide the effectiveness decay rate of actual police enforcement by allowing the user to chart the speeds in a particular location and overlay times when an officer was present and providing on-site enforcement. The system can monitor the speed in the location and when the speeds creep back up to a set speed or multiple of the speed after the enforcement period, the officer can be notified to provide enforcement again and reduce the speeds. For example, once the police car goes away, some locations may take longer for the average speed to creep back up to normal and others may have the average speed increase more quickly. A visual display of the situation provides a systematic method for determining enforcement locations and timing in place of conventional “seat-of-the-pants” enforcement planning.

Abstract: Methods and systems for creating and implementing improved routing polygon abstracts that can be used to efficiently find areas to route through in electrical designs, where the routing polygon abstracts include at least a horizontal routing polygon abstract, a maximum horizontal routing polygon abstract, a vertical routing polygon abstract, and a maximum vertical routing polygon abstract, that are created through various steps including bloating, shrinking, merging, and extending the objects towards an outer boundary.

Abstract: A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule criteria. The method further comprises reviewing a representation of G0-space and G0 rule violations for each cell of the plurality of cells. The method additionally comprises inputting an adjustment to the layout data. The method also comprises reviewing a representation of adjusted cell edge spacings, and selecting to output a final layout.

Abstract: In a system automatically processing data from a first computing device for use on a second computing device, a registry file including a plurality of filename parameters is read. Each filename parameter identifies a matching filename pattern, an extract script indicator, and a read file indicator. The extract script indicator indicates an extract script for a file having a filename that matches the matching filename pattern. The read file indicator indicates how to read the file having the filename that matches the matching filename pattern. One parameter of the plurality of filename parameters is selected by matching a filename of a source file to the matching filename pattern of the one parameter. The associated extract script is selected and used to read data from the source file using the associated read file indicator and the read data is output to a different file and in a different format.

Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.

Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.