Abstract: In a method for cooling a semiconductor, a time profile of a load of the semiconductor is determined over a predefinable period of time. A cooling apparatus for cooling the semiconductor is controlled or regulated depending on a load cycle of the semiconductor resulting from the determined time profile of the load, and the cooling apparatus is controlled or regulated as a function of the load averaged over the predefinable period of time.

Abstract: A switch device structure includes RF1-st and RF2-nd input terminals, RFA-th, RFB-th and RFC-th output terminals, P2A-th, P1B-th and P1C-th paths, and first and second common paths. The P2A-th path includes a first terminal, and a second terminal coupled to the RFA-th output terminal. The P1B-th path includes a first terminal, and a second terminal coupled to the RFB-th output terminal. The P1C-th path includes a first terminal, and a second terminal coupled to the RFC-th output terminal. The first common path is coupled to the RF2-nd input terminal and the first terminal of the P2A-th path. The second common path is coupled to the RF1-st input terminal, the first terminal of the P1B-th path, and the first terminal of the P1C-th path. The first and second common paths cross each other on different planes to form a crossover.

Abstract: The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

Abstract: A network controller receives link metrics for network links on cables between network devices in a communication network. The link metrics include metrics indicative of crosstalk experienced by network links among the network links on cables. The network controller determines, based at least in part on the link metrics, respective link settings for respective network links among the network links. The link settings are determined to mitigate crosstalk experienced by the respective network links as a result of transmission of signals in at least some of the network links at baud rates that correspond to bandwidths that exceed maximum bandwidth ratings of respective cables of the corresponding ones of the network links. The network controller causes configuration of the respective network links based on the link settings to optimize performance across the plurality of network links in the communication network.

Abstract: Disclosed are a quick simulation and optimization method and system for analog circuits. Aiming at a problem that a customized circuit model is difficultly modeled in a design process of the analog circuit, and the problem of a low circuit design efficiency caused by a slow electromagnetic field simulation speed, the invention proposes to firstly construct a device library, build a circuit and interconnect an AI network to obtain a comprehensive network parameter of the AI network; the comprehensive network parameter in a simulation process is compared with a network parameter target of an analog circuit, and an circuit layout of the analog circuit corresponding to the AI network is output to a three-dimensional full-wave electromagnetic field simulation tool for simulation and verification when requirements are met.

Abstract: A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.

Abstract: Control system (1) for a state of a quantum harmonic oscillator, comprising: —a harmonic oscillator (3) in a Schrödinger's cat type state, —a stabilisation device (10) with a predetermined parity of a number of bosons of the state, which device is configured to use first and second frequency combs each comprising at least as many rays as a mean number of bosons in the state, and —a multiphonic dissipation device (20) which is suitable for removing at least one pair of bosons simultaneously from the oscillator, the dissipation device being activated only between two successive time peaks of the frequency combs over a time period greater than the inverse of the product of the mean number and the inverse of the characteristic time of the multiphonic dissipation, a time period separating two activation periods being less than a characteristic loss time of a boson.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: The present invention relates to a method for determining a configuration operable by a configurable electronic device. The device receives a second configuration and a predefined parameter. The device archives a first configuration in the non-transitory computer readable storage medium. The device applies the second configuration and then determine whether the predefined parameter is satisfied. When the predefined parameters are satisfied, the device maintains to apply the second configuration. When the predefined parameter is not satisfied, the device retrieves the first configuration and applies the first configuration.

Abstract: A computer-implemented method of interactive machine learning in which a user is provided with predicted results from a trained machine learning model. The user can take the predicted results and either: i) adjust the predicted results and input the adjusted results as new data; or ii) adjust the predicted data to retrain the model.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a primary capacitor structure and an outer capacitor structure. Each of the primary capacitor structure and the outer capacitor structure includes a first crisscross structure and a second crisscross structure that are staggered. Each of the first crisscross structure and the second crisscross structure includes longitudinal conductive strips and lateral conductive strips, wherein the longitudinal conductive strips are disposed in a first integrated circuit (IC) layer and the lateral conductive strips are disposed in a second IC layer. The second crisscross structure of the primary capacitor structure and the first crisscross structure of the outer capacitor structure jointly generate the parasitic capacitance.

Abstract: A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

Abstract: A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.

Abstract: Disclosed are techniques for wireless communication. In an aspect, a relative location anchor group (RLAG) may facilitate a position estimation procedure in an environment where absolute position estimation accuracy is below a threshold. An absolute position estimate derived via the RLAG may optionally be transformed to a true (or more accurate) position estimate via transformation information. In some cases, new anchors may be added to the RLAG after performing a position estimation procedure with the RLAG. In other designs, a local coordinate system (LCS) may be used for position estimation in lieu of a global coordinate system (GCS), such as WGS 84.

Abstract: Implementations disclosed describe methods and systems to perform the methods of deploying and executing machine learning models on target-specific computational platforms. Optimization techniques include but are not limited to alignment of kernel operations with hardware instructions of a target processing device, reduction of kernel dimensions near boundaries of data, efficient reuse of a small number of memory components during neural network operations, run-time quantization of data and neural network parameters, and other methods.

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

Abstract: Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.

Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Abstract: Disclosed are a quantum topology graph optimization method, apparatus, terminal and storage medium, comprising: obtaining a first quantum topology graph of a target quantum algorithm, determining an intermediate node in the first quantum topology graph, and removing connecting lines between other graph nodes other than the intermediate node so as to obtain a second quantum topology graph without the crossed connecting lines; if not, updating the first quantum topology graph to a third quantum topology graph; determining an optimized sub-graph corresponding to one node to be optimized and composed of N child nodes connected by connecting lines according to a preset way, assigning connecting lines between non-optimized nodes and each child node so as to obtain a fourth quantum topology graph; restoring connecting lines between non-optimized nodes in the fourth quantum topology graph so as to obtain an optimized quantum topology graph.

Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Abstract: A disclosed example to determine a migration recommendation of a service between geographic regions includes: a graph generator to generate an interaction graph, the interaction graph including first and second nodes and an edge therebetween, the first node representative of a first service in a first geographic region, the second node representative of a second service in a second geographic region, and the edge representative of a network path of interactions between the first and second services; a weighing engine to determine a weight value of the edge between the first and second services based on a count of network interactions between the first and second services and a real-time latency between the first and second services; and a recommendation engine to generate a migration recommendation to migrate the first service to the second geographic region based on the weight value of the edge.

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

Abstract: An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.

Abstract: Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case configurations for a given IC design based on features extracted from the given IC design.

Abstract: A method for source mask optimization with a lithographic projection apparatus. The method includes determining a multi-variable source mask optimization function using a plurality of tunable design variables for an illumination system of the lithographic projection apparatus, a projection optics of the lithographic projection apparatus to image a mask design layout onto a substrate, and the mask design layout. The multi-variable source mask optimization function may account for imaging variation across different positions in an exposure slit corresponding to different stripes of the mask design layout exposed by a same slit position of the exposure apparatus. The method includes iteratively adjusting the plurality of tunable design variables in the multi-variable source mask optimization function until a termination condition is satisfied.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout so as to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips disposed in a first integrated circuit (IC) layer; and lateral first conductive strips disposed in a second IC layer. The longitudinal and lateral first conductive strips jointly form well-type structures including outer wells and inner wells that are electrically connected. The second conductive structure includes second conductors disposed in the first IC layer. The second conductors include outer conductors and inner conductors that are electrically disconnected and respectively disposed in the outer wells and the inner wells. The outer wells and the closest inner conductors jointly generate parasitic capacitance.

Abstract: A semiconductor package structure and method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a connection layer formed on a metal base layer, at least one die unit formed on the connection layer, a metal pillar connecting the metal base layer and surrounding the die unit, and an interconnect structure overlaid onto the die unit and the metal pillar. Each die unit comprises at least one die attached onto the connection layer and surrounded by a molding structure. The interconnect structure includes a first interconnect layer overlaid onto the die unit and the metal pillar and a second interconnect layer formed on the first interconnect layer. The first and second interconnect layers comprise first and second metal layers being parallel with the top surface of the die unit. A projection of the metal layers overlaps an upper surface of the die.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: The disclosure relates to a method for the modular adjustment of a programmable controller. A base run-time system is provided. Unambiguous references having a determined sequence are defined in the base run-time system. At least one function object is provided with one or several methods to be carried out and at least one function pointer to one or several of the methods. Each function pointer is linked to a defined unambiguous reference. At least one provided function object is executed on the basis of the linked unambiguous references.

Abstract: Disclosed are a method, system and device for manufacturing a printed circuit board, and a computer storage medium. The method comprises: acquiring a printed circuit board to be manufactured which includes a via hole; acquiring shape information of the via hole; acquiring connection information of circuit layers in said printed circuit board; assembling preset conducting devices according to the connection information and the shape information, so as to obtain a target conducting device that matches the connection information and the shape information; guiding the target conducting device into the via hole to obtain a conducting printed circuit board; and connecting the conducting printed circuit board to obtain a target printed circuit board, wherein the types of the preset conducting devices comprise a metal conducting device, a non-metal conducting device and a semi-metal conducting device.

Abstract: Approaches for logic compaction include inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor. The synthesis tool identifies a multiplier and/or an adder specified in a circuit design and synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization. The synthesis tool synthesizes the multiplier and/or adder into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization. The method includes implementing a circuit on the programmable IC from the logic having LUT-carry connections in response to the optimization directive specifying area optimization.

Abstract: A method for determining a training pattern in a layout patterning process. The method includes generating a plurality of features from patterns in a pattern set; grouping the patterns in the pattern set into individual groups based on similarities in the plurality of generated features; and selecting representative patterns from the individual groups to determine the training pattern. In some embodiments, the method is a method for training a machine learning model in a layout patterning process. The method may include, for example, providing representative patterns from the individual groups to the machine learning model to train the machine learning model to predict a continuous transmission mask (CTM) map for optical proximity correction (OPC) in the layout patterning process.

Abstract: A method for calibrating a process model of a patterning process. The method includes identifying a portion of the substrate that has values within a tolerance band of one or more parameters (e.g., CD, EPE, etc.) of the patterning process, obtaining, via a metrology tool, metrology data corresponding to the portion of the substrate, processing the metrology data, and calibrating a process model based on the processed metrology data.

Abstract: A computing device is provided, including a cluster update accelerator circuit configured to receive signals encoding a combinatorial cost function of a plurality of variables and a connectivity graph for the combinatorial cost function. In an energy sum phase, the cluster update accelerator circuit may determine a respective plurality of accumulated energy change values for the combinatorial cost function based at least in part on the connectivity graph. In an update phase, the cluster update accelerator circuit may determine a respective update indicator bit for each accumulated energy change value. In an encoder phase, based on the plurality of update indicator bits, the cluster update accelerator circuit may select a largest update-indicated cluster of the variables included in the connectivity graph. The cluster update accelerator circuit may output an instruction to update the variables included in the largest update-indicated cluster.

Abstract: This invention relates to a robust optimal design method for photovoltaic cells. Firstly, the deterministic optimal model is established, which is solved by Monte Carlo method to obtain the maximum output power value of optimization objective and its corresponding design variable value, and then the design variable value obtained from deterministic optimization is deemed as the initial point of the mean value of the robust optimal design variable. Later, the robust optimal model is solved by Monte Carlo method in order to obtain the mean value of design variable, and then appropriate materials and manufacturing techniques are selected for corresponding photovoltaic components according to the design variable obtained, so as to achieve the robust optimal design of photovoltaic cells. In fact, this invention improves the output stability and reliability of photovoltaic cells.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: A method for obtaining learned self-consistent electron density and/or derived physical quantities includes: conducting non-self-consistent (NSC) calculation to generate a first NSC dataset X1 from a first plurality of configurations of atoms; conducting self-consistent (SC) calculation to generate a first SC dataset Y1 from the first plurality of configurations of atoms; mapping the first NSC dataset X1 to the first SC dataset Y1 utilizing machine learning algorithm to generate a mapping function F; and generating a learned self-consistent data Y2 from a new NSC data X2 utilizing the mapping function F.

Abstract: A method designs nuclear reactors using design variables and metric variables. A user specifies ranges for the design variables and threshold values for the metric variables and selects design parameter samples. For each sample, the method runs three processes, which compute metric variables for thermal-hydraulics, neutronics, and stress. The method applies a cost function to compute an aggregate residual of the metric variables compared to the threshold values. The method deploys optimization methods, either training a machine learning model using the samples and computed aggregate residuals, or using genetic algorithms, simulated annealing, or differential evolution. When using Bayesian optimization, the method shrinks the range for each design variable according to correlation between the respective design variable and estimated residuals using the machine learning model. These steps are repeated until a sample having a smallest residual is unchanged for multiple iterations.

Abstract: The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented N methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

Abstract: In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

Abstract: One embodiment provides a method, including: obtaining at least one video capturing images of a writing capture device used during a business process design session, wherein the images comprise portions of the process flow; obtaining at least one audio recording corresponding to the business process design session; identifying an intended business process model shape; determining at least one business process model shape missing from the process flow provided on the writing capture device; identifying a task dependency for pairs of business process model shapes; and generating a business process model from (i) the intended business process model shapes, (ii) the at least one business process model shape missing from the process flow, and (iii) the identified task dependencies.

Abstract: A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one current cell will have to be moved in order to place the ECO cell in the target region. Timing slacks for current cells in a neighborhood of the target region are determined. Based on the timing slacks of the current cells, at least one of the current cells is moved to a different location to create sufficient open space to place the ECO cell within the target region.

Abstract: A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

Abstract: According to one embodiment, a design support device executes a first processing. The first processing includes setting a control value group for a semiconductor element. The semiconductor element includes gates including first and second gates. The control value group includes a first time difference between first and second timings. A voltage is applied to the first gate at the first timing. A voltage is applied to the second gate at the second timing. The first processing includes calculating a characteristic value from an output result when an electrical signal corresponding to the control value group is input to the semiconductor element. The first processing includes calculating a first function from history data including not less than one data set. The data set includes the control value group and a score based on the characteristic value. The design support device sets a new control value group.

Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

Abstract: Techniques described herein address these and other issues by utilizing two or more sensors to take temperature measurements from which a temperature-differential or instantaneous temperature rate-of-change, can be determined. In turn, this can be used to make a highly accurate model of the relationship between the temperature, temperature-differential, and clock circuitry frequency, to accurately estimate the frequency rate-of-change for frequency correction/compensation.

Abstract: A method (and system) includes receiving, at a computing device including a design tool application, design parameters indicative of a plurality of power supply loads to be powered. The method further includes generating power supply solutions that do not include multi-channel voltage regulators and generating power supply solutions that do include multi-channel voltage regulators. The method also includes ranking all power supply solutions and providing the ranked power supply solutions to a user.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

Abstract: A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.