Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.

Abstract: A quantum contextual measurement is generated from a quantum device capable of performing continuous time evolution, by generating a first measurement result and a second measurement result and combining the first measurement result and the second measurement result to generate the quantum contextual measurement. The first measurement result may be generated by initializing the quantum device to a first initial quantum state, applying a first continuous time evolution to the first initial state to generate a first evolved state, and measuring the first evolved state to generate the first measurement result. A similar process may be applied to generate a second evolved state which is at least approximately equal to the first evolved state, and then applying another continuous time evolution to the second evolved state to generate a third evolved state, and measuring the third evolved state to generate the second measurement result.

Abstract: A parameter candidate for a semiconductor element is provided. A data set of measurement data is provided to a parameter extraction portion, and a model parameter is extracted. A first netlist is provided to a circuit simulator, simulation is performed using the first netlist and the model parameter, and a first output result is output. A classification model learns the model parameter and the first output result and classifies the model parameter. A second netlist and a model parameter are provided to the circuit simulator. A variable to be adjusted is supplied to a neural network, an action value function is output, and the variable is updated. The circuit simulator performs simulation using the second netlist and the model parameter. When a second output result to be output does not satisfy conditions, a weight coefficient of the neural network is updated. When the second output result satisfies the conditions, the variable is judged to be the best candidate.

Abstract: While a qubit control system (e.g., a laser system) is in a first configuration, it causes a qubit state (as represented as a point on the surface of a Bloch sphere) of a quantum state carrier (QSC), e.g., an atom, to rotate in a first direction from an initial qubit state to a first configuration qubit state. While the qubit control system is in a second configuration, it causes the QSC state to rotate in a second direction opposite the first direction from the first configuration qubit state to a second configuration qubit state. The second configuration qubit state is read out as a |0 or |1. Repeating these actions results in a distribution of |0s and |1s that can be used to determine which of the two configurations results in higher Rabi frequencies. Iterating the above for other pairs of configurations can identify a configuration that delivers the most power to the QSC and thus yields the highest Rabi frequency.

Abstract: Aspects of the subject disclosure may include, for example, obtaining instructions for implementing a quantum algorithm adapted to obtain a computational result according to a quantum mechanical process. A sequence of quantum operations is generated according to the instructions for implementing the quantum algorithm, wherein the sequence of quantum operations is adapted to physically manipulate a plurality of quantum bits according to the quantum mechanical process. The sequence of quantum operations is provided to a geographically separated quantum central module, via a communication channel, the geographically separated quantum central module implements the quantum mechanical process to obtain a computational result. The computational result is received from the geographically separated quantum central module via the communication channel. Other embodiments are disclosed.

Abstract: A quantum bit control apparatus, including a control signal generator, optoelectronic detectors, a quantum chip, and a shielding apparatus, the optoelectronic detectors are disposed in the shielding apparatus, and an inner part of the shielding apparatus is in a vacuum state. The control signal generator is disposed in a first temperature area, and is configured to generate optical control signals and send the N optical control signals to the optoelectronic detectors. The optoelectronic detectors are disposed in a second temperature area having a temperature lower than of the first temperature area. The N optoelectronic detectors are configured to convert the received optical control signals into electronically controlled signals and send the electronically controlled signals to the quantum chip. The quantum chip is disposed in the second temperature area, and controls a quantum bit in the quantum chip based on the electronically controlled signals.

Abstract: A system receives a predictive model and receives one or more runtime constraints. The system generates a directed acyclic graph (DAG) of the predictive model indicating dependencies. The system compiles the predictive model into first instructions for a first processor based on the one or more runtime constraints and the DAG. The system packages first instructions, the one or more runtime constraints, and the DAG of the predictive model in a first binary. The system recompiles the predictive model into second instructions for a second processor based on the runtime constraints and the DAG stored in the first processor. The system packages the second instructions, the DAG, and the runtime constraints in a second binary.

Abstract: A quantum computer directs an amplitude of a qubit to be proportional to the value of a function g of N variables {right arrow over (xk)} by: (A) initializing M+1 qubits on the quantum computer, the M+1 qubits comprising: (1) a target qubit t having an amplitude of a reference state; and (2) a control register with M qubits {ql}; and (B) changing the value of the amplitude of the reference state on the target qubit t, the changing comprising: (B)(1) applying a sequence of SU(2) gates to the target qubit t, the sequence of SU(2) gates comprising M controlled quantum gates Gi and at least one rotation parameter, wherein at least one qubit of the control register acts as a control qubit for the controlled quantum gate Gi; and (B)(2) tuning the at least one rotation parameter until a halting criterion based on the amplitude of the reference state is satisfied.

Abstract: A device includes a first cell active area asymmetrically positioned in a first device column between a first barrier line and a second barrier line, a second cell active area asymmetrically positioned in a second device column between the first barrier line and a third barrier line, where the first cell has a first cell length in a first direction perpendicular to the first barrier line which is three times a second cell length in the first direction. The first cell active area and the second cell active area are a first distance from the first barrier line, and the first cell active area is a second distance from the second barrier line, and the second cell active area is the second distance away from the third barrier line.

Abstract: A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.

Abstract: Techniques and systems for generating constrained random stimuli during functional verification of a design under verification (DUV) are described. Some embodiments can compute an observed probability distribution for each variable in a set of variables based on at least a first random solution generated using a set of constraints that are defined over the set of variables. The embodiments can then compute a correction probability distribution for each variable in the set of variables based on the observed probability distribution and an intended probability distribution. Next, while generating at least a second random solution using the set of constraints, the embodiments can select a random value for a given variable in the set of variables based on the correction probability distribution for the given variable. The observed probability distribution can be continuously updated and stored as constrained random stimuli are generated.

Abstract: Installation of electrical systems can require a large amount of branch circuits that can lead to a labeling degeneracy that can require a customized on-site tagging step to identify each conductor to be installed, or cause technicians to install additional circuit housing runs to circumvent the degeneracy. Circuit grouping systems and methods, and circuit installation methods, are disclosed herein that prevent such inefficiencies.

Abstract: An illustrative system may comprise a plurality of distributed network nodes hosting a two-dimensional distributed digital ledger. The distributed digital ledger may have a plurality of chains of digital blocks in the two-dimensions, wherein each chain may be associated with a particular functionality (e.g., a first set of integrated circuit processes) and a corresponding level of security. For example, a first chain in the first direction may contain digital blocks containing code differentials of the hardware description language code forming the integrated circuit design. A second chain in a second direction may contain digital blocks containing simulation data records generated during the simulation of the integrated circuit design. The first chain and the second chain may be based upon different cryptographic protocols and therefore may be cryptographically separate from each other.

Abstract: Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.

Abstract: The present disclosure provides a method and an apparatus for testing a semiconductor device. The method includes providing an active area in an integrated circuit design layout; grouping the active area into a first region and a second region; calculating a first self-heating temperature of the first region of the active area; calculating a second self-heating temperature of the second region of the active area; and determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature.

Abstract: Various embodiments describe methods, systems, and devices for client-driven dynamic server-side configuration validation. Exemplary implementations may include validating client device configuration data, updating a client device shadow with the validated client device configuration data, in which the client device shadow includes a schema in a client device-agnostic language, and translating client device configuration data of the client device shadow from the client device-agnostic language to a client device-specific language. Also, receiving the client device configuration data from a computing device over a communication network, and sending the client device configuration data of the client device shadow in the client device-specific language to a client device via a communication network.

Abstract: An oscillator in which crosstalk can be reduced is provided. An oscillator includes a SQUID, a transmission line connected to the SQUID, a ground plane, and a first connection circuit disposed in a vicinity of a node of an electric field of a standing wave that is generated when the oscillator is oscillating, the first connection circuit connecting parts of the ground plane located on both sides of the transmission line to each other.

Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

Abstract: Aspects of the present disclosure address systems, methods, and a user interface for providing interactive skew group visualizations for integrated circuit (IC) design. The method includes causing display of a user interface that includes a display of a grouped view of a clock-tree including a plurality of skew group indicators. The method further includes receiving a user selection of a skew group indicator and updating the user interface to display a detailed view of the skew group including a graphical representation of each clock sink in the skew group and corresponding timing information. The method further includes receiving a second user selection of a first clock sink and in response, the display is updated to display an indicator of a physical location of the first clock sink within the clock tree.

Abstract: A system receives a predictive model and receives one or more runtime constraints. The system generates a directed acyclic graph (DAG) of the predictive model indicating dependencies. The system compiles the predictive model into first instructions for a first processor based on the one or more runtime constraints and the DAG. The system packages first instructions, the one or more runtime constraints, and the DAG of the predictive model in a first binary. The system recompiles the predictive model into second instructions for a second processor based on the runtime constraints and the DAG stored in the first processor. The system packages the second instructions, the DAG, and the runtime constraints in a second binary.

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.

Abstract: A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

Abstract: Provided is an image processing apparatus that includes an image processing section that executes filter processing using a filter coefficient. The filter coefficient is set at least on the basis of a detection result for details based on a first image and a detection result of detection of a disturbance performed on a second image.

Abstract: A product may be associated with a linked document, a link to which is included in a linking document. Associating the linked document with the product may include accessing document linkage data, identifying a relevant linkage record from the linkage data, using a linking document identifier determined from the relevant linkage record to access linking document information in respect of the linking document, processing the linking document information to identify a first product to which the first linking document relates, and associating the first product with the linked document.

Abstract: A method, system and product comprising: obtaining a directed acyclic graph representing a quantum circuit, the directed acyclic graph comprising a set of blocks and connections therebetween, wherein a connection between a first block and a second block indicates passing an output value of a qubit outputted by the first block to be an input value of a qubit manipulated by the second block; determining a Constraint Satisfaction Problem (CSP) based on the directed acyclic graph, wherein the CSP comprises one or more constraints based on the connections defined by the directed acyclic graph; automatically solving the CSP, wherein said automatically solving comprises selecting an implementation to each block that adheres to the one or more constraints; and synthesizing a gate-level representation of the quantum circuit based on the solution to the CSP.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: In order to provide processor elements and programmable devices, which have little restriction on logical block arrangement and wiring, and which can improve a degree of integration, processor element 1 includes: arithmetic units 11 that perform arithmetic processing on the basis of functions which have implemented instruction sets generated in accordance with programs; registers 12 that store arguments of the functions; bypass switches 13 of the arithmetic units 11; bypass switches 14 of the registers 12; a connection setting unit 16 that switches the connections of function units 20; a multiplexer 17 that switches the input to the connection setting unit 16; a demultiplexer 18 that switches the output destination of the output from the connection setting unit 16; and a selection unit 15 that switches, in accordance with a state, the bypass switches 13, 14, the connection setting unit 16, the multiplexer 17 and the demultiplexer 18.

Abstract: Installation of electrical systems can require a large amount of branch circuits that can lead to a labeling degeneracy that can require a customized on-site tagging step to identify each conductor to be installed, or cause technicians to install additional circuit housing runs to circumvent the degeneracy. Circuit grouping systems and methods, and circuit installation methods, are disclosed herein that prevent such inefficiencies.

Abstract: A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: An illustrative system may comprise a plurality of distributed network nodes hosting a two-dimensional distributed digital ledger. The distributed digital ledger may have a plurality of chains of digital blocks in the two-dimensions, wherein each chain may be associated with a particular functionality (e.g., a first set of integrated circuit processes) and a corresponding level of security. For example, a first chain in the first direction may contain digital blocks containing code differentials of the hardware description language code forming the integrated circuit design. A second chain in a second direction may contain digital blocks containing simulation data records generated during the simulation of the integrated circuit design. The first chain and the second chain may be based upon different cryptographic protocols and therefore may be cryptographically separate from each other.

Abstract: Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits. Alternatively or additionally, each network circuit of a plurality of network circuits in the reconfigurable hardware modeling device may comprise signal reduction circuitry configurable to perform the signal reduction function.

Abstract: A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

Abstract: Methods and apparatuses for designing quantum circuits include obtaining Pauli strings included in a qubit Hamiltonian. At least some of the strings are grouped, based at least partially on a judgment of whether Pauli strings are observables that are jointly measurable by entangled measurement, at least at some operators. A quantum circuit is designed based on a result obtained from the grouping.

Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

Abstract: An integrated circuit includes an intellectual property (IP) block including a plurality of standard cells. A first power gating cell supplies power to the IP block via a first power rail extending in a first horizontal direction. A first conductive line extends in a second horizontal direction perpendicular to the first horizontal direction in a first metal layer. A second power gating cell is arranged adjacent to the first power gating cell in the second horizontal direction to supply power to the IP block via a second power rail extending in the first horizontal direction. A second conductive line extends in the second horizontal direction in the first metal layer. The first conductive line is coupled with the second conductive line in the second horizontal direction.

Abstract: It is possible to comprehensively calculate a potential and a current of a transmission line in an electric circuit, a potential and a current of an element, and an electromagnetic field including noise generated from the electric circuit. A computer performs a circuit configuration inputting step of inputting a circuit configuration of a distributed constant circuit and a lumped constant circuit and an initial value of each variable, and a calculating step of obtaining a scalar potential and a current in a multi-conductor transmission line, a scalar potential and a voltage in an element, and an electromagnetic radiation amount by, under the circuit configuration and the initial value, solving a basic equation of a transmission theory using a boundary condition formula at x=0 and w which are the boundary between the distributed constant circuit and the lumped constant circuit.

Abstract: A method includes identifying a set of tests for a source code, analyzing the set of tests to identify overlapping blocks of the source code that are to be tested by each of the set of tests, merging a subset of the tests that include the overlapping blocks of the source code to create a merged test, and causing the merged test to be executed to test the source code. In an implementation, code coverage results are used when analyzing the set of tests to identify overlapping blocks of the source code.

Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.

Abstract: A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique.

Abstract: Systems and methods for entering and storing data. User input defining a data set is received. A data collection construct including a data entry user interface for inputting data in the data set is defined using the user input. A data storage construct including queries for retrieving the data is automatically defined based on the user input. Additional user input indicating modifications to the data set is received. The data collection construct, the data storage construct, and the queries are automatically updated based on the additional user input indicating modifications to the data set.

Abstract: A method for modeling glitch of a logic gate is provided. An input glitch with a glitch width is obtained from the logic gate. The glitch width is scaled by a first scaling factor when the glitch width is greater than or equal to a first threshold width. The glitch width is scaled by a second scaling factor when the glitch width is less than the first threshold width and greater than or equal to a second threshold width. An output glitch with the scaled glitch width is provided for the logic gate. The scaled glitch width is greater than 0. The first threshold width is greater than the second threshold width, and the second scaling factor is smaller than the first scaling factor.

Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

Abstract: Systems and methods are provided for causing display of a graphical user interface for designing at least one visualization, receiving data defining a first visualization control, receiving a least one data model defining at least one data source related to the first visualization control, and receiving at least one calculation module defining calculation details for the first visualization control. Further, the systems and methods are provided for generating an analytical instance for the at least one visualization comprising the first visualization control, the at least one data model, and the at least one calculation module, and uploading to a server system a specification associated with the analytical instance.

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.