Abstract: A method, computer program and associated apparatuses for metrology. The method includes determining whether a substrate or substrate portion is subject to a process effect. The method includes: obtaining inspection data including a plurality of sets of measurement data associated with a structure on the substrate or portion thereof (for example measurement pupils); and obtaining fingerprint data describing a spatial variation of a parameter of interest. An iterative mapping of the inspection data to the fingerprint data is performed. Whether the structure is subject to a process effect is based on a degree to which the iterative mapping converges on a solution.

Abstract: Novel tools and techniques are provided for implementing management of routing across multiple voice or data networks with separate routing masters. In various embodiments, in response to receiving a request to establish a call between a calling party in a first network and a called party in a second network, a computing system might receive a first set of network information from a first routing database(s) that is operated by a first service provider and a second set of network information from a second routing database(s) that is operated by a second service provider separate from the first service provider; might analyze the received first and second sets of network information to generate a unified routing model for optimizing routing of the call through the first and second networks; and might establish the call through a selected optimized route based on the generated unified routing model.

Abstract: In certain aspects, a memory device includes an array of memory cells. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. A redundant bank of the M redundant banks is located between two main banks of the N main banks or adjacent to one main bank of the N main banks.

Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

Abstract: A method for improving a process model for a patterning process, the method including obtaining a) a measured contour from an image capture device, and b) a simulated contour generated from a simulation of the process model. The method also includes aligning the measured contour with the simulated contour by determining an offset between the measured contour and the simulated contour. The process model is calibrated to reduce a difference, computed based on the determined offset, between the simulated contour and the measured contour.

Abstract: Disclosed herein are a method, a system, and a computer-readable storage-medium embodiments of automatic elastic CPU for a physical verification job. An embodiment includes generating multiple commands for a physical verification job of a design. The multiple commands are related by a dependency graph. The embodiment further includes allocating an initial amount of computing resources to execute the multiple commands, queuing a subset of the multiple commands for execution based on the dependency graph, adding an estimated amount of computing resources to the initial amount based on the number of the queued subset of commands and an estimated time to complete the queued subset of commands, and releasing a portion of the estimated amount of computing resources in response to the portion of the estimated amount of computing resources being idle for an amount of time greater than a target time.

Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.

Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, the slanted layout component having a side slanted from a base axis is detected. In one aspect, an offset angle of the side of the slanted layout component with respect to the base axis is determined. In one aspect, the slanted layout component is rotated according to the offset angle to obtain a rotated layout component. The rotated layout component may have a rotated side in parallel with or perpendicular to the base axis. In one aspect, layout verification can be performed on the rotated layout component with respect to the base axis.

Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: A method of determining a relationship between a stochastic variation of a characteristic of an aerial image or a resist image and one or more design variables, the method including: measuring values of the characteristic from a plurality of aerial images and/or resist images for each of a plurality of sets of values of the design variables; determining a value of the stochastic variation, for each of the plurality of sets of values of the design variables, from a distribution of the values of the characteristic for that set of values of the design variables; and determining the relationship by fitting one or more parameters from the values of the stochastic variation and the plurality of sets of values of the design variables.

Abstract: A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: Methods for compressing shape data for a set of electronic designs include inputting a set of shape data, where the shape data comprises mask designs. A convolutional autoencoder encodes the set of shape data, where the encoding compresses the set of shape data to produce a set of encoded shape data. The convolutional autoencoder is tuned for increased accuracy of the set of encoded shape data based on design rules for the set of shape data. The convolutional autoencoder comprises a set of parameters comprising weights, and the convolutional autoencoder has been trained to determine what information to keep based on the weights.

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Abstract: Computer-implemented systems and methods for improving construction of a mask layout block, for eliminating electromigration and self-heat violations during construction of a mask layout block, and for maintaining process design rules and layout connectivity during construction of a mask layout block are provided. At least one selected polygon is analyzed and a selected position of the selected polygon determined. The systems and methods obtain one or more electromigration rules or self-heat rules associated with the selected polygon. An information window with the one or more electromigration or self-heat rules and a violation marker associated with the selected position of the selected polygon are provided. The system determines if the selected position of the selected polygon or a length or width of the selected polygon violates an electromigration rule or self-heat rule.

Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

Abstract: A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.

Abstract: A process proximity correction method is performed by a process proximity correction computing device which performs a process proximity correction (PPC) through at least one of a plurality of processors. The process proximity correction method includes: converting a target layout including a plurality of patterns into an image, zooming-in or zooming-out the image at a plurality of magnifications to generate a plurality of input channels, receiving the plurality of input channels and performing machine learning to predict an after-cleaning image (ACI), comparing the predicted after-cleaning image with a target value to generate an after-cleaning image error, and adjusting the target layout on the basis of the after-cleaning image error.

Abstract: A method of fabricating a semiconductor device includes generating a mask based on second layout data obtained by applying an OPC model to first layout data and performing a semiconductor process using the mask on a substrate, obtaining a plurality of pattern images by selecting a plurality of sample patterns from the substrate, selecting sample images corresponding to the sample patterns from each of the first layout data, the second layout data, and simulation data obtained by performing a simulation based on the second layout data, generating a plurality of input images corresponding to the sample patterns by blending the sample images corresponding to the sample patterns, respectively, and generating an error prediction model for the OPC model by training a machine learning model using a data set including the input images and the pattern images.

Abstract: A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.

Abstract: A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A process of characterizing a process window of a patterning process, the process including: obtaining a set of inspection locations for a pattern, the pattern defining features to be applied to a substrate with a patterning process, the set of inspection locations corresponding to a set of the features, the set of features being selected from among the features according to sensitivity of the respective features to variation in one or more process characteristics of the patterning process; patterning one or more substrates under varying process characteristics of the patterning process; and determining, for each of the variations in the process characteristics, whether at least some of the set of features yielded unacceptable patterned structures on the one or more substrates at corresponding inspection locations.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Abstract: A method of designing an integrated circuit (IC) device includes identifying, using a processor, data corresponding to an IC manufacturing process. The designing also includes assigning, using the processor, the data to one or more design rule instruction macros. The designing also includes selecting, using the processor, one or more constraints to be applied to the one or more design rule instruction macros. The designing also includes executing, using the processor, the one or more design rule instruction macros to configure a design rule for the IC manufacturing process.

Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.

Abstract: Methods and systems for learnable defect detection for semiconductor applications are provided. One system includes a deep metric learning defect detection model configured for projecting a test image for a specimen and a corresponding reference image into latent space, determining a distance in the latent space between one or more different portions of the test image and corresponding portion(s) of the corresponding reference image, and detecting defects in the one or more different portions of the test image based on the determined distances. Another system includes a learnable low-rank reference image generator configured for removing noise from one or more test images for a specimen thereby generating one or more reference images corresponding to the one or more test images.

Abstract: An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

Abstract: A method performed by at least one processor includes the following steps. A layout of an integrated circuit (IC) is accessed, wherein the layout has at least one cell. A context group for the cell is determined based on a layout context of the cell, wherein the context group is associated with a timing table. A timing analysis is performed on the layout to determine whether the layout complies with a timing constraint rule according to the timing table. A system including one or more processors including instructions for implementing the method and a non-transitory computer readable storage medium including instructions for implementing the method are also provided.

Abstract: Disclosed are mask layout correction methods and a method for fabricating semiconductor devices. The mask layout correction method comprises performing a first optical proximity correction on an initial pattern layout. The step of performing the first optical proximity correction includes providing a target pattern of the initial pattern layout with control points based on a first model, obtaining a predicted contour of the initial pattern layout by performing a simulation, and obtaining an error between the target pattern and the predicted contour from the control points. The control points include first control points on an edge of the target pattern and second control points in an inside of the target pattern. The step of obtaining the error includes acquiring first error values from the first control points, providing weights to the first error values, and acquiring second error values from the second control points.

Abstract: A method for determining a correction to a patterning process. The method includes obtaining a plurality of qualities of the patterning process (e.g., a plurality of parameter maps, or one or more corrections) derived from metrology data and data of an apparatus used in the patterning process, selecting, by a hardware computer system, a representative quality from the plurality of qualities, and determining, by the hardware computer system, a correction to the patterning process based on the representative quality.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A machine learning device included in a life predicting device observes, as a state variable, life related data related to a life of a consumable component, creates a probability model of a service life for replacement of the consumable component on the basis of the life related data, and predicts, using the created probability model, the service life for replacement of the consumable component based on the life related data.

Abstract: A computer-implemented method manipulates a 3D object in a 3D scene of a computer-aided design system, by: (i) displaying a 3D object having a center of rotation in the 3D scene on a screen; (ii) displaying in the 3D scene a rotation manipulator (RM) having three areas (RA1, RA2, RA3) perpendicular to each other, and each area (RA1, RA2, RA3) corresponding to a rotation plane, and (iii) activating the rotation manipulator. The rotation manipulator (RM) follows the cursor (C) on the screen. The rotation manipulator is activated by locking its location on the screen on an initial press point (PP). One rotation plane is selected by displacing the cursor (C) to the area (RA1, RA2, RA3) corresponding to said plane. A rotation manipulation is performed according to the displacement of the cursor (C) on the screen.

Abstract: Systems and methods are disclosed for generating permit sets. A rules engine can traverse various requirements of a rules data structure in conjunction with rule settings that define permitting rules in effect for a particular jurisdiction to determine a value for each requirement. Document objects may then be created by combining project inputs with the determined values. A composing engine can receive the document objects and populate one or more page templates with the document objects to create a permit set.

Abstract: Method, apparatus, and computer program product are provided for retrieving analogues using topological knowledge representation (TKR). In some embodiments, a TKR input query is built and/or validated using a domain-specific knowledge base (KB). A search database containing candidate analogues and corresponding pre-built TKRs is then searched to retrieve at least one analogue of the TKR input query using statistical analysis. In some embodiments, a system may build the TKR input query based on a seismic dataset. For example, the system may receive a seismic dataset, segment the seismic dataset and classify each region using a computer vision (CV) database and the KB, and build the TKR input query based on the segmented and classified seismic dataset. In some embodiments, the TKR input query may be input and/or edited by a user. For example, the TKR input query may be input and/or edited by the user and validated using the KB.

Abstract: Novel tools and techniques are provided for implementing management of routing across multiple voice or data networks with separate routing masters. In various embodiments, in response to receiving a request to establish a call between a calling party in a first network and a called party in a second network, a computing system might receive a first set of network information from a first routing database(s) that is operated by a first service provider and a second set of network information from a second routing database(s) that is operated by a second service provider separate from the first service provider; might analyze the received first and second sets of network information to generate a unified routing model for optimizing routing of the call through the first and second networks; and might establish the call through a selected optimized route based on the generated unified routing model.

Abstract: The present invention refers to a method for performing an aerial image simulation of a photolithographic mask which comprises the following steps: (a) modifying an optical radiation distribution at a patterned surface of the photolithographic mask, depending on at least one first arrangement of pixels to be generated in the photolithographic mask; and (b) performing the aerial image simulation of the photolithographic mask by using the generated modified optical radiation distribution.

Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.

Abstract: A data-driven misregistration parameter configuration and measurement system and method including simulating a plurality of measurement simulations of at least one multilayered semiconductor device, selected from a batch of multilayered semiconductor devices intended to be identical, using sets of measurement parameter configurations, generating simulation data for the device, identifying recommended measurement parameter configurations selected from sets of measurement parameter configurations, providing a multilayered semiconductor device selected from the batch, providing the at least one recommended set of measurement parameter configurations to a misregistration metrology tool having multiple possible sets of measurement parameter configurations, measuring at least one multilayered semiconductor device, selected from the batch, using the recommended set, thereby generating measurement data for the device, thereafter identifying a final recommended set of measurement parameter configurations and measuring

Abstract: A method of determining a failure model of a resist process of a patterning process. The method includes obtaining (i) measured data of a pattern failure (e.g., failure rate) related to a feature printed on a substrate based on a range of values of dose, and (ii) image intensity values for the feature via simulating a process model using the range of the dose values; and determining, via fitting the measured data of the pattern failure to a product of the dose values and the image intensity values, a failure model to model a stochastic behavior of spatial fluctuations in the resist and optionally predict failure of the feature (e.g., hole closing).

Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the water in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Abstract: The fully-automatic closed-loop detection method includes: comparing a SCD file of a to-be-tested substation with a device-type data template file, so as to determine whether configuration information about the to-be-tested substation is correct; when the configuration information about the to-be-tested substation is correct, parsing the SCD file of the to-be-tested substation and generating a SSD topological diagram of the to-be-tested substation; and acquiring a testing item from a predetermined testing item library in accordance with the SSD topological diagram of the to-be-tested substation, generating a testing scheme for the to-be-tested substation, performing a testing operation and outputting a testing result.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

Abstract: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.