Defect (including Design Rule Checking) Patents (Class 716/52)
  • Patent number: 10817635
    Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken-Hsien Hsieh, Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang
  • Patent number: 10810348
    Abstract: In an approach to integrated circuit track coloring, system ground rules, minimum wire width, minimum spacing, and a set of one or more colors, are received. A track layout is created. A first color is assigned to each power track. A second color is assigned to each wide track. One or more legal colors are determined for each minimum width track. A legal color is assigned to each minimum width track.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventor: Laura R. Darden
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10796065
    Abstract: Defects can be identified using a hybrid design layout that includes a printable layer and a non-printed layer. The hybrid design layout can be generated by incorporating at least a portion of the non-printable layer layout with the printable layer layout. Defects can be identified using optical or scanning electron beam images.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 6, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Allen Park, Ankit Jain
  • Patent number: 10789408
    Abstract: Systems and methods for generating coloring constraints for layout design data. A method includes receiving or determining a constraint rule, by a computer system, for a constraint between geometric elements in the layout design data. The method includes generating constraints according to the one or more constraint rules. The method includes creating one or more groups according to the generated constraints. The method includes storing the generated constraints and the one or more groups in a design layout database. Also systems and methods for identifying elements in a design layout having multiple levels of hierarchical cells.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 29, 2020
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G. Pikus
  • Patent number: 10782616
    Abstract: A method including performing a first simulation for each of a plurality of different metrology target measurement recipes using a first model, selecting a first group of metrology target measurement recipes from the plurality of metrology target measurement recipes, the first group of metrology target measurement recipes satisfying a first rule, performing a second simulation for each of the metrology target measurement recipes from the first group using a second model, and selecting a second group of metrology target measurement recipes from the first group, the second group of metrology target measurement recipes satisfying a second rule, the first model being less accurate or faster than the second model and/or the first rule being less restrictive than the second rule.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: September 22, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Daimian Wang, Shengrui Zhang, Chi-Hsiang Fan
  • Patent number: 10776216
    Abstract: A system and method for a tiered cloud storage for different availability and performance requirements includes a gateway, a block store configured to cache data, and an object store configured to persistently store data. The gateway, the block store, and the object store are in a compute zone. The gateway may receive from a user application a file access call and process the file access call. The gateway may also send the file access call to the block store. Then, the gateway may determine to store data in the object store and flush the data from the block store to the object store.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 15, 2020
    Assignee: Red Hat, Inc.
    Inventors: Huamin Chen, Jay Vyas
  • Patent number: 10769334
    Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bryan G. Hickerson, Mohamed Baker Alawieh, Brian L. Kozitza, John R. Reysa, Erica Stuecheli
  • Patent number: 10770304
    Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
  • Patent number: 10762621
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Patent number: 10739688
    Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: August 11, 2020
    Assignee: Qoniac GmbH
    Inventor: Boris Habets
  • Patent number: 10740236
    Abstract: A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Vikas Sinha, Eric C. Quinnell, Jyotsna Kartha
  • Patent number: 10726186
    Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Tae Kim, Jung-Ho Do, Tae-Joong Song, Doo-Hee Cho, Seung-Young Lee
  • Patent number: 10713411
    Abstract: The present disclosure describes apparatuses and methods for correcting design rule violations. The apparatuses and methods, applicable to the design of features to be rendered onto a photolithography mask used in a semiconductor wafer-manufacturing environment, rely on a design-rule checker working in combination with a list of one or more solutions. The combination of the design-rule checker working with the list of one or more solutions provides for efficient and effective identification and resolution of design rule violations.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 14, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Runzi Chang
  • Patent number: 10713771
    Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 14, 2020
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
  • Patent number: 10706200
    Abstract: A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Patent number: 10699971
    Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 30, 2020
    Assignee: Qoniac GmbH
    Inventors: Boris Habets, Martin Roessiger, Stefan Buhl
  • Patent number: 10699055
    Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Patent number: 10691016
    Abstract: An etching effect prediction method includes determining a sample area of a mask pattern in which etch bias is to be predicted, determining input parameters indicating physical characteristics affecting an etching process undertaken in the sample area, comparing an output value obtained by inputting the input parameters to an artificial neural network, to a measured value of the etch bias that occurred in the sample area, and operating the artificial neural network until a difference between the output value and the measured value is equal to or less than a predetermined reference value.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronincs Co., Ltd.
    Inventor: Seong Bo Shim
  • Patent number: 10691863
    Abstract: A method including modeling high resolution patterning error information of a patterning process involving a patterning device in a patterning system using an error mathematical model, modeling a correction of the patterning error that can be made by a patterning device modification tool using a correction mathematical model, the correction mathematical model having substantially the same resolution as the error mathematical model, and determining modification information for modifying the patterning device using the patterning device modification tool by applying the correction mathematical model to the patterning error information modeled by the error mathematical model.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 23, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Peter Ten Berge, Everhardus Cornelis Mos, Richard Johannes Franciscus Van Haren, Peter Hanzen Wardenier, Erik Jensen
  • Patent number: 10678150
    Abstract: Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 9, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Uwe Hollerbach, Thomas L. Laidig
  • Patent number: 10656530
    Abstract: Extracting shapes from a pixelated SRAF bitmap image of pixels for mask making is disclosed. A method includes receiving the pixelated SRAF bitmap image of pixels, each pixel having a respective brightness value; selecting a ridge point in the pixelated SRAF bitmap image; for each pixel of at least some of the pixels, determining a respective arrival time at the pixel; and determining a mask shape using the arrival times of the at least some of the pixels. The ridge point is one of the pixels and is selected based on the respective brightness value of the one of the pixels. An arrival time is based on a respective brightness value of the pixel and a Mask Rule Check (MRC) rule.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 19, 2020
    Assignee: ASML US, LLC
    Inventors: Jihui Huang, Ke Zhao, Jiangwei Li
  • Patent number: 10642950
    Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Romain Lallement, Stuart A. Sieg
  • Patent number: 10635004
    Abstract: A method including obtaining a fit of data for overlay of a metrology target for a patterning process as a function of a stack difference parameter of the metrology target; and using, by a hardware computer, a slope of the fit (i) to differentiate a metrology target measurement recipe from another metrology target measurement recipe, or (ii) calculate a corrected value of overlay, or (iii) to indicate that an overlay measurement value obtained using the metrology target should be used, or not be used, to configure or modify an aspect of the patterning process, or (iv) any combination selected from (i)-(iii).
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 28, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Aiqin Jiang, Arie Jeffrey Den Boef, Kaustuve Bhattacharyya, Hans Van Der Laan, Bart Visser, Martin Jacobus Johan Jak
  • Patent number: 10635095
    Abstract: The example systems, methods, and devices disclosed herein generally relate to generating create a supervised failure model for assets in the given fleet that is configured to receive operating data as inputs and output a prediction as to the occurrence of a given failure type at the asset. In some instances, a data analytics platform may create and use an unsupervised failure model for a subset of the assets, use the respective unsupervised failure models to detect a set of anomalies that are each suggestive of a prior failure occurrence, from the set of anomalies, identify a subset of anomalies that are each suggest of a prior failure occurrence of the given failure type, and create the supervised failure model using failure data for the identified subset of anomalies.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 28, 2020
    Assignee: Uptake Technologies, Inc.
    Inventors: James Herzog, Benedict Augustine, Brian Burns, Eric Hall, Tuo Li
  • Patent number: 10635773
    Abstract: The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Myung-Chul Kim, Paul G. Villarrubia, Shyam Ramji, Gi-Joon Nam, Benjamin Neil Trombley
  • Patent number: 10628549
    Abstract: A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L1) comprising one or more polygon shapes (P1) defined by a plurality of polygon parameters (W1,H1). Design rules (R1,R2) are received comprising inequality constraints (C) on the polygon parameters (W1,H1). A second layout (L2) is calculated by applying a random change (?W12) of value to at least one of the polygon parameters (W1) of the first layout (L1). A third layout (L3) is calculated by varying values of the polygon parameters (W1,H1) of the second layout (L2) until a respective slack (S1,S2) of the polygon parameters (W1,H1) with respect to one or more of the parameter boundaries (B1,B2) defined by the constraints is minimized. The third layout (L3) may be stored as candidate test layout.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 21, 2020
    Assignee: SAGE DESIGN AUTOMATION LTD
    Inventor: Martinus Maria Berkens
  • Patent number: 10621295
    Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinning Liu, Jing Sha, Robert Wong, Dongbing Shao
  • Patent number: 10599046
    Abstract: A method for determining whether to order a mask structure using a processor may include acquiring a simulation result of an EUV pattern layout, determining a correlation parameter (CP), generating a predicted wafer process window, and determining the mask structure is suitable for ordering based on the CP and the predicted wafer process window. The processor may determine the CP based on a weighting value and a simulated depth of focus (DOF), a simulated energy latitude (EL), and simulated line-LER area and LER-width parameters in the simulation result. The CP may indicate a correlation between the simulation result of the EUV pattern layout and an actual wafer result of the EUV pattern layout. The predicted wafer process window may be generated using the processor based on the CP. The predicted wafer process window may indicate whether the actual wafer result of the EUV pattern layout will include a patterning defect.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seongjong Kim
  • Patent number: 10592632
    Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 17, 2020
    Assignee: Imec vzw
    Inventors: Ryan Ryoung han Kim, Jae Uk Lee
  • Patent number: 10592627
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Patent number: 10585346
    Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 10, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
  • Patent number: 10579772
    Abstract: A computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 3, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Christophe David Fouquet, Bernardo Kastrup, Arie Jeffrey Den Boef, Johannes Catharinus Hubertus Mulkens, James Benedict Kavanagh, James Patrick Koonmen, Neal Patrick Callan
  • Patent number: 10564214
    Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carole D. Graas, Nazmul Habib, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu, Emmanuel Yashchin
  • Patent number: 10545411
    Abstract: A method of determining a relationship between a stochastic variation of a characteristic of an aerial image or a resist image and one or more design variables, the method including: measuring values of the characteristic from a plurality of aerial images and/or resist images for each of a plurality of sets of values of the one or more design variables; determining a value of the stochastic variation, for each of the plurality of sets of values of the one or more design variables, from a distribution of the values of the characteristic for that set of values of the one or more design variables; and determining the relationship by fitting one or more parameters from the values of the stochastic variation and the plurality of sets of values of the one or more design variables.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 28, 2020
    Assignee: ASML Netherlands, B.V.
    Inventor: Steven George Hansen
  • Patent number: 10539865
    Abstract: A method is provided for determining an OPC model comprising: recording an aerial image by use of a mask inspection microscope, wherein the aerial image comprises at least one segment of a mask; simulating a plurality of aerial images which comprise at least the segment, proceeding from a mask design and from predefined parameters of an optical model which is part of the OPC model, wherein the parameters differ for each of the simulated aerial images of the plurality of aerial images; determining differences between the measured aerial image and the simulated aerial images; determining those parameters for which the differences between simulated aerial image and measured aerial image are the least. In addition, a mask inspection microscope for carrying out the method is provided.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Holger Seitz, Thomas Thaler, Ute Buttgereit, Thomas Trautzsch
  • Patent number: 10539881
    Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of patterned structures. The method also includes training, utilizing physical design layout patterns containing hotspots, a first neural network model configured to generate synthetic physical design layout patterns, and training, utilizing physical design layout patterns that do and do not contain hotspots, a second neural network model configured to classify whether physical design layout patterns contain hotspots. The method further includes generating synthetic physical design layout patterns containing hotspots by utilizing the trained first neural network model to generate synthetic physical design layout patterns and utilizing the trained second neural network model to select the synthetic physical design layout patterns containing hotspots.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Dongbing Shao, Martin Burkhardt, Sean Burns
  • Patent number: 10522328
    Abstract: A method for transferring a pattern onto a substrate by direct writing by means of a particle or photon beam comprises: a step of producing a dose map, associating a dose to elementary shapes of the pattern; and a step of exposing the substrate according to the pattern with a spatially-dependent emitted dose depending on the dose map; wherein the step of producing a dose map includes: computing at least first and second metrics of the pattern for each of the elementary shapes, the first metric representative of features of the pattern within a first range from the elementary shape and the second metric representative of features of the pattern within a second range, larger than the first range, from the elementary shape; and determining the emitted dose associated to each of the elementary shapes of the pattern as a function of the metrics. A computer program product is provided for carrying out such a method or at least the step of producing a dose map.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: December 31, 2019
    Assignee: ASELTA NANOGRAPHICS
    Inventors: Mohamed Saib, Patrick Schiavone, Thiago Figueiro
  • Patent number: 10496783
    Abstract: Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing. A circuit design is analyzed to identity circuit components of interest. Reference layout patterns that are associated with the circuit components of interest are extracted from a layout design based on the association of circuit components of the circuit design with geometric elements of the layout design. Pattern matching is performed to identify layout patterns that match the reference layout patterns. The identified layout patterns are then processed.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 3, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Sherif Hany Riad Mohammed Mousa, Jonathan James Muirhead, Alex Joseph Pearson, William Matthew Hogan
  • Patent number: 10452793
    Abstract: In one example, a method for evaluating a system includes obtaining a model of the system that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. In one embodiment, obtaining the model involves constructing a new model; however, in other embodiments, obtaining the model involves accepting or retrieving a pre-constructed model is input. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the model.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Yefim Shuf, Jonathan Sloan
  • Patent number: 10439912
    Abstract: Systems and methods are described herein are directed to determining optimal operating set points in sync with dynamic demand responsive to time-varying events in a data center. The method includes establishing, by a matrix module executing on a computing device, a data matrix of a first set of critical data based on resources in the data center representing dynamic demand, the dynamic demand responsive to the time-varying events in the data center. A decomposition module can generate new critical data based in part on the first set of critical data. A prediction module can determine optimal operating set points using the new critical data. The optimal operating set points for the resources can be transmitted by a communications module to a data center orchestration unit such as a building management module.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 8, 2019
    Assignee: AdeptDC Co.
    Inventors: Rajat Ghosh, Yogendra Kumar Joshi
  • Patent number: 10409947
    Abstract: According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: David A. Petermann, Andrew P. Hoover, Chandrakanth Ramesh
  • Patent number: 10394115
    Abstract: A method for verifying mask data in a computing device includes receiving layout data, receiving mask data, determining an interaction number between a pattern corresponding to the layout data and a pattern corresponding to the mask data, and detecting an error of the mask data based on the interaction number.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kil Yun, Sunghoon Kim, Jae-Eun Lee, Hyangja Yang
  • Patent number: 10395002
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 10395361
    Abstract: Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire a plurality of images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field is recovered for each of the pattern areas of the test reticle based on the acquired images from each pattern area of the test reticle. The recovered reticle near field is then used to determine whether the test reticle or another reticle will likely result in unstable wafer pattern or a defective wafer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 27, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Abdurrahman Sezginer, Mohammad Mehdi Daneshpanah
  • Patent number: 10394116
    Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
  • Patent number: 10380508
    Abstract: In one aspect there is provided a method. The method may include generating a graphical representation of a decision logic underlying a solution, the graphical representation having a plurality of nodes. A component archetype can be identified. The identified component archetype can support generating a function implementing one of the plurality of nodes in the graphical representation of the solution. An instance of the component can be generated based at least on the component archetype. The function can be generated by invoking the instance of the component. The generated function can be hosted by the instance of the component. Alternately and/or additionally, the generation function can be copied into one or more separate execution environments. Systems and articles of manufacture, including computer program products, are also provided.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 13, 2019
    Assignee: FAIR ISAAC CORPORATION
    Inventors: Joshua Prismon, Andrei Palskoi, Andrew K. Holland, Fernando Felipe Campos Donati Jorge
  • Patent number: 10372037
    Abstract: A computer-implemented method for constructing a design characterized by a double patterning layer is presented. The method includes receiving the design in a memory of the computer when the computer is invoked to construct the design. The method further includes generating, using the computer, a multitude of fill shapes along a multitude of tracks associated with a multitude of net shapes. The multitude of fill shapes and the multitude of net shapes are decomposable into two colors in accordance with a spacing constraint of the double patterning layer.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 6, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Himanshu Sharma, Byungwook Kim, Virender Kashyap, Abhishek Khandelwal
  • Patent number: 10372862
    Abstract: A new approach is proposed to support layout objects selection and replication via a graphic-based layout editing tool running on a host. Specifically, the graphic-based layout editing tool presents a plurality of layout objects in a layout on a display of the host and enables a user to directionally and continuously move a cursor across the layout along a single line, wherein the single line intersects with and selects a starting group of one or more layout objects. The graphic-based layout editing tool then retrieves metadata and/or design rules associated with the starting group selected layout objects and to create an expanded group of layout objects by replicating and including one or more of the layout objects in the starting group selected layout objects. The graphic-based layout editing tool then presents the expanded group of layout objects on the display following the layout objects replication operation.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 6, 2019
    Assignee: Skillcad, Inc.
    Inventor: Pengwei Qian
  • Patent number: 10362623
    Abstract: An apparatus and a method. The apparatus includes a first subscriber identity module (SIM); a second SIM; a dual SIM resource controller (DSRC) connected to the first SIM and the second SIM; and a radio frequency (RF) communication entity connected to the DSRC, wherein the DSRC performs one of scheduling a first paging preparation period of the first SIM prior to a second paging preparation period of the second SIM and re-attempting by the first SIM an RF request for the RF communication entity after an initial RF request for the RF communication entity is not granted.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Yangwen Liang, Fangming He, Srinivas Gururaja, Tariq Al-Khasib