Abstract: Methods for reticle enhancement technology include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array (FSA). The FSA is an array of sampled values of the smooth function, which is a continuous differentiable function. Methods also include providing a continuous tone mask (CTM), wherein the CTM is used to produce the predicted wafer pattern, the predicted wafer pattern spanning an entire design area.

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

Abstract: The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

Abstract: To support different timestamp formats, for example, for different network protocols, an integrated circuit device is provided with a memory that is programmed with multiple instruction sets associated with multiple timestamp formats. Each of the instruction sets contains instructions to generate a timestamp according to a corresponding timestamp format. A compute circuit can generate a formatted timestamp by using a base timestamp input and executing an instruction set selected from the multiple instruction sets stored in the memory.

Abstract: Enhanced push pull driving waveforms for driving a four particle electrophoretic medium including four different types of particles, for example a set of scattering particles and three sets of subtractive particles. Methods for identifying a preferred waveform for a target color state when using a voltage driver having at least five different voltage levels.

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

Abstract: Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

Abstract: An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.

Abstract: Methods and systems for detecting defects on a mask are provided. One method includes generating a database reference image for a multi-die mask by simulation and detecting first defects on the mask by comparing the database reference image to images of the mask generated by an imaging subsystem for a first of the multiple dies. The method also includes generating a die reference image for the first of the multiple dies by applying one or more parameters of the imaging subsystem learned by generating the database reference image to the images generated by the imaging subsystem of one or more of the multiple dies other than the first multiple die. In addition, the method includes detecting second defects on the mask by comparing the die reference image to the images of the mask generated by the imaging subsystem for the first of the multiple dies.

Abstract: A method for determining a deformation of a resist in a patterning process. The method involves obtaining a resist deformation model of a resist having a pattern, the resist deformation model configured to simulate a fluid flow of the resist due to capillary forces acting on a contour of at least one feature of the pattern; and determining, via the resist deformation model, a deformation of a resist pattern to be developed based on an input pattern to the resist deformation model.

Abstract: A layout geometry of a lithographic mask is received. The layout geometry is partitioned into feature images, for example as selected from a library. The library contains predefined feature images and their corresponding precalculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the lithographic mask illuminated by the source illumination.

Abstract: A method and a system for correcting lithography process hotspots based on stress damping adjustment are provided. The method includes: acquiring a mark hotspot of a mask pattern; forming N annuli centered on the mark hotspot from inner to outer on a mask; moving vertexes of the mask pattern located in each annulus by a specific distance in a direction deviating from the mark hotspot and connecting the moved vertexes according to an original connection relationship to acquire an updated layout; verifying electrical characteristics of the updated layout, determining whether a deviation of the electrical characteristics of the updated layout is within a tolerable range, and performing geometric correction to compensate for a deviation of electrical parameters if no is determined and then ending correction, or ending the correction if yes is determined.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: A method, a non-transitory computer readable medium, and a system for evaluating an inspection algorithm for inspecting a semiconductor specimen.

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

Abstract: Enhanced push pull driving waveforms for driving a four particle electrophoretic medium including four different types of particles, for example a set of scattering particles and three sets of subtractive particles. Methods for identifying a preferred waveform for a target color state when using a voltage driver having at least five different voltage levels.

Abstract: Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

Abstract: Testcase recommendations are generated for a testcase creator application by training a learning function using metadata of previously generated testcases by parsing the metadata into steptasks, and providing the parsed metadata to the learning function to enable the learning function to determine relationships between the steptasks of the previously generated testcases, and using, by the testcase creator application, the trained learning function to obtain a predicted subsequent steptask for a given type of testcase to be generated. Each steptask describes one of the steps of the testcase using a concatenation of a step number of the one of the steps of the testcase, a module and a submodule to be used to perform of the one of the steps of the testcase, and a function to be performed at the one of the steps of the testcase.

Abstract: A method for determining an etch profile is described. The method includes determining a masking layer profile. Loading information can be determined. The loading information indicates dependence of an etch rate for the masking layer profile on a quantity and pattern of material being etched. Flux information can be determined. The flux information indicates dependence of the etch rate on an intensity and a spread angle of radiation incident on the masking layer profile. Re-deposition information can be determined. The re-deposition information indicates dependence of the etch rate on an amount of material removed from the masking layer profile that is re-deposited back on the masking layer profile. An output etch profile for the layer of the wafer is determined based on the loading information, the flux information, and/or the re-deposition information.

Abstract: A method of making a mask includes computing a mask volume correction matrix for a given mask layout to be used to perform a lithography process. The mask volume correction matrix represents a diffraction field for a predetermined thickness of a material of the mask. A simulated mask pattern is computed by applying the mask volume correction matrix to the given mask layout. The simulated mask pattern is provided to a mask making tool.

Abstract: A method for determining a metric of a feature on a substrate obtained by a semiconductor manufacturing process involving a lithographic process, the method including: obtaining an image of at least part of the substrate, wherein the image includes at least the feature; determining a contour of the feature from the image; determining a plurality of segments of the contour; determining respective weights for each of the plurality of segments; determining, for each of the segments, an image-related metric; and determining the metric of the feature in dependence on the weights and the calculated image-related metric of each of the segments.

Abstract: A three-dimensional mask model that provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.

Abstract: A computer-implemented method and an electronic device for detecting, in an electrical circuit with electrical components (Mg) subject to variations (?) of their model parameters (xj), those components (Mg*) the model parameter variations (?) of which have the strongest influence on a performance (yn) of the circuit, comprising: providing a topology (Q) of the circuit and the model parameters (xj) of all components (Mg) therein; determining, therefrom, topological patterns (Pk) of interconnected components (Mg); generating variation samples (vn), each comprising a different set of candidate variations (x?j) of the model parameters (xj); calculating, for each variation sample (vn), the circuit's performance (yn) and a deviation from a standard performance and forming a deviation vector (yD) therefrom; and using the variation samples (vn), the deviation vector (yD) and the topological patterns (Pk) in a regression model for detecting the most influential components (Mg*).

Abstract: A method of determining the position of a first edge of a pattern in a mask used in fabricating an integrated circuit in which the first edge corresponds to a second edge associated with the pattern of a layout of the integrated circuit, includes, in part, dividing the edge into a multitude of segments, assigning a variable to each segment, applying a non-linear optimization algorithm to a current location of the first edge to determine an updated position of the first edge, determining a difference between the position of the second edge and a third edge corresponding to the updated position of the first edge and obtained by computer simulation of the mask pattern providing a model of the layout pattern when formed on a semiconductor wafer, and repeating the applying and the determining steps iteratively until the difference is smaller than a threshold value.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: Provided are an image processing apparatus, an image processing method, and a storage medium that can determine an anomaly while reducing influence of an individual difference of images. The image processing apparatus includes: a first generation unit that generates a first estimation image including at least a predetermined region of an inspection target by using a part of an inspection image including the inspection target; a second generation unit that estimates a difference between the first estimation image and the inspection image to generate a second estimation image by using the part of the inspection image; a comparison unit that compares the first estimation image with the inspection image; and an output unit that outputs a comparison result obtained by the comparison unit, and the comparison unit compares a difference between the first estimation image and the inspection image with the second estimation image.

Abstract: In a first aspect, the present disclosure relates to a method for designing a pattern of a stress relief layer for a flat device to be transformed into a shape-retaining non-flat device by deformation of the flat device. The flat device (and thus also the non-flat device) may comprise at least two components and at least one electrical interconnection between two components. In a second aspect, the present disclosure is related to a method of manufacturing a shape-retaining non-flat device by deformation of a flat device, wherein the flat device is attached to a patterned stress relief layer designed in accordance with the first aspect of the present disclosure. In preferred embodiments, the stress relief layer is a thermoplastic layer or a layer comprising a thermoplastic material and deformation of the flat device comprises deformation by a thermoforming process, after attachment of the flat device to the stress relief layer.

Abstract: Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.

Abstract: In some embodiments, a method of ensuring fabricability of a segmented design for a physical device to be fabricated by a fabrication system is provided. A proposed segmented design is searched for forbidden patterns in a set of forbidden patterns. Segments from the proposed segmented design that appear in forbidden patterns are added to a set of unfabricable segments. A material indicated by at least one unfabricable segment from the set of unfabricable segments is changed to create an updated segmented design, and the updated segmented design is searched for the forbidden patterns in the set of forbidden patterns. In response to determining that the updated segmented design includes at least one forbidden pattern, the adding, changing, and searching actions are repeated. In response to determining that the updated segmented design does not include any forbidden patterns, an indication is generated that the updated segmented design is fabricable.

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

Abstract: A system and method for generating a computer-based united cellular lattice structure includes dividing a part volume into a number of adjacent subvolumes each having a side combination corresponding to a number and orientation of adjoining sides and non-adjoining sides. A modified lattice cell may be generated from a base lattice cell for each side combination of the subvolumes such that each modified lattice cell has face surfaces on faces thereof corresponding to non-adjoining sides and does not have face surfaces on faces thereof corresponding to adjoining sides. Copies of the modified lattice cells may then be generated and inserted into corresponding subvolumes such that the faces of the modified lattice cell copies having face surfaces are positioned along non-adjoining sides of the subvolumes and faces of the modified lattice cell copies not having face surfaces are positioned along adjoining sides of the subvolumes.

Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.

Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.

Abstract: A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: Embodiments provide for a processor including logic to accelerate convolutional neural network processing, the processor including first logic to apply a convolutional layer to an image to generate a first convolution result and second logic to apply a look-up convolutional layer to the first convolution result to generate a second convolution result, the second convolution result associated with a location of the first convolution result within a global filter kernel.

Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured for measuring a property of a substrate. The method includes: determining a quality parameter for a plurality of substrates; determining measurement parameters for the plurality of substrates obtained using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameters; and determining the one or more optimized values of the operational parameter based on the comparing.

Abstract: A method including: simulating an image or characteristics thereof, using characteristics of a design layout and of a patterning process, determining deviations between the image or characteristics thereof and the design layout or characteristics thereof; aligning a metrology image obtained from a patterned substrate and the design layout based on the deviations, wherein the patterned substrate includes a pattern produced from the design layout using the patterning process; and determining a parameter of a patterned substrate from the metrology image aligned with the design layout.

Abstract: A method including: obtaining a thin-mask transmission function of a patterning device and a M3D model for a lithographic process, wherein the thin-mask transmission function represents a continuous transmission mask and the M3D model at least represents a portion of M3D attributable to multiple edges of structures on the patterning device; determining a M3D mask transmission function of the patterning device by using the thin-mask transmission function and the M3D model; and determining an aerial image produced by the patterning device and the lithographic process, by using the M3D mask transmission function.

Abstract: System and methods for an edge-based camera are disclosed. Semiconductor layout designs are a representation of an integrated circuit that are used to manufacture the integrated circuit. Parts of the layout design, such as points of Interest (POIs), may be subject to analysis with regard to a downstream application, such as hotspot detection. Unlike pixel-based characterizations, POIs are characterized using topological features indicative of quantized values and dimensional features indicative of analog values. For example, an edge may be characterized using a set of relations, which characterizes corners and polygons (including the polygon on which the POI resides and external polygons). In turn, the set of relations may be used to define image representations, including images in different directions relative to the POI (including cardinal and ordinal image). In this way, the topological/dimensional characterization of the POI may be used to analyze the POI in the layout design.

Abstract: Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

Abstract: The present disclosure provides a pattern density analysis method for analyzing a local pattern density of a layout, the method comprising: obtaining a pattern attribute of each layout pattern located on a layout region to be analyzed; setting, for each layout pattern, a relevant window for the layout pattern based on the corresponding pattern attribute; calculating the pattern density of each relevant window; and selecting the maximum value of the pattern densities of the relevant windows as the maximum local pattern density of the layout, and selecting the minimum value of the pattern densities of the relevant windows as the minimum local pattern density of the layout.

Abstract: Aspects of the disclosed technology relate to techniques for achieving optical proximity correction cross-tile consistency. A layout design is divided into a plurality of regions. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design. Based on the modified layout design and the layout pattern surrounding each of the edge fragments in the modified layout design, a final modified layout design is generated such that the edge fragments in different regions in the plurality of regions in the final modified layout design having the same layout pattern have a same edge adjustment value with respect to the layout design.

Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., to account for chamber-to-chamber variability) using machine learning techniques.

Abstract: A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.

Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-tone mask with a plurality of mask tones is described. The method generates a transmission function matrix based on a setting of the multi-tone mask. The method applies the transmission function matrix to transform a formula for calculating light intensity from Abbe's form to Hopkins' form while maintaining the accuracy of Abbe's form. The method then computes the light intensity using the transformed formula.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.