Abstract: The present invention discloses a system and method for performing interoperability testing. The method comprises sending a command from a server module to a client module, receiving the command at an application under test module via a shared directory module between the client module and the application under test module, executing a test at the application under test module based on the received command, and sending results of the test from the application under test module to the server module via the shared directory module and the client module, wherein the test is executed, and the results of the interoperability of the application between the client module and server module are sent, in a real-time, low-intrusive, supply chain setting.

Abstract: The present invention provides a method and system for eliminating redundant execution sequences that appear in workloads during workload simulation on an e-business application server. The invention eliminates redundancy by creating command patterns for commands that recur. This use of the command patterns permit execution of commands without having to rewrite the software code necessary for implementing the command every time there is a necessity to use the command in a workload. By building a reference workload and cloning the command patterns for each workload, redundancy can be eliminated among the workloads.

Abstract: Method and apparatus for providing a user interface application programming interface (API) for providing extended access to the database by third-party and user software products. In accordance with one embodiment, a method for accessing a business database includes instantiating a company object as an instance of a company class conforming to a component object model standard, setting a server property of the company object to a database server name, setting a company database name property of the company object to the name of a company, setting a user name property of the company object to the name of a user, setting a password property of the company object to a password of the user, setting a language property of the company object to a desired language of the user; and invoking a connect method within the company object, the connect method opening a software connection to a database identified by the company database name property.

Abstract: A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.

Abstract: An apparatus and method for converting an instruction and data trace to an executable program are provided. The apparatus and method are used to convert an instruction and data trace to an executable binary program that may then be used on a new computer system such that the simulations and the final computer both have similar run characteristics for a true comparison. The apparatus and method traverse a linear sequence of trace instructions to replace register names with unique labels and propagate these unique labels through the trace instructions. Thereafter, the trace instructions are traversed in a reverse direction to calculate register values based on the value of conditional branch registers. The resulting register values and corresponding memory addresses are then assembled into an executable program.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: In a software debugging apparatus, dump information formed by a hardware simulator is acquired and analyzed. When displaying the result of the analysis, information when software has operated hardware and information when the hardware has changed the value of an I/O register are separately displayed.

Abstract: A computer implemented application development (authoring) system permits objects (such as VBX custom controls) to be graphically inserted into the program under development by dragging and dropping associated icons into one of four views. The properties associated with the object may than be assigned settings. Development of a complete application is accomplished by visually arranging, ordering, and interconnecting the objects without the necessity of writing any code. The four views of Output, Map, Multitrack, and Workform may be synchronized so that changes made to the program in one view are simultaneously reflected in all other views. The system generates as output a script listing the objects and their properties which is then executed by a separate run time program. The system permits use of objects written to a standard specification and the addition at any time of additional objects written to that.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: A method for providing data indicative of the performance of a competing algorithm and an incumbent algorithm includes evaluating an incumbent-algorithm score indicative of a performance of an incumbent algorithm. The performance of a competing algorithm executing in place of the incumbent algorithm is then simulated. On the basis of the simulation, a competing-algorithm score predictive of a performance of the competing algorithm is evaluated. These scores are then provided to an output device.

Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.

Abstract: A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding differences within the data by analyzing various relationships within the data strings, such as the existence of unique strings. A computer program and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.

Abstract: A method and system for tracking instances of a testcase execution event within a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a design entity list is generated within the HDL model, wherein the design entity list identifies all design entities instantiated within the HDL model. One or more instrumentation code modules are dynamically loaded into the simulation control program, wherein the instrumentation code modules generate and process testcase execution events associated with at least one of the identified design entities.

Abstract: An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: An interface to one or more hardware devices includes a configuration library and objects to model the hardware. Software programs using the interface need not understand how to communicate with the hardware. Instead, the software programs may communicate with the interface. In turn, the interface communicates with the hardware. The software may be written when the hardware implementation features are unknown.

Abstract: A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plurality of processes; initializing each of the processes; executing with a single thread of control among the processes; and continuously cycling among the processes to obtain status information. A computer program and apparatus for implementing the aforementioned methodology are also disclosed.

Abstract: In response to an automatic baseline input, a default control template for a site in a telecommunications network is translated into monitoring and simulation templates. Current end-to-end application and component information are translated into operational modes for monitoring and simulation modules according to the monitoring and simulation templates. Operational controls are established for controlling the monitoring and simulation modules for controlling, in real time, the transmission of network management and simulation traffic.

Abstract: A system and method for intelligently generating computer code. The system being comprised of a local computer, which is connected to a remote computer via a network system or the Internet and which is capable of exchanging files with the remote computer. The local computer is further comprised of a document manager for transferring files between the local computer and the remote computer and for providing enhanced file management functions. The document manager works in connection with the server module, the site manager and the connectivity layer to connect to remote computers, to transparently exchange files with the remote computer and to manage server profiles and connection information that is related to remote computers and transferred files. Once the file is transferred to the local computer, the editor can modify the code associated with the file; the editor is also capable of creating new files.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.

Abstract: An automated analysis system detects malicious code within a computer system by generating and subsequently analyzing a behavior pattern for each computer program introduced to the computer system. Generation of the behavior pattern is accomplished by a virtual machine invoked within the computer system. An initial analysis may be performed on the behavior pattern to identify infected programs on initial presentation of the program to the computer system. The analysis system also stores behavior patterns and sequences with their corresponding analysis results in a database. Newly infected programs can be detected by analyzing a newly generated behavior pattern for the program with reference to a stored behavior pattern to identify presence of an infection or payload pattern.

Abstract: A software debugger adapted for connection to a hardware simulator simulating a hardware system includes a simulation information acquiring unit for acquiring cycle level execution information from the hardware simulator, and a debug processing unit for executing debugging by setting a processing width for time of one step execution instruction during debugging of a program executed on the hardware system based on the cycle level execution information.

Abstract: This invention is applied to a system design support system which handles at system level, e.g., a specification for software executed by a computer, a specification for hardware combined with semiconductor devices and the like, a specification for an embedded system constituted by a combination of software and hardware, and a specification for a business process such as a work flow. A consideration is given to difficulty in efficiently implementing an interrupt in a specification created in a system description language in such a case where the interrupt is defined at a lower level which is structurally separate from a portion where the interrupt actually occurs. An interrupt structure localizing apparatus specifies a portion in a system-level specification in which an interrupt actually occurs and localizes the portion, thereby obtaining a specification structure in which an interrupt does not occur across hierarchical structures.

Abstract: A PLC system construction support tool is provided wherein a display 31 of text and numeric values is produced at the left of a paste board 22. The display 31 is provided for each row of a system and whenever a unit is added or deleted, the numeric values are updated. The display 31 contains a character string of “WIDTH” meaning the total length of the units on the corresponding row and the numeric value of the width (mm units), a character string of “CURRENT CONSUMPTION” meaning the total current consumption of the units on the corresponding row and the numeric value of the current consumption (mA units), and a character string of “WEIGHT” meaning the total weight of the units on the corresponding row and the numeric value of the weight (g units).

Abstract: A system and method of direct invocation of Methods using class loaders. The method includes compiling a call to and a Method of a first class (assuming that the Method is final), determining whether the second class includes an instance of the Method of the first class, determining whether the instance of the Method of the second class overrides the Method of the first class, and altering the compiled code of the Method of the first class if the instance of the Method of the second class overrides the Method of the first class.

Abstract: A system and method for taking-off material details using a two-dimensional CAD interface for estimating a bill of materials and automatically creating a material take-off list for items in a two or three-dimensional design drawing, without manual work. The taken-off list information is provided on-line upon receiving an order for an information provision service through a communication network, such as the internet. The system is applicable, for example, in architecture, civil engineering, machinery, and facilities. The system comprises: a project information containing unit for containing project information including position data, design specifications, and shape data for a variety of design items; a material/cost containing unit for containing material information and cost information for building elements included in a CAD drawing; and a bill-of-material take-off processing unit for creating a material take-off list and the associated cost.

Abstract: There are previously involved: a program source-into which a log output instruction for adjusting an application model is embedded; a simulation source for performance simulation corresponding to the program source; and initial parameter values for adjusting the application model. Software parts capable of storing a history of parameter values after adjustment are combined to create an application program and the application model. Logs obtained by executing the application program and the application model are compared, and the parameters of the application model are automatically adjusted in conformance with actual measurement results of the application program. The adjusting result is fed back to the application model, and added to the history of original software parts, in which the parameter initial values are changed at need.

Abstract: A debugging system and debugging techniques for configurable processors remove the requirement of foreknowledge of specific configurable processor information from components of the debugging system where obtaining that foreknowledge is costly. The system is part of an environment that generates a processor where the proper information is generated in the right forms for such use.

Abstract: Method and system for automatically backtracing through a testcase file. First the testcase file is accessed. Next, a start line identifier for specifying an instruction line in the testcase file at which to begin processing is received. The instruction line in the testcase file that is specified by the start line identifier is processed first. The previous instruction lines in the testcase file are then processed in a sequential fashion until the beginning of the testcase file is reached.

Abstract: A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high level simulator of the processor. Next, a plurality of checkpoints are established. Then, state data at each of the checkpoints is saved. Finally, the program is run on a plurality of low level simulators of the processor in parallel, where each of the low level simulators is started at a corresponding checkpoint with corresponding state data associated with the corresponding checkpoint.

Abstract: For testing a logic unit under test (UUT), rule-based random irritation of a UUT model is provided to be used in conjunction with a simulator. The UUT model is stimulated (or irritated) with data patterns randomly generated by a pattern generator within the boundary of limitations imposed by a rules list. The rules list provides restrictions or encouragements on how data patterns are to be applied to the software model of the UUT. The pattern generator may be implemented either within or outside the simulator. If the pattern generator is incorporated into the simulator, then a software environment is required to interface communications between the pattern generator, the simulator, and other software entities involved in the simulation.

Abstract: A method, apparatus, article of manufacture, and a memory structure for generating a test code for an automatic procedure is disclosed. The method comprises the steps of defining a source file having a plurality of tags associated with a member of a library of executable code objects defining a set of instructions for performing a portion of the automatic test procedure, generating a test plan in a conventional language from the source file, and generating an automated test code for the automated test procedure from the source file. In one embodiment, a test index identifying system elements tested by the test code is generated and incorporated into the test plan, allowing the user to verify that all desired system elements are exercised by the automated test code. The article of manufacture comprises a data storage device tangibly embodying instructions to perform the method steps described above.

Abstract: A method and system for simulating the execution of a software program on a simulated hardware system. An instrumented software program is divided into program segments delineated by tags and is then analyzed for data describing the program segments. The data is tabulated and indexed in a function data table according to the program segments. Hardware parameters that at least define a portion of the simulated hardware system are tabulated in a hardware configuration file. The software program is executed on a host system, and when a tag is executed, data indexed in the function data table under the program segment corresponding to the executed tag and hardware parameters tabulated in the hardware configuration file are used to calculate an estimated execution time for the program segment corresponding to the executed tag. The estimated execution time for the program segment is added to a running total for the overall execution time of the software program.

Abstract: A computer-implemented method and system for determining colimits of hereditary diagrams. A user specifies a diagram of diagram and specifies performance of a colimit operation. Once the colimit is performed, the name of the colimit is added to the hereditary diagram. The described embodiment supports diagrams of diagrams, also called hierarchical diagrams.

Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.

Abstract: A data processing system, method, and program including an automated software test environment are disclosed for automatically testing a software application. A work flow manager is established for automatically managing the automated software test environment. The automated software test environment includes multiple computer systems coupled to a server computer system utilizing a network. The work flow manager is executed utilizing the server computer system. Multiple ordered test phases are established. At least each of two of the order test phases are executed utilizing different ones of the computer systems. An event is transmitted to the work flow manager utilizing one of the computer systems to start execution of selected ones of the ordered test phases. The work flow manager controls execution of the selected ordered test phases in response to the receipt of events.

Abstract: A method and apparatus for linking external information to a network management system are disclosed. A network management system is installed for and executes in association with a managed network. An external application program is identified by defining and storing in a connection file information that describes: the name and location of the program; a position in a menu control tree into which folders and items, which identify functions and options of the external application program, should be displayed and accessed; security roles associated with each folder and item; and other meta-information about the application program and its maker. The information may be stored in a markup format in a connection file. The network management system reads the connection file and integrates the information into its registry and other locations that determine how the network management system operates.

Abstract: The present invention relates to the design of an essentially digital system. As one example of digital systems, these may perform real-time transformations on time discrete digitized samples of analogue quantities. An example of such a system is a digital communication system. The transformations on the data can be specified in a programming language and executed on a processor such as a programmable processor or directly on application specific hardware. In accordance with the present invention the digital system is described as a set of threads in a description language. Alternative names for a thread are tasks and processes. The set of threads defines a representation or model of the digital system. In accordance with the present invention, the representation or model is preferably executable at each stage of the design independent of the current level of abstraction of that representation or model. With description language is meant a programming language.

Abstract: Backtraces are logged in the log file during execution of a program and tagged with information that can categorize the backtraces. Certain tags are also marked as “interesting” in the log file. A report is generated from the log file, indicating which of the backtraces are associated with the tags marked as interesting. In one embodiment, allocations of objects are logged with their addresses, and the objects that are later migrated into session memory are marked interesting.

Abstract: A functional testing technique is provided employing an abstraction matrix that describes a complex software component to be tested. The abstraction matrix includes state and event information. The technique is an automated process which parses the abstraction matrix to generate test cases and mapped expected results therefore. The test cases are separated based on layers of the software component and data structures are associated with the separated test cases of the layers. The data structures allow the test cases of the various layers to be uncorrelated. The software component executable is employed to generate test case execution threads from the test cases and mapped expected results for a particular layer. These execution threads can then be executed in parallel, thereby testing the software component.

Abstract: To test the functionality of a computer system, automated testing may use an automation testing tool that emulates user interactions. A database may store words each having a colloquial meaning that is understood by a general population. For each of these words, the database may store associated computer instructions that can be executed to cause a computer to perform the function that is related to the meaning of the word. During testing, a word may be received having a colloquial meaning that is understood by a general population. The database may be queried for the received word and the set of computer instructions may be returned by the database. The automated testing tool may then perform the function returned to the colloquial meaning of the word. The words stored in the database may be in English or another language.

Abstract: The invention comprises a method and system for encoding and generating transaction-based stimuli event states for the eventual application to the simulation of VLSI circuits. In the invention, each test state input is described by a vector where that vector is characterized by two symbols. The first symbol is the “stride” which references its relative time of reoccurrence among the test state inputs. The second symbol denotes the specific transaction on that stride. The stride is a number that is incommensurate relative to the other strides of the transactions.

Abstract: A data construct set and method for use with an industrial process which is controlled according to execution code wherein a processor running the code generates requests to mechanical resources to cause the resources to perform the process, the construct enabling generation of diagnostic code interspersed within the execution code which, when an event is to occur, indicates the event to occur, the invention also including status based diagnostics generally and methods of using the data construct set for generating both execution code and status based diagnostics.

Abstract: The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.

Abstract: A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.

Abstract: A computer program for creating a computer program executable on one or more digital signal processors each having a predefined function set. The computer program includes computer code for receiving user input selecting one or more digital signal processors. The computer program also includes computer code for defining one or more audio digital signal processing graphical controls. Each graphical control has an associated interface handler. The computer program also has computer code for associating an algorithm module containing digital processor specific functionality with the one or more audio graphical controls using the interface handler and computer code for linking the one or more audio graphical controls together defining an execution path.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.