Abstract: A system and method for debugging system solutions under design which cooperates with a solution design platform in which relationships between two or more system-level computing components are defined, in which each system-level computing component is associated with a behavioral model, and in which each relationship between system-level computing components is defined as a message-based communications interface. During simulation of the solution, messages are created by analysis of each behavioral model, and are transported or exchanged between system components. The debugging facility monitors interfaces between the system-level components, captures messages at the monitored interfaces, and adds tracking information to the captured messages. Following simulation, the stored messages and tracking information can be reformatted and displayed for review by the user to assist in determination of the problems in system-level operation.

Abstract: A list of program instructions are mapped into memory addresses to form an executable program by simulating their execution in turn so as to determine a memory address of a next program instruction to be executed. That memory address is then examined to determine if a program instruction has already been mapped thereto. If the memory address is empty, then the next program instruction from the list is mapped to that empty memory address and the execution of that next program instruction is simulated and the process repeated. If the memory address is not empty, then the program instruction read from that memory address is simulated again and the process repeated.

Abstract: An implementation of a technology, described herein, for facilitating the protection of computer-executable instructions, such as software. At least one implementation, described herein, may generate integrity signatures of one or more program modules—which are sets of computer-executable instructions—based upon a trace of activity during execution of such modules and/or near-replicas of such modules. With at least one implementation, described herein, the execution context of an execution instance of a program module is considered when generating the integrity signatures. With at least one implementation, described herein, a determination may be made about whether a module is unaltered by comparing integrity signatures. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method for generating test cases for software and a test case generator comprising a simulator that drives software under test from one input state to the next. The simulator is constrained by predetermined criteria to visit states that meet the criteria thus preserving computer resources. The states reached by the simulator are tested.

Abstract: The present mechanism allows commands entered on a command line in a command line operating environment the ability to execute in a first execution mode or an alternate execution mode. The command is executed in the alternate execution mode if the command includes an instruction to execute in the alternate execution mode. The alternate execution mode is provided by the operating environment and provides extended functionality to the command. The alternate execution mode may visually display results of executing the command, visually display simulated results of executing the command, prompt for verification before executing the command, may perform a security check to determine whether a user requesting the execution has sufficient privileges to execute the command, and the like.

Abstract: A computer implemented method for validating reports is provided. A request to validate a report is received. At least one element of the report is mapped to a corresponding template of independently defined logic. At least one corresponding template of independently defined logic is applied to a system of record to generate data. Comparisons of the at least one element against the data are displayed.

Abstract: A simulation method for optimizing transport displacement of workpieces in transfer presses is provided. Conclusions relating to the freedom of motion, number of strokes and program data for tool-specific machine control are determined by manipulating a displacement curve on a digital image of the transfer press which is determined by the simulation method.

Abstract: A system, method and computer program product for optimizing a software system through scenario evaluation. In accordance with the disclosed technique, a request is received for evaluation of an operational scenario that operates over an environment that is a superset of existing system capabilities encompassing system features or parameters that are not available in the currently running system. A knowledge base is consulted to derive recommendations with respect to operating parameters that may be collected to evaluate the scenario, mechanisms for gathering data relating to the parameters, and data evaluator operations for deriving a data evaluation result based on the data gathering. The knowledge base is further consulted to determine a reconfiguration recommendation based on the result. Scenario evaluation is performed based on simulation of the reconfiguration recommendation using the data evaluation result to determine efficacy of the scenario.

Abstract: A system and method for developing an application for subsequent deployment on a mobile device, the mobile device configured for using the deployed application to communicate over a network with a data source through a transaction server. The system and method comprising: an interface component module for providing access to a defined interface component for use in providing communication between the application and a local software configured to be resident on the mobile device; and a composer module for defining a text file containing definitions expressed in a structured definition language, the definitions describing a message section and a data section and a user interface section of the application, the composer module further for inserting handler definitions in the text file such that the handler definitions are configured for calling the interface component of the interface component module.

Abstract: A system for integration of commercial-off-the-shelf software applications and databases is provided. The system includes a commercial-off-the-shelf software application operable with a first data store and providing an output compatible with the first data store. The system includes a translator, a second data store, a service broker and a data access layer. The translator is operable to receive the commercial-off-the-shelf software application output and to translate the output to a format compatible with a second or other data store, such as newer version data stores or different vendor data stores. The second data store is operable to receive and store the translated output. The service broker is operable to maintain a record of transactions output from the commercial-off-the-shelf software application and to maintain a record of transactions stored in the second data store. The storage broker is further operable to roll-back failed transactions in the second data store.

Abstract: The system and method of the present invention can allow the imbedding of simulation primitives within a conventional programming language in order to use the full capabilities of the conventional programming language and its compiler without modification in the programming of efficient, scalable simulators. The simulation primitives are designed to be preserved through the compilation process, thus allowing a rewriter to modify the compiler's byte code output without accessing the source code. Also, since the rewriter output is a set of class files and a kernel can be written in the conventional programming language, and the system and method of the present invention can execute within a conventional virtual machine associated with the conventional programming language.

Abstract: An implementation of a technology, described herein, for facilitating the protection of computer-executable instructions, such as software. At least one implementation, described herein, may generate integrity signatures of one or more program modules—which are sets of computer-executable instructions—based upon a trace of activity during execution of such modules and/or near-replicas of such modules. With at least one implementation, described herein, the execution context of an execution instance of a program module is considered when generating the integrity signatures. With at least one implementation, described herein, a determination may be made about whether a module is unaltered by comparing integrity signatures. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A system for evaluating a simulation includes a reference simulator configured to execute a simulation image to obtain golden data, a test simulator configured to execute the simulation image to obtain test data, and a comparator configured to generate a comparison result by comparing a portion of the golden data to a portion of the test data before the execution of the simulation image on the test simulator has completed.

Abstract: A method of testing a process that has undergone modification. The process consists of multiple steps, and execution of the process involves interaction with multiple interfacing systems. A step consists of, e.g., sending a transmission to an interfacing system. The process is executed in normal fashion by sending transmissions to interfacing systems and obtaining responses to the transmissions from the interfacing systems. The transmissions and the responses thereto obtained from the interfacing systems are stored in a simulator. After the process is modified by modifying a step of the process, the modified process is executed in such a manner that transmissions are sent to the simulator rather than to the interfacing systems. The simulator sends responses to the transmissions. It is determined whether the responses received from the simulator are the expected responses, based on the modification made to the process.

Abstract: A method of simulating an analog mixed-signal circuit design using mixed-language descriptions includes initializing a mixed language simulation cycle, processing digital events during delta cycles at a current simulation time of the cycle, and, after the digital events are processed, determining an analog solution at the current simulation time.

Abstract: A compiling method and a processor using the same are provided. The compiling method includes simulating a first program code which includes at least one first operation command to generate a first operation result, compiling the first program code to generate a second program code which includes at least one second operation command, simulating the second program code to generate a second operation result, and comparing the first operation result with the second operation result to verify whether the second program code is valid.

Abstract: A method and apparatus for producing predictive performance and capacity information employing a type of factory to reduce the ongoing cost of providing simulation models to answer questions raised by the various business entities is provided. To achieve this, a continual process for providing on-going performance information is provided. The core concept is the development and long-term reuse of component models to create other, more broadly scoped performance models. This requires the implementation of standard simulation model constructs to facilitate reuse, processes for the development of models and their use by clients, and a stable yet flexible repository for component models. The invention comprises processes, standards, templates, and software tools that implement a performance service that consists of the long term maintenance of predictive performance models for repeated use by lines of business to provide capacity planning information.

Abstract: A method for testing a software shim is provided, in which a skeleton executable file is altered so that it mimics the executable file for which the shim is intended. The alterations made to the skeleton executable file may include one or more of the following: changing the file name, padding the file and changing the calculated checksum of the file.

Abstract: Embodiments of a callback procedure mechanism and method are disclosed in relation to a system running a physics simulation in parallel with a main application. A main application registers callback procedures in memory shared with the physics simulation in response to data generated by the physics simulation. The callback procedures are executed by the physics simulation with data generated by the physics simulation.

Abstract: A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Abstract: Embodiments of the invention are generally directed to a system and method for software program testing using a unit testing environment. A model having qualifiers is created using a modeling tool. A markup language meta-model is generated using the earlier created model. A unit test, generated using the markup language meta-model and the code or source code are stored in a code repository or source code repository. During execution, the unit test environment synchronizes the code from the code repository and reports are generated based on the unit test execution.

Abstract: Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system, are dynamically determined. For each representative simulation phase of the instructions, a model is selected from a number of models that provides specified accuracy with a minimal amount of simulation time, and the representative simulation phase is simulated using the model selected. The simulation results for the instructions to be executed on the system are then output.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.

Abstract: A system and method for a desk checker includes a partial state representation, a simulator controller to access the partial state representation and to continue a simulation without state information, and a desk checking component controlled by the simulator controller. The desk checking component includes any of a user interface, a static analysis engine, a partial execution component, and an analyzer. The system and method for desk checking includes simulating code execution on a computing device with partial state information and requesting user input to supplement the partial state information.

Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.

Abstract: A method and apparatus for concurrency testing within a model-based testing environment is provided. One implementation involves concurrency testing within a model-based software system testing environment, by receiving concurrent test service requests; duplicating a model representing software under test, based on the number of requests; sending the concurrent requests to each of the duplicated models sequentially but in different orders; storing the outcomes of each of the models; comparing the outcomes from the models to the outcome from the software system under test; and if all comparisons fail, then indicating test failure.

Abstract: Techniques for determining effects, on a system, of values for a parameter that is used to manage memory for the system include generating data that indicates a workload and an actual performance of the system. The data is generated while processing the workload within the system using a first value for the parameter. Based on the data, an estimated performance is generated. The estimated performance is a performance that the system would have experienced if a second value for the parameter had been used to process the workload. The second value is different from the first value for the parameter. Using these techniques, an administrator can determine what change in system performance could be achieved by changing a value of the memory management parameter. Therefore the system administrator can better determine whether to make the change in the value of the memory management parameter.

Abstract: A technique for maintenance and utilization of templates in a database. In response to a database access request in a productive data database access configuration, a database interface facilitates access to a template database when a template switch is enabled. The database interface facilitates normal database access when the template switch is disabled.

Abstract: An implementation of a technology is described herein for operating systems and loaders of executable images. Furthermore, the technology, described herein, facilitates the adoption and recognition by an operating system of an otherwise unsupported executable-image format by increasing the ease with which an executable-image loader may be modified. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A system and method for debugging system solutions under design which cooperates with a solution design platform in which relationships between two or more system-level computing components are defined, in which each system-level computing component is associated with a behavioral model, and in which each relationship between system-level computing components is defined as a message-based communications interface. During simulation of the solution, messages are created by analysis of each behavioral model, and are transported or exchanged between system components. The debugging facility monitors interfaces between the system-level components, captures messages at the monitored interfaces, and adds tracking information to the captured messages. Following simulation, the stored messages and tracking information can be reformatted and displayed for review by the user to assist in determination of the problems in system-level operation.

Abstract: A software-controlled computational component for processing input data is provided that includes a control program 148 for controlling the operation of a first computational component, an input for input data, and an output for output data. Each of the machine code for the control program, the input data, and the output data are expressed in a markup language, such as Extensible Markup Language.

Abstract: A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a succession of instruction words having address information, the succession of instruction words prescribing a sequence of machine words which are intended to be processed by an arithmetic and logic unit which is coupled to a buffer store, altering the association between at least a portion of the set of machine words and at least a portion of the set of addresses, changing the address information in the succession of instruction words based on the alteration of the association, storing the changed succession of instruction words in a memory, and storing the set of machine words in the memory, so that it is possible to access the machine words using the associated addresses.

Abstract: A method for analyzing and presenting application results, said method comprising the steps of creating at least one log file representing a result file of an application; tagging the at least one log file with at least one file tag representing a location of the result file of the application; tagging the at least one log file with at least one return code tag; tagging the at least one log file with at least one application configuration tag representing a graphical representation of the result file of the application; parsing the at least one log file tag; parsing the at least one return code tag; parsing the at least one application configuration tag; generating a summary report file from the at least one log file by using the parsed at least one file tag, the at least one return code tag, and the at least one application configuration tag; translating the summary report file into the graphical representation wherein the graphical representation comprises hyperlinks for navigation between the at least one

Abstract: The invention relates to enabling a user to log data of a block diagram without using a functional logging block within the block diagram. There is a first timing identifier for a first data set based on a timing characteristic of the first data set. There is also a first task identifier established by an execution engine that is associated with a first data set. The logging of the data associated with the first data set is based on the first timing identifier and the first task identifier.

Abstract: A dynamic runtime high level architecture (HLA) federation-execution data display allows a user to dynamically select HLA-federation-execution data to display while joined to an executing HLA federation.

Abstract: A debugger attaches to a parallel process that is executing simultaneously at various nodes of a computing cluster. Using a shim, executing at each node, to monitor each of the processes, the parallel process is debugged such that neither the process or the particular message passing system implemented on the cluster, needs to know of the existence or details regarding the debugger.

Abstract: Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a “system level netlist.” This system level netlist contains “system level instances” corresponding to “hardware cells” of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.

Abstract: A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

Abstract: Code coverage questions are addressed by a code coverage method that instruments an electronic module source design file with coverage probes and gives hierarchical names to the probes, then provides therefrom an instrumented gate level netlist. The instrumented netlist is run on a hardware emulator, executing reset trigger scripts to reset the branch and statement probes, and then a fully initialized design is driven in emulation on a simulated testbench from which the probe values are retrieved. These values can then be evaluated to determine the extent of code coverage. Various forms of coverage are supported including branch, statement, reset trigger and toggle coverage.

Abstract: A method for multi-platform parallel or real-time machine programming is provided. The method comprises specifying a parallel machine definition code defining a plurality of signal or data processing components and a communication of data or signals between the components, automatically converting the code into computer instructions for execution on an essentially sequential, non-parallel computer processor, a parallel execution of the instructions on the sequential processor and automatically converting the code into hardware programming data for providing parallel hardware operation according to the code, by including, in the hardware programming data, event control circuitry specification, priority control circuitry specification and buffering control circuitry specification to ensure that the hardware operation matches the execution on the sequential computer processor.

Abstract: A method of simulating software by use of a computer includes executing a program inclusive of a plurality of threads by a hardware model implemented as software on a software simulator, utilizing a monitor function of the simulator to collect information about accesses by monitoring accesses made by the plurality of threads with respect to resources provided in the hardware model, utilizing the monitor function to detect, from the collected information, overlapping accesses made to an identical resource area by two or more of the threads, and utilizing the monitor function to generate a message for warning of the overlapping accesses.

Abstract: Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit, and verification environments. The high-level language may be used to generate templates for custom computation logical units for specific user-determined functionality. The high-level language and compiler permit optimizations for power savings and custom circuit layout, resulting in integrated circuits with improved performance per watt of power consumption.

Abstract: Software configurations of devices are automatically restored. One or more software components obtained for a device are automatically tracked. Those one or more software components tracked for the device are then automatically provided to the device to restore the software configuration of the device, in response to an indication that restoration is desired.

Abstract: A method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: Technologies for estimating deviations in the performance characteristics of a newer version of software relative to an older version. Such performance characteristics include cache misses, pages faults, and the like. Estimations are typically made by instrumenting and profiling an older version binary, determining differences in code blocks between the older and a newer version, propagating profile data from the older version to the newer version based on a simulation heuristic, and estimating performance deviations based on the older version, the profile data, configuration parameters, and the changes in the newer version without actually executing the newer version of the binary.

Abstract: Systems and methods facilitate accurate and rapid simulation of software by periodically saving simulation states and design stimuli for use as a replay model. Divergences from the stored information may be detected during subsequent re-executions, which can in turn be run using the saved stimuli and states.

Abstract: A method for dynamic installation and activation of software packages in a distributed networking device. A master node provides a software package database that contains software packages for all nodes. It notifies a node that a software update is being requested, which examines the package identifiers and the dependencies and determines the running processes that will be affected by the update. The processes evaluate the effect that the update will have on their operation. If any of the processes determine that the update will degrade or have a negative impact on the operation of the node, the process will veto the update. If the master node receives no vetoes, it updates the node which installs and activates without interrupting the normal operation of the node.

Abstract: A system for testing components of a simulator has a slave device. A master controller is coupled to the slave device. The master controller transmits chip select and data signals to the slave device for testing a component of the simulator. A computer system is coupled to the master controller. The computer system displays at least one image of a control panel. A cursor of the computer system is placed on a desired component on the at least one image of the control panel. A test signal from the computer system is sent to the master controller for testing the component of the simulator.

Abstract: Methods and apparatus for testing software with real-time source data from a projectile according to various aspects of the present invention operate in conjunction with a real-time data source, a signal processor, a recordable medium, and a testing platform. The signal processor receives real-time data from a real-time data source during a test and saves it to a storage medium before providing the real-time data to the testing platform for permanent storage. During a subsequent test, the testing platform may upload the saved real-time data to the signal processor foregoing the need to generate new real-time data from the real-time data source.

Abstract: A system and method for increasing performance in a simulator environment operable to simulate a multiprocessor platform with program code running thereon. A set of processors are initialized upon instantiating the simulator environment on a host machine for executing the program code instructions. Code execution on a simulated processor is suspended by executing a simulator API routine which is called when the program code is to enter an idle state. The host resources that would otherwise have been spent on the processor running the idle loops are therefore conserved for use by the remaining processors.