Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.

Abstract: A system for providing communication between a debugger and a hardware simulator comprises a gateway providing a communication path between a hardware simulation and a separate debugger, the gateway comprising a bi-directional communication path out of the debugger into the hardware simulation, via uni-directional paths and communication paths out of the hardware simulation into the debugger, via a bi-directional path.

Abstract: A packet core network (PCN) includes a plurality of interconnected routers. An emulator is provided along with at least one of the routers and operates to control transmission of Internet Protocol (IP) datagrams there through in order to simulate the effects of having one of the non-radio inter-router connections fictionally comprise a wireless cellular radio link. The emulator responds to user input specifying wireless cellular radio link conditions to determine a time delay to be applied by the router against the transmission of each datagram. This time delay is set roughly equivalent to the delay introduced, under the user specified wireless cellular radio link conditions, by emulated radio link operation to erase uncorrectable frames to obtain retransmission. The emulator further sets a data rate for router handling of datagrams based on the user input to simulate congestion on the radio link due to the presence of other, competing users.

Abstract: The system and methods of the present application comprise one or more computers that generate and maintain a plurality of software-simulated computers. Each software-simulated computer is adapted to efficiently run an installed application program. Additional security layers provide access to the installed application through a remote user interface installed on a user's computing device. The system generates a new copy of the software-simulated computer for each user session, that prevents configuration problems from interfering with the proper operation of the application program, thereby consistently running the application in an optimized fashion, regardless of changes made to the software-simulated computer by the user or a virus. These software-simulated computers are unaffected by changes a user makes on their own client device. To this end, the system provides robust, web accessible capabilities to application software that may not have been adapted for use on the Internet.

Abstract: A storage medium is disclosed. The storage medium having stored on it a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of programming instructions to enable the other set of programming instructions to be compilable into either a version suitable for use in a hardware/software co-simulation that effectively includes calls to hardware simulation functions that operate to generate bus cycles for a hardware simulator, or another version without the effective calls, but explicitly expressed instead, suitable for use on a targeted hardware.

Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.

Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.

Abstract: An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing is operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

Abstract: An automatic code generation section reads a control model, and generates and releases a control program which is written in the C language. At the generation of the control program, a correspondence information formation section creates correspondence information indicative of the correspondence relationship between the control model and the control program. A simulation section reads the control model and simulates its operation. A program execution section reads the control program and executes it. A synchronizing section makes synchronization, that is, a relational linkage, between the operation results of the simulation section and the program execution section based on the correspondence information.

Abstract: A debugging method is used for the keyboard controller code. Through the breakpoints set at the testing end and loaded debugging program, the keyboard controller code sends state data to the testing end at the breakpoints in accord with the debugging program. The testing end returns commands according to the received state data to trace the execution state of the code, thereby debugging the code procedure.

Abstract: A method is provided for prototyping, testing, stimulating and verifying software embedded in a microprocessor without modifications to the underlying source code. The method includes: presenting an software program having a plurality of machine instructions of a finite number of fixed lengths in an executable form; searching through the machine instructions of the executable and finding at least one appropriate instruction to replace; and defining a replacement instruction for identified machine instructions in the software program; and replacing identified machine instructions in the executable form of the software program with the replacement instruction. The replacement instruction may be further defined as a branch instruction that references an address outside an address space for the software program.

Abstract: A personal computer includes a code generation tool to generate a source code from a given model compliant with a plurality of variations. From an HDD, the computer acquires the given model including a plurality of part specification blocks, each of the part specification blocks specifies a specific part of the given model. From the HDD or an input apparatus, the computer acquires selection information indicating that a given specific part of the given model is to be selected or deleted using the corresponding part specification block. Based on the selection information, the computer thereby generates a source code from an intermediate model where unnecessary part is deleted from the given model.

Abstract: A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

Abstract: Simulate and calibrate a process by generating a modular representation of a process using modules and variables, each module representing a portion of the process, each variable representing an adjustable parameter of the process. One or more variables are set to specific values. Source code is generated to implement the process according to the modular representation, the code being generated without implementing portions of the process that are not executable when the one or more variables are set to the specific values. The source code is compiled into a machine code and executed to implement the process.

Abstract: To help identify shortcomings in software requirements for a software capability early in the software development lifecycle, the present invention discloses a method of logic testing a software requirement for a software capability, the method comprising: (a) defining a logical representation of the software requirement; (b) defining a test scenario that corresponds to the software requirement; and (c) processing the defined logical representation with the defined test scenario to thereby generate a simulation result indicative of whether the software requirement needs alteration. Preferably, the present invention is implemented as an integrated tool executed by a desktop PC or workstation that interacts with the user through a variety of graphical user interfaces (GUIs) to perform logic testing of software requirements.

Abstract: A method and architecture for analyzing a computer program by finding similar sections of execution of the computer program. Code of the computer program is run over a plurality of intervals of execution, and during the execution of the program, a statistic is tracked for a component. Using the tracked statistic, behavior of the computer program is identified over each of the plurality of intervals of execution, and at least one identified behavior of at least one interval of execution is compared to the behavior of another interval of execution to find similar sections of behavior.

Abstract: A system and a method for automatic verification of complex enterprise software systems, which improves the testing process by producing test scenarios using business process specifications.

Abstract: A mechanism for testing execution of applets with plug-ins and applications is described. In one embodiment, a data structure that specifies at least two applets of a plurality of applets is accessed. Based on the data structure that specifies the two applets, a plug-in that executes with an application is caused to attempt to execute each of the two applets. After causing the plug-in to attempt to execute the two applets, results are generated based on the attempt to execute each of the two applets. The mechanism may be implemented to test multiple test suites that each comprise one or more test cases that each include an applet, and reports may be generated for individual test cases, test suites, or a set of test suites. This embodiment of the present invention minimizes the time required for testing and allows for testing the effects of applets that are not visible to a user.

Abstract: A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.

Abstract: An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Abstract: An operating system is simulated to run in conjunction with a native operating system, allowing processes originally developed for the operating system being simulated to be ported to the environment of the native operating system with a minimum of effort. Ported processes will consume resources of both operating systems, the native operating system and the simulated operating system, that are cleaned or otherwise removed when the ported process ends by setting up a monitoring facility to detect when the ported process ends. When that occurs, the simulated operating system resources are cleaned by a cleanup process that impersonates the ported process that ended. The cleanup process is also monitored, so that when it ends, additional cleanup processes are called into action to cleanup the system resources of the remaining simulated operating system used by the ported process that ended, and the system resources used by the cleanup process.

Abstract: A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.

Abstract: A debugging environment for a multi-processor simulator or emulator is disclosed. The simulator or emulator is ideally suited for the development of embedded software. The simulator can contain multiple processor models, with each processor model representing a processor. The simulator or emulator also includes a scheduler which controls the execution of the processor models. Each processor also communicates with a debugger via a debug adapter. The debug adapter acts as a pass-through filter for non-control commands which are communicated between a processor and its attached debugger. However, the debug adapter routes control commands to the scheduler. The scheduler ensures that all of the processors and debuggers maintain synchronization. Other modules can also be included in the multi-processor simulation environment, for example, clock gate modules.

Abstract: The present invention can be applied to an operation input processing apparatus provided with an operation input executing section which issue tickets in response to users' input operations. A personal computer extracts an application program applied for the operation input processing apparatus from a software resource containing a plurality of application programs and operates the operation input executing section by executing the extracted application program. Thereby the operation input processing apparatus having various functions can operate application programs easily without damage thereto.

Abstract: Modules produced and utilized for system simulation are translated by a computer system into software modules compatible with and executable on a target system platform. Initially, software is typically produced to enable a modeling tool to simulate a new design and target system behavior. The simulation software basically includes functions performed by the corresponding target system. The computer system of the present invention translates modules associated with the simulation to software modules compatible with and executable on a target system platform. The translated modules are subsequently compiled and downloaded to the target system. The present invention enables direct transition from simulation to a software implementation.

Abstract: A first system for analysis of a portion of a partial state space includes a representation component and an analysis component. The portion of the partial state space is related to a part of a second system. The representation component of the first system employs a value in the portion of the partial state space to represent that information for the part of the second system is unknown. The analysis component of the first system employs the value in the portion of the partial state space to analyze, in response to an analysis question that is related to the part of the second system, the portion of the partial state space.

Abstract: A method comprising providing an interpretable coded algorithm; providing an executable coded algorithm; determining whether the interpretable coded algorithm is functionally equivalent to the executable coded algorithm; and selectively performing one of interpreting the interpretable coded algorithm and executing the executable coded algorithm.

Abstract: In selecting and building a processor configuration, a user creates a new set of user-defined instructions, places them in a file directory, and invokes a tool that processes the user instructions and transforms them into a form usable by the software development tools. The user then invokes the software development tools, telling the tools to dynamically use the instructions created in the new directory. In this way, the user may customize a processor configuration by adding new instructions and within minutes, be able to evaluate that feature. The user is able to keep multiple sets of potential instructions and easily switch between them when evaluating their application.

Abstract: There is provided a simulation method of instruction scheduling comprising detecting a loop from an instruction sequence to be simulated, registering an instruction scheduling target instruction sequence in a loop detection state, comparing a current scheduling target instruction sequence with the registered scheduling target instruction sequence for each loop cycle, and skipping, when the current scheduling target instruction sequence matches the registered scheduling target instruction sequence, scheduling of that scheduling target instruction sequence, and newly registering, when the two instruction sequences do not match, the current scheduling target instruction sequence and executing scheduling.

Abstract: In a software debugging apparatus, dump information formed by a hardware simulator is acquired and analyzed. When displaying the result of the analysis, information when software has operated hardware and information when the hardware has changed the value of an I/O register are separately displayed.

Abstract: The invention provides a simulation method and the like which, where simulations of hardware and software that cooperatively operate with one another are conducted, can readily link software debugging functions to hardware simulation functions. At a first computer, a debugger is used to debut software, and generates commands for simulation of hardware and transmits the same to a second computer. At the second computer, the commands are received at an HDL simulator, and the commands are inputted in a bus interface model included in a hardware simulation model created in an HDL by using the HDL simulator, whereby hardware simulations are performed in cooperation with debugging of software.

Abstract: A system and method enable appropriately concentrating instruction strings or data pieces sporadically present in a plurality of regions over more than one compilation unit and adjusting the front-and-rear relationship of executed instruction strings without changing the program compilation unit such as a file, subroutine, or function and also without creating a link processing program for batch processing of the system as a whole. Different section names are given to the executed instruction strings and the unexecuted instruction strings and the referenced data and the unreferenced data of an object program respectively. When an execution module is generated from the object program by linking, the sections having an executed section name and the sections having an unexecuted section name in a plurality of files may be aggregated respectively to divide the instructions into an execution portion and an unexecution portion.

Abstract: A system and method for increasing performance in a simulator environment operable to simulate a multiprocessor platform with program code running thereon. A set of processors are initialized upon instantiating the simulator environment on a host machine for executing the program code instructions. Code execution on a simulated processor is suspended by executing a simulator API routine which is called when the program code is to enter an idle state. The host resources that would otherwise have been spent on the processor running the idle loops are therefore conserved for use by the remaining processors.

Abstract: A system and method for determining fault path behavior in a computer software system. An error or event, the occurrence of which is to be tested, is assigned a probability value and an array of elements populated by pseudo-random numbers. Upon each operation of the system under test the current array value is compared against the probability value. If the current array value is greater than or equal than the probability value, the error or event is simulated within the software. Otherwise, the event is not simulated and the software is left to operate conventionally. The array is incremented upon each occurrence of the system under test.

Abstract: A method of operating a computer system includes providing a program in memory, verifying the program prior to an installation of the program and generating a program fault signal when the verification fails. The program includes at least one program unit, and each program unit includes an Application Programming Interface (API) definition file and an implementation. Each API definition file defines items in its associated program unit that are made accessible to one or more other program units and each implementation includes executable code corresponding to the API definition file. The executable code includes type specific instructions and data. Verification includes determining whether a first program unit implementation is internally consistent, determining whether the first program unit implementation is consistent with a first program unit API definition file associated with the first program unit implementation and generating a program fault signal when the verifying fails.

Abstract: A technique for applying time compression to simulate long-term execution of a software application in the short time frames includes providing simulated events to a software application under test and selectively advancing the system clock. The subject system utilizes two utility modules to interact with a software application under testing. The first module, the Event Simulation module, generates a range of predefine events which simulate the nature and frequency of events to which the software application would react. The second module, the Clock Modification module, intercepts the time signal generated by the operating system under which the software application is executing and modifies the clock signal, typically by advancing the time at a rate which is faster than one second per second, i.e., normal time rate. With the subject system, the behavior of an application over a simulated period may be observed in just a fraction of the simulated period duration, e.g.

Abstract: Described is a method that enables the automatic generation of a boolean program that is a predicate abstraction of a program written using a general programming language. The method is capable of abstracting code statements within the program that include procedure calls, assignments, goto statements, conditionals, and pointers. In accordance with the invention, predicates of interest are identified for each code statement in the program. For each particular code statement, the process generates predicate statements that describe an effect that the statement has on the predicates of interest. If the effect of a particular code statement is indeterminable, non-deterministic predicate statements are included in the boolean program to model the indeterminable nature of the code statement. In addition, if a particular code statement includes a procedure call, the arguments and return value of the procedure call are translated to associated predicates in the calling context.

Abstract: The invention provides a debug function built-in type microcomputer that is capable of creating a readily analyzable debug environment and compressing output information, even when an output signal line having a bit width fewer than a bit width of a command bus is used to trace contents on the command bus. In a debug function built-in type microcomputer, a DBG (debug unit) outputs information to be traced, and status information indicative of contents of the information to be traced from a status generation circuit.

Abstract: The method of the present invention comprises splitting pointer data in a code and data image, and allocating the upper half of each pointer in a compressed block to allow a system to exceed a memory addressing limitation during execution, while retaining the same data structure layout. In addition, the method of the present invention compresses and then allocates the upper pointer data “on demand” so that memory requirements during a large pointer (for instance, 64-bit) build are merely incremental over normal pointer (32-bit) requirements.

Abstract: A method used with a simulator and a controller, the controller running execution code to provide output signals which, when linked to resources, cause the resources to cycle through requested activities, the simulator receiving controller output signals and, in response thereto, generating motion pictures of resources as the resources cycle through requested activities, the simulator using data structures which model the resources to determine which motion pictures to generate, the method for generating execution code and data structures for use by the controller and the simulator, respectively, and comprising the steps of, for each resource, encapsulating resource information including resource logic in a control assembly (CA), instantiating at least one instance of at least one CA, compiling instantiated CA instance resource logic to generate execution code, gleaning simulation information from the instantiated CA instances and using the gleaned simulation information to generate a simulation data structur

Abstract: A means of increasing the steady-state simulation speed of a design comprising digital, analog, mixed-signal and full-wave components is taught using general purpose processors and electronically re-configurable logic.

Abstract: A method of generating circuit simulation code using a computer language includes declaring a width of a state variable equal to a width of a vector state where the vector state has a width greater than a system platform width. The method also includes extracting data from the vector state and placing the data in the state variable.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: A behavioral abstraction is, in an abstract sense, a generalization of an event cluster. Behavioral abstraction is a technique where a predetermined behavioral sequence is automatically recognized by the simulator in a concurrent stream of system events. A behavioral sequence is at its most basic level a partial order of events. However, the events considered in a behavioral sequence are subject to configuration-based filtering and clustering. This allows a designer to create a model for a particular behavior and then set up a tool to find instances of the particular behavior in an execution trace. Behavior models are representations of partially ordered event sequences and can include events from several components.

Abstract: Herein there are described methods for testing the control software of an entity (CE,CO) of a control system of a telecommunication equipment, fit for control systems comprising a controller entity (CE) and a plurality of controlled entities (CO-1 . . . CO-n), wherein the entities are in communication (NW) between each other.

Abstract: A source code debugger connected to a cycle-accurate instruction set simulator, comprising: a pipeline information obtaining module configured to obtain address information in execution at respective stages on a pipeline from the cycle-accurate instruction set simulator; a pipeline information displaying module configured to edit the address information of the pipeline obtained by the pipeline information obtaining module together with the progress of processing of the stages; a resource information obtaining module configured to obtain address information of a program in execution together with instruction codes; and a resource information displaying module configured to edit the address information and the instruction codes obtained by the resource information obtaining module.

Abstract: A to-be-verified model 21 including a processor 23, a program RAM 24, a data RAM 25, and a peripheral I/O device 26, which are connected to each other through a bus, is described in hardware description language. A test bench 22, which requests interrupt to the processor 23 through the peripheral I/O device 26, is also described in a hardware description language. A test program 14, which includes an interrupt processing routine according to each interrupt factor and a main routine to be processed by the processor 23, is described in assembly language. A command to write the identifying code of interrupt processing routine in a trace memory region RV in the data RAM 25 is inserted in each interrupt processing routine. After simulating the to-be-verified model 21 and the test bench 22, the trace value RV is compared with an expected value EV so as to verify the interrupt routine execution sequence.

Abstract: An arithmetic device allocation design method of the present invention includes the steps of: in the case of allocating an arithmetic operation A to the arithmetic device, comparing an increased circuit area due to a selector to be provided so as to allocate the operation A to an arithmetic device C to which another arithmetic operation B has already been allocated and an increased area due to an arithmetic device D to be created anew to which only the operation A is allocated; when the increased circuit area due to the selector is smaller, allocating the operation A to the device C to which the another operation B has already been allocated while providing the selector; and when the increased circuit area due to the device D is smaller, creating the device D anew so as to allocate the operation A to the device D created anew.

Abstract: For testing a logic unit under test (UUT), rule-based random irritation of a UUT model is provided to be used in conjunction with a simulator. The UUT model is stimulated (or irritated) with data patterns randomly generated by a pattern generator within the boundary of limitations imposed by a rules list. The rules list provides restrictions or encouragements on how data patterns are to be applied to the software model of the UUT. The pattern generator may be implemented either within or outside the simulator. If the pattern generator is incorporated into the simulator, then a software environment is required to interface communications between the pattern generator, the simulator, and other software entities involved in the simulation.