Abstract: A utility program develops and updates an API-translation layer of an emulator for running programs written for one platform on another platform. The utility builds a module for each API from a set of templates to execute the API's function on the other platform. Generalized function templates iterates through API functions. Exception templates can override the generalized templates in specific cases. Types templates convert individual arguments of the API. Code templates contain code for incorporation into a number of other templates.

Abstract: A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generating a plurality of expression objects representing fixed values and/or relationships between said fixed values and said variable values according to said program code; said objects being organized into a branched tree-like network having all register objects at the lowest basic root or tree-trunk level of the network with no register object feeding into any other register object.

Abstract: A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generating a plurality of expression objects representing fixed values and/or relationships between said fixed values and said variable values according to said program code; said objects being organized into a branched tree-like network having all register objects at the lowest basic root or tree-trunk level of the network with no register object feeding into any other register object.

Abstract: A method and structure for emulating on a single display platform an application's user interface as it would appear on each of a number of target devices, given a set of device characteristics for any device to be emulated and a formal description of one or more applications to be emulated. The method includes combining a selected one or more of the device characteristics and a selected one of the application formal descriptions and providing a simultaneous and consistent display representation for the selected application, so as to provide a stylized rendering of the selected application's interface in a uniform appearance and in which the selected application's interface for more than one target device can be simultaneously viewed. The method also synchronizes the display representation, so that a simultaneous update to all of the selected target device representations is updated when information in a device-independent portion of the formal description is changed.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: A computer system includes a memory and a processor. The memory includes an interpreter for interpreting data in a multiple task system. The interpreter includes a scanner for reading at least one command from an input port and providing a token according to the category of the command, a first parser for interpreting the command when the token indicates the first parser, and a second parser for interpreting the command when the token indicates the second parser, for temporarily storing data generated after interpreting the command into a message center in the memory, and for executing the data stored in the message center after interpreting all other corresponding commands. The processor is for processing programs and data stored in the memory.

Abstract: A method, system, and apparatus for improving performance of multi-threaded computer programs that re-establishes the lock structure that enables access to a portion of the computer memory and thereby reduces contention for computer memory. The present invention analyzes the references to computer memory and re-structures the memory access lock structure and thereby improves the use of regions of computer memory that are found to be mutually exclusive.

Abstract: An emulator (30) allows subject code (10) written for a subject processor (12) having subject processor registers (14) and condition code flags (16) to run in a non-compatible computing environment (2). The emulator (3) identifies and records parameters of instructions in the subject code (10) that affect status of the subject condition code flags (16). Then, when an instruction in the subject code (10) is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.

Abstract: A method for dynamically customizing object code for simulation includes obtaining a statically generated object (SGO) and a first test vector, segmenting the SGO with a marker node to generate a segmented SGO comprising a plurality of SGO segments, generating a first simulation profile using the segmented SGO and the first test vector, locating a first unexercised segment of the plurality of SGO segments using the first simulation profile, and generating a first reduced SGO by removing the first unexercised segment from the segmented SGO.

Abstract: A high level transformation method and apparatus for converting data formats in the context of network applications, among other places. A flexible transformation mechanism is provided that facilitates generation of translation machine code on the fly. A translator is dynamically generated by a translator compiler engine. The translator compiler engine implemented according to the present invention uses a pair of formal machine-readable format descriptions (FMRFDs) and a corresponding data map (DMAP) to generate executable machine code native to the translator platform CPU. When fed an input stream, the translator generates an output stream by executing the native object code generated on the fly by the translator compiler engine. In addition, the translator may be configured to perform a bi-directional translation between the two streams as well as translation between two distinct protocol sequences.

Abstract: A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor.

Abstract: A simulator includes a binary translator to translate target code into host instructions to be executed on a host processor. To identify target instructions which may be modified by self-modifying code, the simulator determines whether a target instruction to be translated resides in a writeable page, and if so, inserts a run-time check into a translation cache along with translated instructions corresponding to such target instructions.

Abstract: Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

Abstract: The library contains a plurality of functions and a plurality of procedures that model hardware-components of the target processor. The plurality of functions and/or a plurality of procedures are defined and described in a high-level language, e.g. C-language. All of software development can be done in the high-level language; a common source code can be used in two types (compiler type and interpreter type) of simulators without rewriting the source code. Parts of the simulators can be communalized and development efficiency improves. The executing-cycles-number is acquired and measurable.

Abstract: The present invention relates to a computer system adapted to efficiently execute binary translated code. In accordance with the present invention, foreign code is stored in a foreign virtual memory space, translated to acquire binary translated code, which is stored in a host virtual memory space and then executed. The host computer system isolates each virtual memory configuration into separate processes referred to as a virtual machine while enabling multiple virtual machines to exist simultaneously. Execution may switch from one virtual machine to another merely by switching to a new page table, where each page table describes the memory configuration of a virtual machine. Common system level resources are shared by the virtual machines under the control of a virtual memory manager.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: A semiconductor test program debugging apparatus is disclosed to which data concerning a packet input to and output from the packet transfer memory device is supplied, and which extracts a part corresponding to the packet from data input to and output from the memory device with response to a test signal generated by a tester simulator and displays the details of the part.

Abstract: A source code is entirely described in a high-level language. The source code includes a library description and a versatile description other than the library description to correspond to a target processor-adapted assembler code. The library description is made up of functions defined in high-level language. In order to produce target processor-adapted software, a dedicated translator transforms the library description into, one by one, an assembler code, while a compiler compiles the versatile description. A simulator includes a compiler that is operable to compile the library description with reference to a library.

Abstract: A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.

Abstract: A method (and system) of transparent dynamic optimization in a multiprocessing environment, includes monitoring execution of an application on a first processor with an execution monitor running on another processor of the system, and transparently optimizing one or more segments of the original application with a runtime optimizer executing on the another processor of the system.

Abstract: Techniques for porting operating systems of a first class whose representatives include operating systems implementing the POSIX standard to operating systems of a second class whose representatives include operating systems implementing the Win32 API. Processes belonging to operating systems of the first class are characterized by a single thread, parent-child relationships, and signal handlers that execute on the top of the stack; processes belonging to operating systems belonging to the second class have multiple threads, do not have parent-child relationships and do not necessarily execute their signal handlers at the top of the stack. Techniques are disclosed for implementing signal handling as required for operating systems of the first class and providing a signal to a parent process of the first class when one of its child processes terninates.

Abstract: A dynamic binary translator converts input instruction sequences into output instruction sequences that are stored in a translation cache. In order to maintain coherence of the translation cache with the run-time version of the input instructions, translated code is checked by either a conflict detection mechanism or a code-invariance mechanism. For conflict detection, the system preferably uses memory traces generated by the memory management unit of the underlying hardware processor. In order to check for code-invariance, preludes for comparing cached, output instruction sequences with their supposed run-time input instruction equivalents are appended to the cached instructions themselves. Changes in the input sequences then result only in retranslation of instruction sequences in which at least one instruction has changed; this avoids costly total flushes of the translation cache.

Abstract: Configuration software is used for generating hardware-level code and data that may be used with reconfigurable/polymorphic computing platforms, such as logic emulators, and which may be used for conducting signals intelligence analysis, such as encryption/decryption processing, image analysis, etc. A user may use development tools to create visual representations of desired process algorithms, data structures, and interconnections, and system may generate intermediate data from this visual representation. The Intermediate data may be used to consult a database of predefined code segments, and segments may be assembled to generate monolithic block of hardware syhthesizable (RTL, VHDL, etc.) code for implementing the user's process in hardware. Efficiencies may be accounted for to minimize circuit components or processing time. Floating point calculations may be supported by a defined data structure that is readily implemented in hardware.

Abstract: A method comprising providing an interpretable coded algorithm; providing an executable coded algorithm; determining whether the interpretable coded algorithm is functionally equivalent to the executable coded algorithm; and selectively performing one of interpreting the interpretable coded algorithm and executing the executable coded algorithm.

Abstract: In selecting and building a processor configuration, a user creates a new set of user-defined instructions, places them in a file directory, and invokes a tool that processes the user instructions and transforms them into a form usable by the software development tools. The user then invokes the software development tools, telling the tools to dynamically use the instructions created in the new directory. In this way, the user may customize a processor configuration by adding new instructions and within minutes, be able to evaluate that feature. The user is able to keep multiple sets of potential instructions and easily switch between them when evaluating their application.

Abstract: There is provided a simulation method of instruction scheduling comprising detecting a loop from an instruction sequence to be simulated, registering an instruction scheduling target instruction sequence in a loop detection state, comparing a current scheduling target instruction sequence with the registered scheduling target instruction sequence for each loop cycle, and skipping, when the current scheduling target instruction sequence matches the registered scheduling target instruction sequence, scheduling of that scheduling target instruction sequence, and newly registering, when the two instruction sequences do not match, the current scheduling target instruction sequence and executing scheduling.

Abstract: An operating environment for use on a computer system to provide operating system services to a user application running on the computer system. The computer system includes a network connecting the computer system to at least one other computer system. The user application generates operating system commands requiring access to the network, and commands requiring operating system actions that do not access the network. An operating environment according to the present invention includes a network server for accessing the network, a non-network server for executing operating system commands not requiring network services, and an emulation library for receiving the operating system commands generated by the user application.

Abstract: A computer-implemented method for converting a UML rendering of an RSM-based metamodel to a UML rendering of a MOF-based metamodel. The method includes the steps of removing inheritance from classes defined within a Repository Services Model (“RSM”) and removing each explicit “construct” operation from each class in the RSM-based metamodel Next, each use in the RSM-based metamodel of an RSM type is changed to use a non-RSM type. After this, each element of the RSM-based metamodel is converted to a corresponding MOF-based element and a determination is made as to whether or not the RSM naming service is used in the RSM-based metamodel, and if so “name” attributes are added that would have been inherited from the RSM classes. A <<metamodel>> stereotype is added to the UML rendering of the MOF-based metamodel; and the MOF properties are set on the UML rendering.

Abstract: A method and structure for emulating on a single display platform an application's user interface as it would appear on each of a number of target devices, given a set of device characteristics for any device to be emulated and a formal description of one or more applications to be emulated. The method includes combining a selected one or more of the device characteristics and a selected one of the application formal descriptions and providing a simultaneous and consistent display representation for the selected application, so as to provide a stylized rendering of the selected application's interface in a uniform appearance and in which the selected application's interface for more than one target device can be simultaneously viewed. The method also synchronizes the display representation, so that a simultaneous update to all of the selected target device representations is updated when information in a device-independent portion of the formal description is changed.

Abstract: A method and apparatus for processing a composite signal generated by a transient signal generation mechanism to extract a repetitive low SNR transient signal, such as an evoked potential (EP) appearing in an electroencephalogram (EEG) generated in response to sensory stimulation, by: (a) dynamically identifying, via a learning process, the major transient signal types in the composite signal; (b) decomposing the identified major transient signal types into their respective constituent components; (c) synthesizing a parametric model emulating the transient signal generation mechanism; and (d) utilizing the model and the constituent components to identify and extract the low SNR transient signal from the composite signal.

Abstract: Systems and methods for implementing efficient execution transfers between successive translations of stack-based code in a virtual machine environment are provided. Briefly described, one such method comprises the steps of: defining a global translation convention for translating one or more stack-based code instructions on a register-based environment, the global translation convention specifying a predetermined portion of a stack-based context corresponding to a stack that is to be mapped to one or more registers corresponding to the register-based environment and enforcing the global translation convention for each translation of the one or more stack-based code instructions in the register-based environment.

Abstract: Systems and methods for verifying execution of translated code operative on a host computer system different from the computer system designated for the original program code. In one arrangement, the system and method fetch program code, translate program code, emit the translated program code into at least one code cache, execute the translated code within the at least one code cache, interpret the program code, and compare a translator generated state with an interpreter generated state to confirm desired code execution.

Abstract: An embodiment of the invention includes, parsing a source code, performing a plurality of optimizations on the parsed code, generating a plurality of configuration instruction sets based on the optimized source code and automatically selecting one of the plurality of generated configuration instruction sets according to a user defined criteria, the selected configuration instruction set being used to configure hardware.

Abstract: A threaded interpreter (916) is suitable for executing a program comprising a series of program instructions stored in a memory (904).

Abstract: An emulator (30) allows subject code (10) written for a subject processor (12) having subject processor registers (14) and condition code flags (16) to run in a non-compatible computing environment (2). The emulator (3) identifies and records parameters of instructions in the subject code (10) that affect status of the subject condition code flags (16). Then, when an instruction in the subject code (10) is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.

Abstract: To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as branch prediction, register usage, overflow, a history of branch predictions of groups of branches combined, and a history of register usage for: dynamically modifying instruction parameters of an emulation sequence of instructions; reordering emulated instructions; and adding or changing the dynamic execution information.

Abstract: A quantum integrated development environment is provided for designing quantum logic that utilizes N qubits, compiling the quantum logic into quantum machine language instructions, and running the machine language instructions on a quantum computing system. Additionally, the results of the execution are provided as an output.

Abstract: A system and method of simulating a PC platform are disclosed. The PC platform includes a CPU, a chipset, memory and IO devices. The machine instructions of a target CPU are simulated by several simulation modules. The simulation modules include a monitor that translates the machine instructions into translated code and performs virtualization of the target CPU state. The monitor protects the translated code by using a segmentation mechanism. The simulation modules also include a virtual machine that executes the translated code, and a kernel that detects exceptions occurring in the virtual machine and transfers control between the virtual machine and the monitor according to a type of the exceptions. Most of the simulated instructions, including those that access the memory, are executed directly to achieve high simulation speed.

Abstract: Disclosed is a an integrated circuit method and system for generating a compiler to map a code set to object code capable of being executed on an operating system platform. The integrated circuit is encoded with logic including at least one neural network. The at least one neural network in the integrated circuit is trained to convert the code set to object code. The at least one trained neural network is then used to convert the code set to object code.

Abstract: A system in which a terminal of a program developer and a program conversion system are connected to each other via a network. The program conversion system is provided with a program sending/receiving device for sending a generated conversion destination program to and receiving a conversion source program from the terminal of the program developer, emulation devices corresponding to different conversion source programs, respectively, for generating intermediate-language programs by converting the conversion source programs, conversion devices corresponding to different conversion destination programs, respectively, for generating the conversion destination programs by converting the intermediate-language programs, a first selecting section for selecting one of the plurality of emulation devices, and a second selecting section for selecting one of the plurality of conversion devices.

Abstract: The present disclosure relates to a system and method for emulating a computer system. In one arrangement, the system and method pertain to fetching program code, translating program code, emitting translated program code into at least one code cache, and executing translated code within the at least one code cache in lieu of associated program code when a semantic function of the associated program code is requested. Operation of the system and method can be facilitated with an application programming interface that, in one arrangement, can comprise a set of functions available to the translator including an emit fragment function with which the translator can emit code fragments into code caches of the dynamic execution layer interface, and an execute function with which the translator can request execution of code fragments contained within the at least one code cache.

Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. The guest computer architecture has programs composed of legacy instructions. To perform the emulation of the legacy instructions on the host system, the legacy instructions are accessed in the host system. Each particular legacy instruction is translated into one or more translated instructions for emulating the particular legacy instruction. State information is provided for determining a program execution mode for the legacy instructions. For each particular legacy instruction, a query is made to determine if translated instructions for execution mode remain stored as a result of a prior translation. If not stored, the legacy instruction is translated and the translated instructions are stored with the state information. If the translated instructions for the desired translation mode are already stored, emulation continues without need for further translation.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. The guest computer architecture has programs composed of legacy instructions. Each particular legacy instruction is translated into one or more particular translated instructions for emulating the particular legacy instruction. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set. If the corresponding flag is set, translation of the operand-using instruction is suspended and the one or more particular translated instructions corresponding to the operand-setting instruction are executed to determine the value of the precedent operand.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. The guest computer architecture has programs composed of legacy instructions. To perform the emulation of the legacy instructions on the host system, the legacy instructions are accessed in the host system. Each particular legacy instruction is translated into one or more particular translated instructions for emulating the particular legacy instruction. RISC blocks translated from CISC blocks are held in system memory cache. The efficiency of translation of CISC blocks to RISC blocks in the cache is improved by using small-, equal-sized RISC blocks that are linked into a logical entity. The logical entity is a linked group of one or more RISC blocks logically linked for each CISC block. The logical links from one RISC block to another RISC block are implemented by a linked-list.

Abstract: Legacy instructions of a guest system are dynamically emulated on a host system in blocks using block addresses. Detailed translation information is stored in a translation store. Translation indications for a subset of all the translated blocks are stored into a tracking table at block numbers determined by the block addresses. Each particular legacy instruction of a translated block is translated into one or more translated instructions for emulating the particular legacy instruction. If the particular legacy instruction is a store instruction, the indication in the tracking table is checked for the particular block number to determine if instruction data has been stored. If instruction data has been stored for the particular block number, the translation store is checked to determine if instruction data has been modified. If instruction data has not been stored for the particular block number, the checking of the translation store is bypassed adding to the efficiency of the emulation.

Abstract: A conditional thunk utility employing an assembler-level direct-branch thunk technique. In a condition-check alternative, the conditional thunk utility performs a condition check followed by a direct-branch jump. The condition-check methodology is implemented using an assembler-level direct-branch technique, and the conditional thunk utility does not utilize the stack to queue the arguments of a function call. Thus, the stack is not altered from its desired condition just prior to executing the API function call. The condition-check alternative checks the thunk condition for each function call and, for this reason, may be used when the thunk condition can vary relatively frequently while the host computer system is running. In a jump-table alternative, the conditional thunk utility performs an assembler-level jump table check followed by a direct jump to a target address.

Abstract: A method and apparatus to provide pre-boot security and legacy hardware and environment support for a computing system having an extensible firmware architecture is described. A virtual machine monitor is employed to provide the virtualization of system state for the purposes of running legacy compatibility code or protecting key data and code regions for safety and security. An application may be given access to a subset of the system resources, and access to portions of the memory map not designated for updates would trap (program interrupt) to the VMM. A VMM pre-boot policy agent may then protect state and unload any problematic software.