Analysis Of Code Form Patents (Class 717/141)
  • Patent number: 11366644
    Abstract: Systems and methods for analyzing Robotic Process Automation (RPA) code are provided. A robotic process automation (RPA) file is received by the RPA analysis and review system. The RPA analysis and review system uses a code review configuration which defines coding standards for the RPA files code. RPA data within the RPA file is parsed and received for compliance with coding standards and restructured for rendering in a code-review graphical user interface (GUI). A code-review GUI with the restructured RPA data is then rendered, along with information that includes whether the RPA code was in compliance with the coding standards.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: June 21, 2022
    Assignee: UIPCO, LLC
    Inventors: Emily Kathleen Krebs, Jonathan Aguirre, Brian Scott Funderburk
  • Patent number: 11361246
    Abstract: Various systems and methods provide an intuitive user interface that enables automatic specification of queries and constraints for analysis by ML component. Various implementations provide methodologies for automatically formulating machine learning (“ML”) and optimization queries. The automatic generation of ML and/or optimization queries can be configured to use examples to facilitate formulation of ML and optimization queries. One example method includes accepting input data specifying variables and data values associated with the variables. Within the input data any unspecified data records are identified, and a relationship between the variables specified in the input data and a variable associated with the at least one unspecified data record is automatically determined. The relationship can be automatically determined based on training data contained within the input data. Once a relationship is established a ML problem can be automatically generated.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 14, 2022
    Assignee: DataRobot, Inc.
    Inventor: Michael Schmidt
  • Patent number: 11328021
    Abstract: A method may include searching compiled code for a variable name of a resource, the variable name containing a predefined string; identifying a variable name in a resource manifest of the library that matches the variable name that contains the predefined string; based on the identifying, importing the resource to a location associated with the compiled code.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 10, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Matthew E. Centurion
  • Patent number: 11321094
    Abstract: A non-transitory computer-readable medium having stored therein a program for causing a computer to execute a process. The process includes storing a plurality of generation instructions in a storage area for each of a plurality of first assembly instructions, each generation instruction instructing the generation of a machine language of a second assembly instruction that executes processing equivalent to each first assembly instruction, and generating machine languages of a plurality of second assembly instructions so that the machine languages of the second assembly instructions having a dependency relationship do not appear adjacent to each other, according to the plurality of generation instructions in the storage area.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 3, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Kawakami
  • Patent number: 11307962
    Abstract: A method for validating software transforms. A target program binary is mutated, producing a plurality of variants. It is determined whether each variant passes a test suite. Upon determining the variant does not pass the test suite, the variant is discarded. Upon determining the variant passes the test suite, the variant is compared to the target program binary. A candidate transform is extracted which meets scope criteria. The candidate transform is applied to each of a plurality of test programs. It is determined whether the candidate transform is safe. Upon determining that the candidate transform is not safe, the candidate transform is discarded. Upon determining that the candidate transform is safe, the candidate transform is collected.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 19, 2022
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Jason A. Landsborough, Sunny J. Fugate, Stephen T. Harding
  • Patent number: 11281770
    Abstract: Monitoring statements in a database environment. Substantially all database query statements to be executed against a database in the database environment are analyzed to determine if a statement has an outlier statistic. Database queries that do not have an associated outlier statistic are serviced. Further analysis is performed for statements having an outlier statistic to determine if the corresponding statement poses a security risk to the database environment.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 22, 2022
    Assignee: salesforce.com, Inc.
    Inventor: Mark Wilding
  • Patent number: 11269605
    Abstract: An application can be converted to new programming language or framework. A source application written for a legacy framework is analyzed and divided into smaller segments of code. The smaller segments are evaluated for quality in view of best practices design for writing applications. A rubric is determined for each segment and compared to a best practice threshold. Segments can be evaluated for features that can be passed through a model. The model converts the features into new code adapted for target framework. Machine learning and rules databases are updated with details of the conversion.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 8, 2022
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Prasanth Nandanuru, Andrew J. Garner, IV, Kory Bunya, Eduardo Dela Torre, Dennis Montenegro, Yevanna M. Yejjala, Dinakar Channakal Krishnappa, Chinababu Kona, Sai Krishna Verma Sundaragiri, Priyanka Amara, Shiju Thukalankuzhy John
  • Patent number: 11263377
    Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 1, 2022
    Assignee: Xilinx, Inc.
    Inventors: Amitava Majumdar, Albert Shih-Huai Lin, Partho Tapan Chaudhuri, Niravkumar Patel
  • Patent number: 11250015
    Abstract: Systems and methods for low latency materialized information provision are disclosed. For example, a system may include at least one memory storing instructions and one or more processors configured to execute the instructions to perform operations. The operations may include receiving, via a materialization service, data from multiple sources related to an item associated with a webpage hosted by a server. The data may include first event data sourced from a real-time feed and second event data sourced from stored data. Operations may include generating synchronized data based on the first and second event data. Operations may include receiving a request from the web server for information related to the item, the request being associated with a user segment. Operations may include identifying data to aggregate to fulfill the request, generating a data structure gathering synchronized data using the data structure, and forwarding the gathered synchronized data to the server.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 15, 2022
    Assignee: Coupang Corp.
    Inventors: Prakash Kadel, Du Hyeong Kim, Jun Huang, Chengcheng Shen
  • Patent number: 11250127
    Abstract: A computer includes a memory and a processor programmed to execute instructions stored in the memory. The instructions include filtering dependency code from a binary file to separate the dependency code from custom code in the binary file. The instructions further include evaluating the custom code in the binary file for a security risk.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 15, 2022
    Assignee: Blackberry Limited
    Inventor: Adam John Boulton
  • Patent number: 11244247
    Abstract: Embodiments of the present invention are directed to facilitating concurrent forecasting associating with multiple time series data sets. In accordance with aspects of the present disclosure, a request to perform a predictive analysis in association with multiple time series data sets is received. Thereafter, the request is parsed to identify each of the time series data sets to use in predictive analysis. For each time series data set, an object is initiated to perform the predictive analysis for the corresponding time series data set. Generally, the predictive analysis predicts expected outcomes based on the corresponding time series data set. Each object is concurrently executed to generate expected outcomes associated with the corresponding time series data set, and the expected outcomes associated with each of the corresponding time series data sets are provided for display.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: February 8, 2022
    Assignee: Splunk Inc.
    Inventors: Manish Sainani, Nghi Huu Nguyen, Zidong Yang
  • Patent number: 11240268
    Abstract: Dynamic honeypots for computer program execution environments are described. A determination is made whether a time period has expired since a computer program execution environment, of multiple computer program execution environments, began executing a computer program that provides a user service. The computer program execution environment is changed into a computer security mechanism that counteracts an attempt of unauthorized use of a system that comprises the computer program execution environment, in response to a determination that the time period has expired since the computer program execution environment began executing the computer program that provides the user service.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 1, 2022
    Inventors: Amit Lieberman, Assaf Natanzon, Oron Golan, Raul Shnier
  • Patent number: 11231767
    Abstract: A method for dynamic frequency scaling (DFS) on the electronic systems level (ESL). The method can run in a virtual environment and dynamically scale the frequency of a virtual component based on a first transaction time and a second transaction time.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan Ting, Ashok Mehta, Stanley John, Sandeep Kumar Goel
  • Patent number: 11226888
    Abstract: Systems and methods for function argument checking are disclosed. The systems and methods can use declarations and validation instructions based on the declarations. Validation instructions for a function can be generated automatically from a declaration for the function. The validation instructions can be executed in response to invocation of the function. The validation instructions can include instructions for determining whether an input satisfies a condition on a corresponding argument of the function, instructions for identifying a position of the input, and instructions for providing, in response to determining that the input does not satisfy the condition, an indication of the nonsatisfaction of the condition and the position. The condition can specify a datatype or size for the argument or one or more validation functions for checking the argument.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 18, 2022
    Assignee: The MathWorks, Inc.
    Inventors: Halldor N Stefansson, Bryan T White, David A Foti, Jianzhong Xue
  • Patent number: 11221861
    Abstract: Provided herein are methods, systems, and computer-program products for providing a library of base classes to be used by applications to facilitate real-time analytics. In some examples, the library may be a C++ Library that provides a set of primitive operators (e.g., spout base class, tube base class, and sink base class) for user derivation. In some examples, the spout base class may relate to receiving data from a data source, the tube base class may relate to performing one or more operations on the received data, and the sink base class may relate to sending the processed data to a data target. The spout, tube, sink together provide a real-time streaming framework interface that may be extended by the user.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: January 11, 2022
    Assignee: K&M Systems, Inc.
    Inventors: Alexander Hurd, Kurtis Cahill
  • Patent number: 11216582
    Abstract: Systems, methods, and devices for implementing secure views for zero-copy data sharing in a multi-tenant database system are disclosed. A method includes granting, to one or more cross-accounts, access to a share object comprising a secure view and usage functionality associated with a user-defined function (UDF) to underlying data without providing a view of the procedural logic associated with the UDF.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 4, 2022
    Assignee: Snowflake Inc.
    Inventors: Allison Waingold Lee, Peter Povinec, Martin Hentschel, Robert Muglia
  • Patent number: 11210466
    Abstract: Disclosed is a method and system to obtain a structured grammar, based on a restricted language (e.g., a known subset of a full language such as a computer language) that may assist with automated parsing and correlation of configuration files conforming to the structured grammar. Once obtained, a plurality of different network device configuration documents (e.g., config file information) may be parsed to create a scaffold view using slots for correlated data across the plurality of different network devices. For example, the scaffold view may include populated branches of the scaffold representative of the plurality of different network device configuration documents. Maintaining a correlation of source data to changes in a single view based on the scaffolding may be used to comprehensively view and edit configuration information.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 28, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Frank Wood, Kevin Tajeran, Charles F. Clark, Gurraj Atwal
  • Patent number: 11204759
    Abstract: A method includes, receiving a first version of a software patch for an application. The method further includes receiving a second version of the software patch, the second version being associated with an upstream version of the application. The method further includes, comparing the first version of the software patch with the second version of the software patch, the comparing accounting for differences between the first version of the software patch and the second version of the software patch that result from differences between the application and the upstream version of the application. The method further includes, in response to comparing, tagging the first version of the software patch as a match when there are no differences other than the differences between the first version of the software patch and the second version of the software patch that result from differences between the application and the upstream version of the application.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 21, 2021
    Assignee: RED HAT, INC.
    Inventors: Steven Francis Best, David Bryce Arcari
  • Patent number: 11190209
    Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p?r. The method also includes each column in the p×(k+r) array has an even parity and each line of slope j for 0?j?r?1 in the p×(k+r) array has an even parity. The method includes the lines of slope j taken with a toroidal topology modulo p. A computer program product for encoding an array of (p?1)×k symbols of data into a p×(k+r) array includes a computer readable storage medium having program instructions executable by a computer. The program instructions cause the computer to perform the foregoing method.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven R. Hetzler, Veera W. Deenadhayalan
  • Patent number: 11188316
    Abstract: An embodiment includes executing a code interpretation engine such that the interpretation engine interprets a first portion of a source code that includes a first comparison between a first pair of operands. The embodiment also includes performing, in memory, a first bitwise comparison between a block A1 and a block B1 of the first portion of the source code. The embodiment also speeds up execution of the first portion of the source code responsive to the first bitwise comparison producing a negative result. The embodiment speeds up the first portion by omitting at least one of (i) a second bitwise comparison between a block A2 and a block B2, and (ii) a field-wise comparison between a block A3 and a block B3.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oluwatobi Ajila, Andrew James Craik, Daniel Heidinga, Graham Alan Chapman
  • Patent number: 11093676
    Abstract: Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. The processor Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 17, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Eric W. Schieve
  • Patent number: 11068632
    Abstract: A simulation apparatus includes a memory and a processor. The processor is configured to: acquire a circuit model described in a hardware description language; extract a reading and writing relationship between a process and a register variable included in the circuit model; determine an evaluation order of the process, based on the number of register variables whose extracted relationship satisfies a given condition; and convert, into a blocking variable, a register variable which satisfies the given condition in the determined evaluation order of the process among the register variables included in the circuit model.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 20, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Patent number: 10949179
    Abstract: Methods and computer-readable media are disclosed herein for generating asynchronous runtime compatible applications from non-asynchronous applications. In embodiments, source code for the application that is not compatible with asynchronous processing is examined. The source code is parsed in order to identify unsafe functions that will cause failures of the application when processed in an asynchronous runtime. The source code corresponding to those unsafe functions is modified by adding asynchronous functions and commands to the source code and restructuring the source code. The modified source code may then be provided to an asynchronous runtime environment as the application is now compatible with asynchronous processing.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 16, 2021
    Assignee: CERNER INNOVATION, INC.
    Inventors: Douglas Bailey, Sean Emery, Matthew Homan
  • Patent number: 10951687
    Abstract: Embodiments of the systems described herein can implement one or more processes remotely delivering customized code to a host application and/or computing device. The host application may be configured as an Application Programming Interface with a customized code processing library that may configure the host application to receive further instructions remotely. The host application may be further configured to execute host code and/or third-party code. The host application may be configured to receive remote application logic, after the host application has been installed on a computing device, and to execute the received application logic to alter the behavior of the host application, such as selectively tracking end user interactions.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: TEALIUM INC.
    Inventors: Patrick McWilliams, Jason Lap-Wing Koo, Chad Major Hartman, George Thomas Webster, IV, Son Phi Hoang
  • Patent number: 10936468
    Abstract: A method of enforcing a deployment static code analysis may comprise receiving human-readable code instructions for a customized software application, compiling the human-readable code instructions into machine-executable code instructions, and performing a customized reporting static code analysis of the machine-executable code instructions to identify a critical code error resulting from violation of a pre-set customized rule associated with a pre-defined terminal risk, via a processor. The method may further comprise receiving an instruction, via a network interface device, from a customer, to release the machine-executable code instructions for the customized software application, automatically terminating release of the machine-executable code instructions via the processor, and transmitting a notification to the customer identifying the pre-defined terminal risk, via the network interface device.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: March 2, 2021
    Assignee: BOOMI, INC.
    Inventor: Eric M. Ochlak
  • Patent number: 10915427
    Abstract: An equivalence verification unit (130) judges through equivalence verification, for each of corresponding combinations which are each a combination of a function included in pre-change source code and a function included in post-change source code, whether the functions included in the corresponding combination are equivalent to each other. A partial verification judgment unit (150) judges, for each of inequivalent ones of the corresponding combinations, whether the corresponding combination is a partial verification combination including a function where an inequivalent path, in which an inequivalent function is called, and a non-inequivalent path, in which a non-inequivalent function is called, are both included. A partial verification unit (160) judges, for each of the partial verification combinations, whether the functions included in the partial verification combination are partially equivalent to each other by excluding the inequivalent path and performing the equivalence verification.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Mikiya Yoshida, Makoto Isoda, Kazuki Yonemochi, Masuo Ito, Madoka Baba, Reiya Noguchi
  • Patent number: 10897397
    Abstract: A method for network configuration validation includes identifying a target network to configure wherein the target network includes one or more switches; generating, within a network device configuration editor having a superset of configuration syntax and allowable settings values, a target network configuration for the target network; receiving a target network configuration grammar including configuration syntax and allowable settings values from the target network by interrogating the target network; limiting the superset to the received target network configuration grammar to create a limited superset; comparing the limited superset to the syntax and settings values in the target network configuration; and indicating syntax errors and settings value errors in the target network configuration.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 19, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John A. Powell, David L. Santos, Devon L. Dawson
  • Patent number: 10872043
    Abstract: A microcontroller configured to provide secure integrity checking of code or data stored in the microcontroller is provided. The microcontroller may include a processor, memory devices defining a microcontroller memory space, a security attribution unit defining secure memory region(s) and non-secure memory region(s) in the memory space, integrity check tables indicating storage locations of various code within the microcontroller memory space, and an integrity checking unit. The integrity checking unit may be configured to receive an integrity check request for checking the integrity of a first piece of code stored in the microcontroller memory space, access a first integrity check table that indicates a storage location of the first piece of code, determine whether the first integrity check table and first piece of code are stored in the same memory region; and determine whether to perform the requested integrity check based at least on this determination.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 22, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Laurent Le Goffic, Sylvain Garnier
  • Patent number: 10860763
    Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 10860295
    Abstract: Methods, systems, and computer-readable media for automated detection of ambiguities in software design diagrams are disclosed. One or more graphs are determined that represent a plurality of elements of a design diagram. The one or more graphs comprise a plurality of nodes representing components and a plurality of edges representing relationships between the components. An evaluation of the design diagram with respect to one or more rules is initiated by a rules engine. The evaluation is based (at least in part) on traversal of the one or more graphs. Based (at least in part) on the evaluation, one or more flaws are identified in the design diagram. A modified design diagram is generated that represents remediation of at least a portion of the one or more flaws.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 8, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Raghuveer Ketireddy, Benjamin Richeson, Trevor Tonn
  • Patent number: 10846598
    Abstract: A computer implemented method to determine whether a verification is to be performed of the satisfaction of one or more mapping conditions mapping a first state in a first pattern matching automaton to a second state in the first automaton, the verification being based on patterns matched by a second pattern matching automaton having states corresponding to wildcard symbols in the first automaton, the method comprising: associating, with the first state, a minimum number of patterns required to be matched by the second automaton to satisfy a mapping condition of the state; providing a pattern match counter in association with the second automaton, the counter being arranged to count a number of patterns matched by the second automaton; providing a verifier in association with the first automaton, the verifier being arranged to perform the verification, the verifier being responsive to the counter.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 24, 2020
    Assignee: British Telecommunications Public Limited Company
    Inventor: James Mistry
  • Patent number: 10817289
    Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 27, 2020
    Assignee: NVIDIA Corp.
    Inventors: Siva Hari, Michael Sullivan, Timothy Tsai, Stephen W. Keckler, Abdulrahman Mahmoud
  • Patent number: 10782936
    Abstract: A computer-implemented method for migrating a monolithic legacy software system to a well-defined modular target software architecture includes selecting a method, based on predefined patterns, for transforming the software legacy software system; creating an abstract syntax tree from the legacy software system's source code; from the abstract syntax tree, determining a flow of the source code and any coding violations and coding smells in the legacy software system's source code; using the flow and the coding violations, identifying architecture issues in the legacy software system; scheduling tasks for transforming the legacy software system into the target software architecture; automatically generating new source code according to the target software architecture; and automatically and autonomously refactoring the new source code.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 22, 2020
    Assignee: ARCHITECTURE TECHNOLOGY CORPORATION
    Inventors: Paul Davis, Doug Sweet, Mark Peters
  • Patent number: 10776713
    Abstract: A method for identifying highly-skewed classes using an imperfect annotation of every instance together with a set of features for all instances. The imperfect annotations designate a plurality of instances as belonging to the target rare class and others to the majority class. First, a classifier is trained on the set of features using the imperfect annotation as supervision, to designate each instance to either the rare class or majority class. A combination of the predictions from the trained classifier and the imperfect annotations is then used to classify each instance to either the rare class or majority class. In particular, an instance is classified to the rare class only when both the trained classifier and the imperfect annotation classify the instance to the rare class. Finally, for each instance assigned as a rare class instance by the combination stage, all instances in its neighborhood are re-classified as either rare class or majority class.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: September 15, 2020
    Assignee: Regents of the University of Minnesota
    Inventors: Vipin Kumar, Varun Mithal, Guruprasad Nayak, Ankush Khandelwal
  • Patent number: 10764123
    Abstract: Examples disclosed herein relate to configuring a network switch. In an example, user-defined configuration data may be included in a startup configuration file of a network switch. A token may be defined in the startup configuration file, wherein the token may represent a command for the network switch. The user-defined configuration data included prior to defining the token may be retained in the startup configuration file. In response to an event to restore factory-default configuration data in the network switch, an option may be provided to apply the user-defined configuration data included prior to the token along with the factory-default configuration data to the network switch. In response to selection of the option, the user-defined configuration data included prior to the token may be applied along with the factory-default configuration data to the network switch.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 1, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Madhusudanan Rengarajan, Radhakrishnan Gopal, Sivakumar Murugan
  • Patent number: 10756759
    Abstract: In column domain dictionary compression, column values in one or more columns are tokenized by a single dictionary. The domain of the dictionary is the entire set of columns. A dictionary may not only map a token to a tokenized value, but also to a count (“token count”) of the number of occurrences of the token and corresponding tokenized value in the dictionary's domain. Such information may be used to compute queries on the base table.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 25, 2020
    Assignee: Oracle International Corporation
    Inventors: Tirthankar Lahiri, Chi-Kim Hoang, Dina Thomas, Kirk Meredith Edson, Subhradyuti Sarkar, Mark McAuliffe, Marie-Anne Neimat, Chih-Ping Wang
  • Patent number: 10698667
    Abstract: Systems and methods for a compiler with type inference is described herein. The compiler includes a computer program having one or more variables and context of the variables. The compiler has a type selector to infer a type of the variable using the context of the variable and dereference the variable using the inferred type. Prior to executing the computer program, the compiler carries out a type check of the variable by accessing a recommended type of the variable and comparing the recommended type and the types associated with the context of the variable.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 30, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darius Amir Hodaei, Triinu Viilup
  • Patent number: 10678523
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Patent number: 10664696
    Abstract: Existing software defect text categorization approaches are based on use of supervised/semi-supervised machine learning techniques, which may require significant amount of labeled training data for each class in order to train the classifier model leading to significant amount of human effort, resulting in an expensive process. Embodiments of the present disclosure provide systems and methods for circumventing the problem of dependency on labeled training data and features derived from source code by performing concept based classification of software defect reports. In the present disclosure, semantic similarity between the defect category/type labels and the software defect report(s) is computed and represented in a concept space spanned by corpus of documents obtained from one or more knowledge bases, and distribution of similarity values are obtained.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Tata Consultancy Services Limited
    Inventor: Sangameshwar Suryakant Patil
  • Patent number: 10620926
    Abstract: Embodiments relate to using a local entry point with an indirect call function. More specifically, a linker is provided to generate at application modules that at least partially defines an indirect function call configuration. The linker loads a first address of a function by using a first symbolic reference, and determines that the function pointer value of the first symbolic reference is solely used to perform indirect calls in the same application module, e.g. local-use-only. The linker indicates that the first symbolic reference can be resolved using the local entry point associated with the function, and performs that indirect function call exclusively through the first symbolic reference, thereby reducing execution of operations.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Patent number: 10620925
    Abstract: A method for generating code for queries in a database system includes obtaining a user query in a first programming language, the user query comprising at least one query parameter for selecting data from a content database. The method includes obtaining machine code corresponding to a compiled version of the user query. Obtaining the machine code includes generating code in a second programming language corresponding to a compiled version of the user query, generating byte code defining a plurality of functions corresponding to a compiled version of the code in the second programming language, and obtaining the machine code corresponding to the compiled version of the user query based on the byte code. The method further comprises executing the machine code using the at least one query parameter, thereby returning a result satisfying the at least one query parameter. A related non-transitory computer-readable medium and system are also provided.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 14, 2020
    Assignee: MemSQL, Inc.
    Inventors: Andrew John Paroski, Michael Adams Andrews, Eric Norman Hanson
  • Patent number: 10585653
    Abstract: An execution environment in a computer system supports a declarative programming model where user code is written with a query syntax in a native programming language to express inherent parallelism in terms of data flow. The execution environment translates queries in the user code into a runtime agnostic representation and dynamically selects an execution runtime for executing the runtime agnostic representation.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 10, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Krishnan Varadarajan, Michael L. Chu
  • Patent number: 10552300
    Abstract: A process for testing a program includes: receiving a variable comprising a plurality of input values; producing a plurality of equivalence classes for the input values; producing a representative value per equivalence class; producing, by a processor, a primary covering array comprising a plurality of primary vectors; producing a secondary covering array comprising a plurality of secondary vectors; providing the secondary vectors to the program; and producing a result vector comprising a plurality of result entries to test the program. A computer system for testing the program includes: a memory; and a processor, in communication with the memory, wherein the computer system is configured to perform the process for testing the program. A computer program product for testing the program includes: a non-transitory computer readable storage medium readable by a processor and storing program code for execution by the processor to perform the process.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 4, 2020
    Assignee: UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: D. Richard Kuhn, Raghu N. Kacker
  • Patent number: 10521209
    Abstract: Computer source code maintenance represents a significant aspect of computer systems. Code that was developed for one platform, in one language, may require a significant investment in human effort to port such code to another platform or language. Converting source code to a language-agnostic source code allows a user to view the interaction of various portions of the source code in a unified view. Additionally, the language-agnostic source code may be automatically regenerated by a processor to a different platform or language. As a further benefit, documentation, standards-compliance, security, and/or other non-functional requirements may be provided to further enhance the utility of the original source code.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 31, 2019
    Assignee: PHASE CHANGE SOFTWARE LLC
    Inventor: Steven Bucuvalas
  • Patent number: 10503432
    Abstract: A method, computer program product, and apparatus for buffering data sets are provided. The method includes preparing at least one buffer including a plurality of compression windows. The method also includes receiving a data set. The method further includes writing the received data set into a data region in a first compression window among the plurality of compression windows included in a first buffer among the at least one buffer. The method also includes updating statistics of a statistics region in the first compression window based on the received data set. The method further includes compressing the data set from the data region of the first compression window based on the statistics in the statistics region of the first compression window. The method also includes sending the compressed data set to the data region of the first compression window to replace the received data set.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Yoshimura, Tatsuhiro Chiba
  • Patent number: 10503928
    Abstract: At least some aspects of the present disclosure feature systems and methods for obfuscating data. The method includes the steps of receiving or retrieve an input data stream including a sequence of n-grams, mapping at least some of the sequence of n-grams to corresponding tokens using an obfuscation table, and disposing the corresponding tokens to an output data stream.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: December 10, 2019
    Assignee: 3M Innovative Properties Company
    Inventors: Brian J. Stankiewicz, Eric C. Lobner, Richard H. Wolniewicz, William L. Schofield
  • Patent number: 10432654
    Abstract: Method and system for detecting an unknown undesirable event, such as (but not limited to) a cyber-threat, a cyber-intrusion, a financial fraud event or a monitored process malfunction of breakdown. An exemplary method embodiment comprises obtaining a dataset comprising a plurality n of multidimensional data points with a dimension m?2 wherein each data point is a vector of m features, processing the MDPs using measure-based diffusion maps to embed the MDPs into a lower dimension embedded space, and detecting in the embedded space an abnormal MDP without relying on a signature of a threat, the abnormal MDP being indicative of the unknown undesirable event.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 1, 2019
    Assignee: ThetaRay Ltd.
    Inventors: Amir Averbuch, Gil Shabat, Erez Shabat, David Segev
  • Patent number: 10430435
    Abstract: In a recurring revenue management system, a first unit of data and a second unit of data is received. Content is extracted from the first unit of data and the second unit of data based on one or more parameters of a predefined data object that is part of an asset data model. The extracted content is added to an instance of the predefined data object, and a reference tag with identification information for its associated content is associated with the content extracted from each of the first unit of data and the second unit of data. A duplicate data condition can be detected and resolved by applying a predefined approach to conflict resolution based on the identification information in the reference tags of the content of the first unit of data and the second unit of data. Related methods, systems, and computer program products are also described.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 1, 2019
    Assignee: ServiceSource International, Inc.
    Inventors: Greg Olsen, Ganesh Bell, Ricardo Craft, Chellah Thirunavukkarasu, Lenin Subramanian, Manohar Raghunath, Zheng Chen
  • Patent number: 10409966
    Abstract: A method comprising: carrying out optimization of an item of software in a first intermediate representation; carrying out protection of the item of software in a second intermediate representation different to the first intermediate representation.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 10, 2019
    Assignee: IRDETO B.V.
    Inventors: Yuan Gu, Harold Johnson, Yaser Eftekhari, Bahman Sistany, Robert Durand
  • Patent number: 10402177
    Abstract: Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, at runtime, identifying, by executing an instruction with one or more processors, a first loop iteration that cannot be executed in parallel with a second loop iteration due to a set of conflicting scalar loop operations. The first loop iteration is executed after the second loop iteration. The method also includes sectioning, by executing an instruction with one or more processors, a vector loop into vector partitions including a first vector partition. The first vector partition executes consecutive loop iterations in parallel and the consecutive loop iterations start at the second loop iteration and end before the first loop iteration.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: September 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jayashankar Bharadwaj, Nalini Vasudevan, Albert Hartono, Sara S. Baghsorkhi