Including Graph Or Tree Representation (e.g., Abstract Syntax Tree Or Ast) Patents (Class 717/144)
  • Patent number: 10310861
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Patent number: 10223697
    Abstract: Disclosed is an improved approach for implementing enterprise software systems that addresses the above-described problems with existing systems. The present approach provides an effective and efficient way for defining schemas for services, and to define how to map the schema to particular transactional contexts.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 5, 2019
    Assignee: Oracle International Corporation
    Inventors: Mark David Lewis, Jianfeng Tai, David Wang, Ying Wang, Re Lai
  • Patent number: 10210336
    Abstract: Preliminary program analysis of an executable may be performed. A security vulnerability level of a portion of the executable may be determined based on the preliminary program analysis. The security vulnerability level of the portion may be compared to a security vulnerability threshold. The precision of runtime monitoring of the portion may be tuned based on the comparison.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul Ionescu, Iosif V. Onut, Omer Tripp
  • Patent number: 10198250
    Abstract: According to an example, partitioning based migration of systems to container and micro-service based-platforms may include determining, based on an analysis of source code for an application that is to be partitioned, an entity model corresponding to the application, identifying resources associated with the application, and determining a mapping of the identified resources to entities of the entity model. Further, partitioning based migration of systems to container and micro-service based-platforms may include identifying dependencies for each of the mapped resources, generating dependency and control flow metrics for the application, generating affinity values between the mapped resources, generating a resource affinity graph, determining an affinity score between each of the mapped resources, and generating resource clusters that correspond to partitions of the application.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 5, 2019
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Vibhu Sharma, Sanjay Podder, Kapil Singi
  • Patent number: 10152311
    Abstract: A method for compiling software code comprises scanning call sites within the code to identify a function that is called with at least one constant argument and creating a list of each call site associated with the function and sets of constant arguments passed to the function. If any common subsets of the constant arguments are shared across a plurality of call sites, a size of the function is estimated. selecting any sets of constant arguments that are used only in one call site. The sizes of specialized functions covering sets of constant arguments that are used in only one call site is estimated. The method comprises creating a first set of specialized versions of the function covering one or more sets of constant arguments that are used in only one call site, and if any common subsets of the constant arguments exist, creating a second set of specialized versions of the function.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 11, 2018
    Assignee: QUALCOMM Innovation Center, Inc.
    Inventor: Tobias Edler Von Koch
  • Patent number: 10095511
    Abstract: A current Java project is converted to a Maven project, by scanning the the current Java project to identify a structure of the Java project, generating a project template for the Maven project based on the identified structure of the Java project, arranging files associated with the Java project according to a structure of the project template generated for the Maven project, validating dependencies and linkages associated with a plurality of modules of the current Java project based on corresponding module requirements, generating a Project Object Model (POM) file for each of the modules, generating a root POM file for the Maven project that includes the dependencies, executing a build of the Maven project utilizing the POM files and the root POM file to generate artifacts for the Maven project, and deploying the artifacts in a central repository and a testing environment.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 9, 2018
    Assignee: Amdocs Development Limited
    Inventors: Shomi Sengupta, Sunil Suresh Anvekar
  • Patent number: 10083183
    Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for providing a SPLAY tree, the SPLAY tree including a data structure having one or more nodes, each node having a node name and a node value, determining that a function of a shared library of an in-memory database system has been called, and determining whether the SPLAY tree includes a node corresponding to the function, wherein: if the SPLAY tree includes a node corresponding to the function, reading a function address of the function from the SPLAY tree, and if the SPLAY tree is absent a node corresponding to the function, reading the function address from a computer-readable file.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: September 25, 2018
    Assignee: SAP SE
    Inventor: Ahmad Hassan
  • Patent number: 10078505
    Abstract: A method and system for partial connection of iterations during loop unrolling during compilation of a program by a compiler. Unrolled loop iterations of a loop in the program are selectively connected, including redirecting, to the head of the loop, undesirable edges of a control flow from one iteration to a next iteration of the loop. Merges on a path of hot code are removed to increase a scope for optimization of the program. The head of the loop and a start of a replicated loop body of the loop are equivalent points of the control flow. A sequence of blocks on the path of hot code, unpolluted by a control flow of a path of cold code, is extended during the compilation. Information computed by an optimizer about the hot code in a first iteration is used to further optimize a second iteration, and the loop is further unrolled.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Craik, Vijay Sundaresan
  • Patent number: 10042654
    Abstract: A method for distributing sets of regular expressions to a fixed number of state machine engines includes combining, with a processing device, a plurality of regular expressions into a single compound regular expression, creating a single nondeterministic finite automaton (NFA) including a plurality of NFA states based on the compound regular expression, performing an interference analysis for each pair of NFA states to identify all pairs of NFA states that would potentially interfere in an equivalent deterministic finite automaton (DFA), creating an interference graph representing the regular expressions associated with potentially interfering NFA states based on the results of the interference analysis, and performing a graph coloring algorithm on the interference graph to assign a different color to each represented regular expression in the graph.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Christoph Angerer
  • Patent number: 10025570
    Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Sara S. Baghsorkhi, Christos Margiolas
  • Patent number: 9934270
    Abstract: A source code search comprises a two-pass search. The first pass comprises a topological measure of similarity. The second pass comprises a semantic measure of similarity. The query source code is a user-selected portion of source code. The results may be ranked and output to an I/O device.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Nathan Fontenot, Fionnuala G. Gunter, Michael T. Strosaker, George C. Wilson
  • Patent number: 9904541
    Abstract: Described herein are technologies pertaining to semantic baselining. Correctness conditions of a baseline program are inferred based upon a first static analysis undertaken over the baseline program. The correctness conditions are subsequently inserted into a revision to the baseline program. When a second static analysis is undertaken over the revised program with the correctness conditions inserted therein, warnings inherited from the baseline program are suppressed, while warnings caused by revisions are surfaced to a developer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: February 27, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Manuel Fahndrich, Shuvendu Lahiri, Francesco Logozzo, Sam Blackshear
  • Patent number: 9864518
    Abstract: Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to allocate a memory location for a parameter passed to a callee. The caller is a module that includes a function call to the callee and the callee is a function. The method may include inserting instructions in the callee to allocate a home memory location for the parameter in response to determining that the caller is not configured to allocate a memory location for the parameter. In addition, the method may include inserting instructions in the callee to set the memory location as a home location for the parameter in response to determining that the caller is configured to allocate a memory location for the parameter.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Patent number: 9841975
    Abstract: A method is provided of performing register allocation for at least one program code module. The method includes constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colorable. If it is determined that the constructed restriction graph is not colorable, then the method determines whether at least one alternative form of the at least one program instruction is available, and modifies the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 12, 2017
    Assignee: NXP USA, Inc.
    Inventors: Andreea Florina Nicolescu, Rene Catalin Palalau
  • Patent number: 9811235
    Abstract: Disclosed herein is a system and method for optimizing a developer's ability to find and navigate relevant documents, relationships, and other information related to an identifier in the code they are developing. An inline viewport is presented to the user in response to the user selecting an identifier in the code whereby the user is able to see relevant information related to the identifier in a spatially consistent location with the code they are investigating. The developer further has the ability to cascade the viewports such that multiple levels of depth of relationships can be viewed in the viewport.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: November 7, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Monty Hammontree, Murali Krishna Hosabettu Kamalesha, Brandon Adams, Steven John Clarke, Zachary S Zaiss, David Pugh
  • Patent number: 9798527
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating efficient compiled code. In an example method, a compilation system obtains an un-optimized computational graph comprising a plurality of nodes representing operations and directed edges representing data dependencies. The un-optimized computational graph is analyzed using pattern matching to determine fusable operations that can be fused together into a single fusion operation. The un-optimized computational graph is transformed into an optimized computational graph by replacing the nodes representing the fusable operations in the un-optimized computational graph with a fusion node representing the single fusion operation. The compilation system produces efficient code by translating the fusion node of the optimized computational graph as a call that performs the fused operations.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 24, 2017
    Assignee: Google Inc.
    Inventors: Eli Bendersky, Robert Hundt, Mark Heffernan, Jingyue Wu
  • Patent number: 9760282
    Abstract: Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to allocate a memory location for a parameter passed to a callee. The caller is a module that includes a function call to the callee and the callee is a function. The method may include inserting instructions in the callee to allocate a home memory location for the parameter in response to determining that the caller is not configured to allocate a memory location for the parameter. In addition, the method may include inserting instructions in the callee to set the memory location as a home location for the parameter in response to determining that the caller is configured to allocate a memory location for the parameter.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Patent number: 9753838
    Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ian E. Baker, Kathryn A. Bassin, Steven Kagan, Susan E. Smith
  • Patent number: 9720664
    Abstract: One or more processors determine whether a first procedure within a first program meets a first criterion. The first criterion is included in a plurality of criteria that are configured for pessimistic aliasing. Responsive to the determination, one or more processors determine whether to flag the first procedure for pessimistic aliasing.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Perry, David Tremaine
  • Patent number: 9703537
    Abstract: One or more processors determine whether a first procedure within a first program meets a first criterion. The first criterion is included in a plurality of criteria that are configured for pessimistic aliasing. Responsive to the determination, one or more processors determine whether to flag the first procedure for pessimistic aliasing.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Perry, David Tremaine
  • Patent number: 9652208
    Abstract: An embodiment method of global scope basic-block reordering includes profiling an application having a source code decomposable into a plurality of basic-blocks. The profiling yields a global basic-block sequence. The method also includes generating a hierarchical locality model according to the global basic-block sequence. The method also includes generating a target code according to the hierarchical locality model.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 16, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Pengcheng Li, Ziang Hu, Handong Ye
  • Patent number: 9626156
    Abstract: Provided is an application architecture design method in which an information processing device is used, the method including the steps of: inputting information about dependency relations and design aspects, which are design items regarding modules for running functions, virtual machines for running the modules, and physical machines for running the virtual machines; and executing processing of adapting architecture properly by switching the input information about the dependency relations and the design aspects in matrices in a DSM format, and thereby rearranging allocation of the modules, allocation of the virtual machines, and allocation of the physical machines in stages in the DSM format. As a result, an excellent design solution for architecture suitable for a virtualized environment, a cloud environment deriving, or a similar environment can be derived.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: April 18, 2017
    Assignees: NEC Corporation, Tokyo Metropolitan University, The University of Tokyo
    Inventors: Shigeru Hosono, Koji Kimita, Fumiya Akasaka, Tatsunori Hara, Yoshiki Shimomura, Tamio Arai
  • Patent number: 9607017
    Abstract: Systems and methods for utilizing relation- and query-specific information to specialize DBMS code at runtime based on identifying runtime locally invariant variables. Runtime invariant is often of the form of variables in code that hold values that are constant during a portion of code execution. Micro-specialization is applied to eliminate from the original program unnecessary code such as branching statements that reference local invariant(s) in branch-condition evaluation. The resulting specialized code reduces the code complexity as well as significantly improves the runtime efficiency during code execution.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 28, 2017
    Assignee: THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Saumya K. Debray, Richard T. Snodgrass, Rui Zhang
  • Patent number: 9524148
    Abstract: Provided is a multi-module compilation system for generating execution codes for each of modules in a module system. The multi-module compilation system may include a module identifier configured to analyze a program code of the module system and to identify target modules that execute the program code, a module code generator configured to divide the program code into module codes for each of the target modules and to generate the module codes, and a compiler configured to compile the module codes and to generate execution codes for each of the target modules.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: December 20, 2016
    Assignee: LUXROBO
    Inventors: Seung Bae Son, Sang Hun Oh, Goo Beom Jeoung
  • Patent number: 9495147
    Abstract: Aspects are directed to obtaining context information for a software development task. A method includes finding, in response to designating any one tool component associated with the software development task as a root component, at least one other tool component having an at least one-level link with the root component. Context information is extracted n from the root component and the at least one other tool component. A context set is generated based on the extracted context information.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhang Hong Chen, Fa Hua Jin, Xin Peng Liu
  • Patent number: 9489697
    Abstract: Systems and methods for determining a payment to a contributor are provided herein. Methods may include determining the contributor of a portion of software in a collaborative work; tracking the number of times the portion of software is used in a collaborative work; determining a weighting for each contributed portion of software; and calculating the proportional payment to each contributor based on the weighing and an income from the collaborative work.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 8, 2016
    Assignee: Microroyalties, LLC
    Inventors: David A. Guerrieri, Mario Antonio Guerrieri
  • Patent number: 9489221
    Abstract: A method for automatically analyzing formulas and adding pattern annotations to quantifiers based on a database of common pattern idioms. The method involves matching base pattern inference for Satisfiability Modulo Theories (SMT) solvers. The method uses a database for fault detection in externally supplied pattern annotated formulas. The method also uses matching code trees to mixed second-order pattern matching.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: November 8, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nikolaj S. Bjorner, Leonardo Mendonca de Moura
  • Patent number: 9424043
    Abstract: Systems and methods for enhancing performance of programs implemented on an integrated circuit (IC) are provided. A forward-flow selector may determine a common branch for adding a data set to and removing a data set from. By selecting a common branch for adding and removing a data set, there will be a pipeline stage for data flowing into the branch. Accordingly, the embodiments described herein enhance throughput by increasing the number of datasets that may enter a branched pipeline without stalling.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 23, 2016
    Assignee: Altera Corporation
    Inventors: John Stuart Freeman, Tomasz S. Czajkowski
  • Patent number: 9411565
    Abstract: A method, executed by a computer, for splitting live register ranges includes identifying one or more H pathways comprising one or more H nodes having high register pressure using a backwards data flow in the graph, identifying an L pathway consisting of two or more L nodes using a depth first search, and inserting register splitting instructions for each symbolic register that is live in both the one or more H pathways and the L pathway. The register splitting instructions are inserted at a starting node of the one or more H pathways. Register merging instructions are inserted at an ending node of the one or more H pathways.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventor: Steven J. Perron
  • Patent number: 9329867
    Abstract: This disclosure describes techniques for allocating registers in a computing system that supports vector physical registers. The techniques for allocating registers may allocate physical registers to vector virtual registers based on priority information that is indicative of a relative importance of allocating respective vector virtual registers as vectors rather than scalars. The techniques for allocating registers may involve allocating physical registers to the vector virtual registers in an order that is determined based on the priority information.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sumesh Udayakumaran, Se Jong Oh
  • Patent number: 9274771
    Abstract: Embodiments of the invention provide systems and methods for automatically and adaptively optimizing compilation of application code using a rule-based optimization analyzer (RUBOA) that can command a compiler to apply and adapt optimizations at the code segment level according to gathered performance data. For example, source code can be canonically compiled, and annotations can associate compiled code sections with source code sections. The generated binary can then be executed and monitored to gather performance characteristics. The RUBOA can apply the gathered performance characteristics and annotations to a pre-defined rule set to generate compiler optimizations, each associated with and parametrically tailored to respective source code segments.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 1, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Spiros Kalogeropulos, Partha Tirumalai
  • Patent number: 9201874
    Abstract: A nominal type framework can be configured to efficiently correlate different nominal types together based on a minimum set of common type shapes or structures. In one implementation, a developer identifies a number of different nominal types of interest (source types), and identifies the minimum set of common type shapes to be accessed by an application program. The minimum set of common type shapes can then be used to create an intermediate type (target type) to which each of the other different source types can be mapped. For example, one or more proxies can be created that map shapes of the one or more source types to corresponding shapes of the created target type. The application program created by the developer, in turn, can access, operate on, or otherwise use the mapped data of each different source type through a single target type.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: December 1, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Clemens A. Szyperski, Quetzalcoatl Bradley, Joshua R. Williams, Christopher L. Anderson, Donald F. Box, Jeffrey S. Pinkston, Martin J. Gudgin
  • Patent number: 9098298
    Abstract: The invention pertains to an optimization method for a compiler, comprising providing a model of inter-operand constraints of physical registers of a target-platform of a compilation; and a) providing an intermediate representation of a source code using virtual registers; b) grouping the virtual registers of the intermediate representation based on the model of inter-operand constraints into two or more groups, each group comprising at least one virtual register; c) if for at least one group at least one interference of virtual registers within the group occurs, amending the intermediate representation to resolve at least one interference and jumping to step b); otherwise d) providing a representation of a group interference graph of interferences between the groups; and e) allocating virtual registers to physical registers using a coloring scheme on the representation of the group interference graph.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bogdan F. Ditu, Dragos Badea
  • Patent number: 9038035
    Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: May 19, 2015
    Assignee: Cisco Systems Israel, Inc.
    Inventors: Yuval Shachar, Doron Shamia, Oren Ravoy
  • Patent number: 9038041
    Abstract: A stream processing platform that provides fast execution of stream processing applications within a safe runtime environment. The platform includes a stream compiler that converts a representation of a stream processing application into executable program modules for a safe environment. The platform allows users to specify aspects of the program that contribute to generation of modules that execute as intended. A user may specify aspects to control a type of implementation for loops, order of execution for parallel paths, whether multiple instances of an operation can be performed in parallel or whether certain operations should be executed in separate threads. In addition, the stream compiler may generate executable modules in a way that cause a safe runtime environment to allocate memory or otherwise operate efficiently.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 19, 2015
    Assignee: TIBCO Software, Inc.
    Inventors: Jonathan Salz, Richard S. Tibbetts
  • Patent number: 9032378
    Abstract: The facilitated computation of an available symbol set at code locations in a dynamic language program, in which the program is executed up to a particular halt point for which an available symbol set is to be generated. At the halt point, a type of a value of a particular variable may be used in order to generate the available symbol set. However, at the halt point, the variable does not yet have a value of a useful type (e.g., null or undefined), which is possible in a dynamic language program. Rather than return an error, the principles described herein result in return of an available symbol set anyway. Specifically, the variable had previously been annotated with information representing accessed type information for the variable, even though the variable has not formally been defined. This annotated information may be used to generate the available symbol set.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Charles P. Jazdzewski, Michael C. Fanning
  • Patent number: 9021593
    Abstract: The present invention discloses a XSS detection method for detecting the XSS vulnerabilities in a web page, comprising for each parameter-value pair in a set of parameter-value pairs that can be accepted by the web page: constructing a parameter-value pair in which a dedicated script is inserted; assembling a URL corresponding to the web page based on the parameter-value pair in which a dedicated script is inserted; acquiring the dynamic web page content corresponding to the assembled URL; and simulating the execution of the acquired dynamic web page content, if the dedicated script is executed, it is determined that the processing of the parameter in the web page contains XSS vulnerabilities. The present invention further discloses a corresponding XSS detection device and a web site security scanning system and a web scanning system using such a device.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 28, 2015
    Assignee: NSFOCUS Information Technology Co., Ltd.
    Inventors: Guangxu Liu, Yujie Wen, Da Zhou, Xiaoming Wang, Xiaoxia Liu
  • Patent number: 9015685
    Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
  • Patent number: 9009223
    Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: April 14, 2015
    Assignee: Alacritech, Inc.
    Inventors: Laurence B. Boucher, Stephen E. J. Blightman, Peter K. Craft, David A. Higgen, Clive M. Philbrick, Daryl D. Starr
  • Patent number: 8984498
    Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: March 17, 2015
    Assignee: Nvidia Corporation
    Inventors: Vinod Grover, Bastiaan Joannes Matheus Aarts, Michael Murphy
  • Patent number: 8984499
    Abstract: According to one embodiment, a code optimizer is configured to receive first code having a program loop implemented with scalar instructions to store values of a first array to a second array based on values of a third array and to generate second code representing the program loop using at least one vector instruction. The second code include a shuffle instruction to shuffle elements of the first array based on the third array using a shuffle table in a vector manner, a blend instruction to blend the shuffled elements of the first array using a blend table in a vector manner, and a store instruction to store the blended elements of the first array in the second array.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Tal Uliel, Elmoustapha Ould-Ahmedvall, Bret T. Toll
  • Patent number: 8984485
    Abstract: Use of an Abstract Syntax Tree (AST) to select portions of source code when analyzing the affect of changes in that source code from one version to another. In this way, it is possible to better focus on how changes in the source code, especially changes which only impact limited portion(s) of the source code, affect code quality with respect to measures like code complexity, performance and so on.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hisham E. Elshishiny, Sherif Sabry, Ghada H. Selim, Ossama Shokry
  • Patent number: 8984475
    Abstract: Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: March 17, 2015
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Soo-Jung Ryu, Choon-Ki Jang, Jaejin Lee, Bernhard Egger, Young-Chul Cho
  • Patent number: 8972946
    Abstract: Embodiments of the invention relate to test case maintenance for user interfaces. In one embodiment, user source and test cases are linked for test case maintenance. A link is determined to have been created between a user interface and at least one test script. The test script includes a set of test instructions. The user interface includes a set of user interface elements. Each test instruction is run against the user interface. Mapping information for each test instruction is generated. A change is determined to have occurred in at least one of the user interface and the test script. In response to a change having occurred to the user interface, at least one test instruction affected by the change is identified. In response to a change having occurred to the test script, at least one user interface element affected by the change to the test script is identified.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joel A. Bullard, Arnaldo Carreno-Fuentes, Margaret Cho, Michael G. Collins, Clemens Drews, Jalal U. Mahmud, Mark D. Vickstrom
  • Patent number: 8966438
    Abstract: A system that enables end-users who are not skilled in the art of traditional computer programming to intuitively program, configure and manage computers and devices and/or systems that contain many computers and devices. End-users connect graphical parts using graphical wires using a graphical user interface. The timing of the messages that are carried in the wires that connect the parts is deterministic, consistent and intuitive to the end-user. Parts and their user-configurable features are typically designed, fully tested and certified by the original equipment manufacturer or independent software vendor. This invention relates to ubiquitous computing, a model of human-computer interaction in which information processing has been thoroughly integrated into everyday objects and activities associated with those objects.
    Type: Grant
    Filed: June 2, 2013
    Date of Patent: February 24, 2015
    Inventor: Mark Spencer Chamberlain
  • Patent number: 8966437
    Abstract: A computer based method, system and apparatus specify graphical concrete syntax in a modeling language. The invention system declaratively describes the graphical concrete syntax of a diagram of a subject model. A mapping engine maps between (i) the graphical concrete syntax and (ii) the abstract syntax and corresponding diagram interchange syntax of the subject model. The declarative descriptions define structure of the graphical concrete syntax rather than a rendering (painting) logic of the graphical concrete syntax.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Maged E. Elaasar
  • Publication number: 20150052506
    Abstract: A system that implements a memory management policy at runtime when receiving a syntax tree in response to initiating the compiling of software code identifies a plurality of calls within the syntax tree and modifies each the plurality of calls with a corresponding memory-modified call to create a plurality of memory-modified calls. Each memory-modified call is linked with a memory management class and the modifying occurs during the compiling of the software code. Following modification of each of the plurality of calls, the system compiles the plurality of memory-modified calls to generate a bytecode.
    Type: Application
    Filed: November 22, 2013
    Publication date: February 19, 2015
    Applicant: Oracle International Corporation
    Inventor: James George DRISCOLL
  • Patent number: 8959498
    Abstract: A parallelization method, system and program. A program expressed by a block diagram or the like is divided into strands and a balance in calculation time is made among the strands. The functional blocks are divided into strands and the strand involving the maximum calculation time from a strand set is found. One or more movable blocks in the strand involving the maximum calculation time is found. The next step is obtaining calculation time of each strand after the movable block is moved to the strand in the input or output direction according to its property, and moving the block to a strand most largely reducing the calculation time of the strand having the maximum calculation time before the movement. This process loops until calculation time is no longer reduced. Strands are then transformed into source codes. Source codes are compiled and assigned to separate cores or processors for execution.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hideaki Komatsu, Takeo Yoshizawa
  • Patent number: 8959494
    Abstract: A system and method for performing functional decomposition of a software design to generate a computer-executable finite state machine. Initially, the software design is received in a form wherein functions in the software design are repetitively decomposed into (1) data and control transformations. Included between the functions are control flow indicators which have transformation-selection conditions associated therewith. The data transformations and the control transformations are translated into states in the finite state machine. The transformation-selection conditions associated with the control transformations are translated into state transitions in the finite state machine.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Massively Parallel Technologies Inc.
    Inventor: Kevin D. Howard
  • Patent number: 8954933
    Abstract: Embodiments of the invention relate to test case maintenance for user interfaces. In one embodiment, user source and test cases are linked for test case maintenance. A link is determined to have been created between a user interface and at least one test script. The test script includes a set of test instructions. The user interface includes a set of user interface elements. Each test instruction is run against the user interface. Mapping information for each test instruction is generated. A change is determined to have occurred in at least one of the user interface and the test script. In response to a change having occurred to the user interface, at least one test instruction affected by the change is identified. In response to a change having occurred to the test script, at least one user interface element affected by the change to the test script is identified.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joel A. Bullard, Arnaldo Carreno-Fuentes, Margaret Cho, Michael G. Collins, Clemens Drews, Jalal U. Mahmud, Mark D. Vickstrom