Including Intermediate Code Patents (Class 717/146)
  • Patent number: 7441237
    Abstract: A system and method for interfacing additional translation logic via composer(s) to a compiler to extend the capabilities of the compiler is provided. Generally, composer(s) can be software libraries that provide employment of componentization and polymorphism to compiler add-ons in order to extend compiler capabilities. One or more composers can be accessible to the compilation process by reference(s) made in a source code file. For example, additional translation logic for data types and/or expressions (e.g., markup language) created after compiler design can be made accessible to a compiler via composer(s), thus extending the existing compiler. The present invention mitigates problems associated with conventional compiler extending schemes and affords for compile code optimization without having to consider substantially all of the operations of a single query.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: October 21, 2008
    Assignee: Microsoft Corporation
    Inventors: Matthew J. Warren, Barend H. Venter, Wolfram Schulte, Erik Meijer, Christopher J. Lovett, Chia-Hsun Chen
  • Patent number: 7441238
    Abstract: To meet the current trend in computer programming, a multi-programming-language compiler system is designed to include a compiler framework which creates a general environment in which to carry out compilation and language modules to encapsulate the details of various programming languages. Such a system makes it easy for tool vendors and end users to adapt to a world where computer programs are written in multiple languages. New language modules may be written that add support for new languages to the compiler framework. It may also be possible to extend existing language modules so that a variant on an existing language may be added to the compiler framework. Such a system may also be adapted to permit several different clients to access detailed language information from the compiler framework. These clients may include a standard command-line shell or a sophisticated multi-language integrated development environment.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: October 21, 2008
    Assignee: BEA Systems, Inc.
    Inventor: Kevin Zatloukal
  • Patent number: 7434211
    Abstract: Described is a mechanism that preserves the state of computer system shared resources and/or settings, and ensures that changes thereto are reverted when an application exits. A shared resource change bubble logically surrounds application code that causes system resource and/or setting data to change. The bubble preserves existing data before it gets changed, and restores the data when the application program code exits. In one implementation, the bubble is implemented as a library loaded by the application. In an alternative implementation, the bubble is run in a separate process, whereby the bubble can restore changed data even if the application program crashes. In another implementation, a bubble is automatically run for any application that the user has specified needs a bubble. Multiple settings and states may be preserved in a bubble for multiple applications, allowing changes to be undone and reapplied per application, e.g., whenever focus changes.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: October 7, 2008
    Assignee: Microsoft Corporation
    Inventors: Roger H. Wynn, Michael S. Bernstein, Kamesh Chander Tumsi Dayakar
  • Publication number: 20080244543
    Abstract: A system can include an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of a first register set and a second register set and that no instructions between said register spill instructions modify any of said register spill instructions; a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and a storage module configured to configure storage of associated register spills in memory so said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.
    Type: Application
    Filed: June 4, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventor: Christopher Lapkowski
  • Publication number: 20080243656
    Abstract: A method and system for providing target code to various computer systems. The target code is provided by a service. The service provides a mechanism for third-party developers to submit initial or base code for distribution to end-user computers as target code. The service converts the initial code to target code that is suitable for execution on the end-user computers. When the service receives the request for target code that matches certain requester-specified characteristics, it selects the intermediate code that best matches the requester-specified characteristics. The service then sends the target code to the requester.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 2, 2008
    Inventor: EDWARD BALASSANIAN
  • Patent number: 7426722
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: September 16, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Publication number: 20080216063
    Abstract: A computer implemented method analyzing a first code in a first managed computer language and generating intermediate code in a completed language. The intermediate code into linking code that allows the second code in a second managed runtime language to interact with the first code.
    Type: Application
    Filed: January 24, 2008
    Publication date: September 4, 2008
    Applicant: BEA SYSTEMS, INC.
    Inventor: Boris Krasnoiarov
  • Publication number: 20080216061
    Abstract: An ambiguous usage of a name in a statement of a computer program is resolved at least partially by adding to an entry statement thereof a definition that includes the ambiguously used name followed by constructing a definition-use graph, followed by checking whether or not an edge from the added definition reaches the statement containing the ambiguously used name. If all edges into the ambiguous statement are from the added definition, then the name is deemed to be a function call. If all edges into the ambiguous statement are not from the added definition, then the name is deemed to be a memory access. If some edges into the ambiguous statement are from the added definition but other edges are not, then the statement is flagged as a dual usage.
    Type: Application
    Filed: May 16, 2008
    Publication date: September 4, 2008
    Applicant: AGILITY DESIGN SOLUTIONS INC
    Inventor: John R. Allen
  • Patent number: 7421686
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine, the method employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: September 2, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Publication number: 20080209407
    Abstract: The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds ?1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.
    Type: Application
    Filed: April 25, 2008
    Publication date: August 28, 2008
    Inventors: Hazuki Okabayashi, Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa
  • Patent number: 7409681
    Abstract: An execution apparatus (10) such as a user PC identifies that translation of generic code representation is required (e.g. Java bytecode included or referenced as part of a web page downloaded from a content provider (20)), and requests a translation of the generic code representation from a remote translation apparatus (30), i.e. a translation server. A translated native code version of the generic code representation specific to a particular execution environment (10) is identified and sent from the translation apparatus (30) immediately ready for native execution on the execution apparatus (10) at full native speed. This avoids perceived slow start-up and unresponsiveness associated with interpretation or compilation of generic code representation at the execution apparatus (10).
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 5, 2008
    Assignee: Transitive Limited
    Inventors: John Graham, Alasdair Rawsthorne, Jason Souloglou
  • Patent number: 7409680
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: August 5, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7406683
    Abstract: Interaction between programming languages includes receiving a command from a user, where the command is written in a first programming language. The first programming language is converted to an intermediate language. Translations are performed between the intermediate language and a second programming language to provide interaction between the first and second programming languages.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: July 29, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Satish Kumar Kalidindi, Carl Linder, Rajeev Madan, Kai Wang, Jianren Yang
  • Publication number: 20080163182
    Abstract: Systems and methods for building a program (e.g., a control program) for execution by a programmable controller from a source program are disclosed. The source program, which includes instructions in a high-level programming language (e.g., structured text, C++, Pascal or graphics oriented languages), is separately converted into first and second processor-executable programs. The first and second processor-executable programs are then compared, and if the first and second processor-executable programs are substantially the same, then one of them is sent to the programmable controller. If they are not substantially the same one of them is considered corrupt and the conversion process is aborted. In variations, the source program is simultaneously converted into the first and second processor-executable programs using a diversified collection of hardware and software components.
    Type: Application
    Filed: December 4, 2007
    Publication date: July 3, 2008
    Inventor: Richard E. Breault
  • Patent number: 7386861
    Abstract: A blocking system intercepts communications between a software program and an operating system in order to handle blocking and unblocking of event signals. The blocking system intercepts system calls to the operating system requesting the blocking and unblocking of event signals and keeps track of which event signals are blocked and unblocked without delivering the system calls to the operating system. The blocking system also intercepts event signals from the operating system and only allows unblocked event signals to pass to the software program. Blocked event signals received by the blocking system are discarded until the program unblocks the blocked event signals. After unblocking an event signal, the blocking system determines whether a corresponding event signal was previously received and blocked. If so, the blocking system transmits a signal indicating that the event corresponding to the event signal occurred.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: June 10, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: William B. Buzbee, James S. Mattson, Lacky V. Shah
  • Publication number: 20080127072
    Abstract: In general, in one aspect, the invention relates to a computer readable medium comprising executable instructions for verifying generation of an intermediate representation (IR). The generation of the IR is verified by generating the IR from source code and interpreting the IR to obtain an interpretation result. Interpreting the IR includes encountering a method call in the IR, locating an execution unit corresponding to the method call, executing the execution unit to obtain an execution result, replacing a portion of the IR with the execution result to obtain a reduced IR, and obtaining the interpretation result from the reduced IR. Finally, the interpretation result is compared to an expected result of the source code, wherein the generation of the IR is verified if the interpretation result equals the expected result.
    Type: Application
    Filed: September 7, 2006
    Publication date: May 29, 2008
    Applicant: Sun Microsystems, Inc.
    Inventors: Bernd J.W. Mathiske, David M. Ungar, Mario I. Wolczko, Gregory M. Wright, Matthew L. Seidl
  • Publication number: 20080127140
    Abstract: A method, apparatus and computer program product for minimizing code duplication in a statically typeable language program is presented. A plurality of trees of functional instructions for a program are received, each of the plurality of trees including at least one functional node. The plurality of trees of functional instructions for a program are compared and similar trees of functional instructions are merged to eliminate similar function nodes. A combined module is produced from results of the merging, the combined module having code duplication removed therefrom.
    Type: Application
    Filed: August 7, 2006
    Publication date: May 29, 2008
    Inventors: Dennis A. Quan, Eric David Perkins
  • Patent number: 7376939
    Abstract: Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: May 20, 2008
    Assignee: Xilinx, Inc.
    Inventors: Anshuman Nayak, Malay Haldar, Alok Choudhary, Vikram Saxena, Prithviraj Banerjee
  • Patent number: 7373642
    Abstract: A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: May 13, 2008
    Assignee: Stretch, Inc.
    Inventors: Kenneth M Williams, Albert Wang
  • Patent number: 7356810
    Abstract: A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generating a plurality of expression objects representing fixed values and/or relationships between said fixed values and said variable values according to said program code; said objects being organized into a branched tree-like network having all register objects at the lowest basic root or tree-trunk level of the network with no register object feeding into any other register object.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: April 8, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7353163
    Abstract: A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the target machine (31), suitably using memory locations of the target machine and/or any available target registers. One of the pair (e.g., Reg XA) holds a definitive value at entry into a section (100) of subject code (10) while the other (e.g., Reg XB) holds a speculative value which is updated during translation and execution of that section of code. Exceptions are handled by recovering the conditions of the virtual subject machine (11) upon entry into the section of subject code (100) using the definitive version of each abstract register (i.e., Reg XA).
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: April 1, 2008
    Assignee: Transitive Limited
    Inventors: Alasdair Rawsthorne, John H. Sandham, Jason Souloglou
  • Patent number: 7346900
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. The intermediate representation is generated to include a combination of register objects and expression objects. Register objects represent abstract registers that provide a representation of the state of the first programmable machine based on expected effects of the instructions within the first program code, while expression objects represent elements, such as operations or sub-operations, of the instructions in the first program code. In the intermediate representation, a branched tree-like network is formed in which each register object serves as a basic root of the network and references expression objects to which they relate either directly or indirectly through references from other expression objects.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: March 18, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7340728
    Abstract: The invention relates to a method, system and apparatus for the direct execution of XML-documents by means of decoration of a XML-document, a document type definition (DTD) or their representation as structure tree, respectively, with textual or graphical flow charts. The structure of the XML-document' is reused for, and integrated with, the code processing the XML document.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: March 4, 2008
    Assignee: Applied Formal Methods Institute
    Inventor: Philipp W. Kutter
  • Patent number: 7328431
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: February 5, 2008
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7325230
    Abstract: A system for compiling source programs into machine language programs, comprising: a data type information processing module configured to analyze a definition statement of a fixed-point data type in a source program, acquire data type information of the fixed-point data type; a type-information storage; a variable information processing module configured to analyze a variable declaration statement of the fixed-point data type, acquire variable information; a variable storage; and a code generating module configured to read arithmetic expression data, acquire the type number, acquire the data type information, convert the arithmetic expression data.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: January 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuya Uchida
  • Publication number: 20080005725
    Abstract: A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: George A. Reis, Robert Cohn, Shubhendu S. Mukherjee
  • Patent number: 7316011
    Abstract: An exemplary method includes parsing metadata associated with at least a portion of source code to construct a truncated parse tree; selecting a segment of the truncated parse tree; parsing metadata associated with the selected segment to construct one or more additional parse tree branches; and analyzing the truncated parse tree and the one or more additional parse tree branches. Such an exemplary method optionally includes generating code based, at least in part, on the analyzing and/or optionally includes purging or overwriting memory associated with the one or more additional parse tree branches. Other exemplary methods, devices and/or systems are also disclosed.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 1, 2008
    Assignee: Microsoft Corporation
    Inventors: Sadagopan Rajaram, Devidas Joshi, P. Vasantha Rao
  • Publication number: 20070294679
    Abstract: Methods and apparatus to call native code from a managed code application and to optimize such calls are disclosed. An example method includes converting a first bytecode to a first intermediate representation, receiving a second intermediate representation including a call to a native function and at least one annotation describing the native function, and replacing a portion of the first intermediate representation with a portion of the second intermediate representation to create a third intermediate representation.
    Type: Application
    Filed: July 27, 2006
    Publication date: December 20, 2007
    Inventors: Konstantin Bobrovsky, Vyacheslav Shakin
  • Publication number: 20070277165
    Abstract: A method and system to implement debugging interpreted input is described herein. One or more Intermediate Language (IL) islands are generated. Each IL island maps to one or more lines of source code. The interpreter reads a line of source code and parses the line of source code for a command. Before executing the command, the interpreter may call into the corresponding IL island. The IL island may include a breakpoint that corresponds to a set breakpoint in the mapped one or more lines of source code. The IL island may include a function. When calling the IL island, the interpreter may pass in a function pointer, one or more states of one or more variables, a representation of a call stack, or any other parameters. The IL islands enable a debug tool to do source-level debugging of languages executed by an interpreter without architectural changes to the interpreter.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 29, 2007
    Applicant: Microsoft Corporation
    Inventors: Jonathon Michael Stall, Richard M. Byers, Steve J. Steiner
  • Publication number: 20070277163
    Abstract: Disclosed herein, a method of automatically verifying software code is provided. The method may include generating a logic representation of the software code, identifying a set of well-defined formula sequences in the logic representation of the software code, and verifying the software code based on the set of well-defined formula sequences. Exemplary embodiments of the verification method verify completeness and consistency of the software code and ensure complete code coverage.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 29, 2007
    Applicant: Syver, LLC
    Inventor: Dimiter R. Avresky
  • Patent number: 7284241
    Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
  • Patent number: 7263693
    Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: August 28, 2007
    Assignee: Esmertec AG
    Inventor: Beat Heeb
  • Patent number: 7254809
    Abstract: Methods, compiler apparatus and a computer program product for compiling UPC source code are disclosed. UPC-unique constructs are converted into C-level form. The C-level constructs are inserted into the source code to form a combined code. The combined code is translated into an intermediate form, wherein any surviving UPC-unique components are discarded. All UPC-unique data or statements are converted to a form that can be handled by general compiler architectures, yet retain UPC properties. The resultant intermediate form is converted to compiled machine code. The generation of C-level constructs occurs at a compiler front end module, avoiding difficulties in intermediate code handling.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Manish Kurhekar, Pradeep Varma, Rajkishore Barik
  • Patent number: 7240342
    Abstract: According to one embodiment, systems, apparatus and methods are disclosed for installing a program onto a target machine, executing the program, and responsive to a change in profile data collected while the program executes which exceeds a predetermined threshold, recompiling the program while the target machine is idle.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Jayashankar Bharadwaj, Ravi Narayanaswamy
  • Patent number: 7228531
    Abstract: Methods and apparatus are provided for efficiently implementing a customizable processor core on a programmable chip. Source code provided in a high level language is compiled into intermediate code. The optimizer uses the intermediate code and user parameters to define aspects of the processor architecture. The output is used to generate a model that provides profiling information for additional optimization.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: June 5, 2007
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 7219338
    Abstract: A system and method for multi-language compilation is provided. The system and method provide a mechanism for two or more separately written compiler components to co-operate in the compilation of mixed language compilation units. The system mitigates problems associated with conventional approaches to dealing with embedded code blocks. Extensibility is facilitated through the use of a common compiler infrastructure (CCI) in the form of a base class library. Compilers for specific languages are written as extensions of these classes. Common conventions and a flexible extensibility mechanism facilitate cooperation amongst the compilers.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: May 15, 2007
    Assignee: Microsoft Corporation
    Inventor: Barend H. Venter
  • Patent number: 7216338
    Abstract: To perform conformance checking of a software implementation with a (possibly non-deterministic) specification, a software implementation and a software specification are applied to produce a CT enabled implementation. Nondeterministic choices of the software specification result in assigning a corresponding choice of the CT enabled implementation to a variable. The CT enabled implementation includes a test that the variable then comprises one of the nondeterministic choices of the software specification. To perform conformance testing where the software specification includes ordered steps, and calls to methods of other classes (mandatory calls), a software object is produced and organized such that each step of the software specification has a corresponding code section in the software object.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: May 8, 2007
    Assignee: Microsoft Corporation
    Inventors: Michael Barnett, Wolfram Schulte
  • Patent number: 7213237
    Abstract: This intermediate code execution system has a first subsystem having a first interpreter which corresponds to an instruction set generated during compilation and sequentially interprets and executes instructions included in an intermediate code, a second subsystem having a preprocessing section which applies to the intermediate code preprocessing to substitute an instruction pattern consisting of a plurality of instructions with an alternative instruction, and a second interpreter which corresponds to an instruction set including the alternative instruction and sequentially interprets and executes an instruction code included in the preprocessed intermediate code, and a method analysis section which selects either processing to execute the intermediate code by the first interpreter or processing to apply preprocessing to the intermediate code by the preprocessing section and then execute the intermediate code by the second interpreter.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: May 1, 2007
    Assignee: Aplix Corporation
    Inventor: Tetsuyuki Kobayashi
  • Patent number: 7210133
    Abstract: A program storage medium storing an emulation system for performing dynamic real time translation of first program code written for the first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: April 24, 2007
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7203933
    Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: April 10, 2007
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7203934
    Abstract: A combination of a first programmable machine and an emulation system operable to perform dynamic real time translation of first program code written for the first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: April 10, 2007
    Assignee: Transitive Limited
    Inventors: Jason Souloglou, Alasdair Rawsthorne
  • Patent number: 7197748
    Abstract: Each component binary in a heterogeneous program is translated from a platform-specific instruction set into a set of intermediate representation (IR) instructions that are platform-neutral. The IR instructions are grouped into IR code blocks, the IR code blocks into IR procedures, and the IR procedures into IR components to create an intermediate representation hierarchy for the program. An application program interface is provided that permits user access to the IR hierarchy for instrumentation, optimization, navigation, and manipulation of the IR hierarchy. The transformed IR hierarchy is then translated into platform-specific instructions and output as a modified binary. The user can designate a different platform for the output translation of a code block than the platform for which the code block was originally written. Prologue and epilog code is added to contiguous blocks that are translated into different architectures.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: March 27, 2007
    Assignee: Microsoft Corporation
    Inventors: Ronnie I. Chaiken, Hon Keat W. Chan, Andrew J. Edwards, Gregory A. Eigsti, David M. Gillies, Bruce M. Kuramoto, John A. Lefor, Ken B. Pierce, Amitabh Srivastava, Hoi H. Vo, Gideon A. Yuval
  • Patent number: 7197747
    Abstract: A method and system for compiling a program written in a type-safe language. Instructions are reordered for speculative execution while reducing the execution time of the program. A dependency graph is generated wherein exception dependent arcs are discriminated from arcs of other dependency types. Determination is made whether earliest execution start time of the H-PEI will be earlier when executed with or without a constraint by the exception dependent arc. If it is determined that it will be earlier in the latter case, the instruction sequence including the H-PEI is reordered for speculative execution.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kauaki Ishizaki, Tatshushi Inagaki, Hideaki Komatsu
  • Patent number: 7197512
    Abstract: Methods, systems, and computer program products for converting an object of one type to an object of another type that allow for the runtime operation of the conversion process to be altered or customized. The conversion may occur within an extensible serialization engine that serializes, deserializes, and transforms objects of various types. The runtime operation of the serialization engine is altered by one or more extension routines that implement the desired customizations or extensions, without requiring replacement of other existing routines. Based on type information, identified for an initial object, the object is converted to an intermediate representation which permits runtime modification, including modification of object names, object types, and object data. The intermediate representation of the initial object is modified in accordance with extension routines that alter the runtime operation of the serialization engine, and the intermediate representation is converted to a final object and type.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: March 27, 2007
    Assignee: Microsoft Corporation
    Inventors: Stefan H. Pharies, Sowmy K. Srinivasan, Natasha H. Jethanandani, Yann Erik Christensen, Elena A. Kharitidi, Douglas M. Purdy
  • Patent number: 7181735
    Abstract: An apparatus for facilitating optimization processing in a compiler includes a language-specific-rule table which stores one or more predetermined rules which are specified for one or more programming languages; an analyzing unit which analyzes a program code which includes one or more instructions, and is described in one of the one or more programming languages, based on the one or more predetermined rules, to obtain an analysis result; and an embedding unit which embeds the analysis result in the program code.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Haraguchi, Masakazu Hayashi, Yuji Watanabe
  • Patent number: 7171655
    Abstract: Verification of intermediate language code. In one embodiment, a computer-implemented method first verifies metadata of an intermediate language code for consistency and accuracy, and then verifying the intermediate language code for consistency and accuracy. This latter part in one embodiment is accomplished by performing first a syntactic check of the intermediate language code, and then a semantic check of the intermediate language code.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: January 30, 2007
    Assignee: Microsoft Corporation
    Inventors: Andrew Gordon, Donald Syme, Jonathon Forbes, Vance P. Morrison
  • Patent number: 7159212
    Abstract: Art asset rendering systems and methods in which pre-processing is performed in a compilation process. Geometric data are processed in the compilation process with knowledge of associated shading programs. The data are converted into data structures targeted directly to a target hardware platform, and a code stream is assembled that describes the manipulations required to render these data structures. The compiler includes a front end configured to read the geometric data and attributes (an art asset) output from a 3D modeling package and shaders in a platform independent form and perform platform-independent optimizations, and a back end configured to perform platform-specific optimizations and generate platform-targeted data structures and code streams.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: January 2, 2007
    Assignee: Electronic Arts Inc.
    Inventors: Eric Schenk, Paul Lalonde
  • Patent number: 7155690
    Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Yamashita, Takao Shinsha, Hideaki Fujikake, Toshiaki Kowatari, Tomoya Hirao, Atsushi Ohkuma, Hiroaki Nishi, Michiaki Muraoka
  • Patent number: 7152228
    Abstract: A method for generating source code objects has steps of generating a translation file containing translation logic; inputting the translation file into a code generator; and generating translation source code as a function of the translation file. A system for accessing a database through a translation layer comprising a first database; a translation layer, defined by translation source code; and an application for accessing the first database through the translation layer.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 19, 2006
    Assignee: Science Applications International Corporation
    Inventors: Richard Glenn Goodwin, Michael Andrew Farrar, Marvin Messina, Jason Steele
  • Patent number: 7152229
    Abstract: A workflow code generator for generating executable code for multi-channel and/or multi-modal applications. The code generator may include a parser for reading application input files and creating internal representations of declarative statements within the input files. The code generator may further include a model analyzer, which processes the internal model to detect errors, perform optimization, and prepare for outputting the result. The code generator uses a symbol or mapping table for storing references to resources that have been used by the input application. The code generator assigns code fragments to object patterns, resolves data object references by referring to mapping table, and traverses the objects and emits code assigned to the objects.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 19, 2006
    Assignee: Symbol Technologies, Inc
    Inventors: Kelvin Chong, Srinivas Mandyam, Krishna Vedati