Static (source Or Intermediate Level) Patents (Class 717/152)
  • Patent number: 11650905
    Abstract: Embodiments are disclosed for testing source code changes. The techniques include generating an incremental intermediate representation of a security vulnerability fix to repair an identified security vulnerability of a source code application. The techniques also include merging the incremental intermediate representation with a full intermediate representation of a previous version of the source code application. The techniques further include generating an impact graph based on the merged intermediate representation. Additionally, the techniques include performing a security vulnerability analysis on the security vulnerability fix based on the merged intermediate representation, the impact graph, and the identified security vulnerability. Further, the techniques include updating the security vulnerability analysis by removing one or more findings that are not related to the impact graph.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 16, 2023
    Assignee: International Business Machines Corporation
    Inventor: Babita Sharma
  • Patent number: 11232105
    Abstract: A unified metrics computation platform decouples user-facing query languages from backend execution engines with the help of an intermediate platform-agnostic language, based on relational algebra procedural query language. The user needs to only specify the computation logic at a single place. By leveraging the intermediate language representation, the unified metrics computation platform can execute the same computation logic on multiple execution engines. The unified metrics computation platform unifies batch, nearline and interactive computations by automatically converting existing user defined batch logic into nearline logic. The user is presented with a unified view of the batch and nearline computation results.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 25, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Khai Tran, Harsh Shah, Maneesh Varshney
  • Patent number: 11157250
    Abstract: Computer software development has produced many advances within computer science and in most aspects of modern society. Even with modern quality control, bug finding, and other code checking applications, computer software is often less than ideal. A developer may write code that is functionally accurate but lacks security, documentation, speed, storage, reusability, and/or other elements that may make a segment of software code less than ideal. Identifying equivalent code, within a defined hypothesis strength and/or resource limitation, and, when found, replacing it with a vetted equivalent promotes the deployment of software that is more robust, secure, usable and reusable, and/or satisfies performance or other objectives.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 26, 2021
    Assignee: PHASE CHANGE SOFTWARE LLC
    Inventors: Steven Bucuvalas, Hugolin Bergier
  • Patent number: 10628577
    Abstract: Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a plurality of code signatures corresponding to software files. A list of the identified software files may be created and presented to a user.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 21, 2020
    Assignee: Synopsys, Inc.
    Inventors: Mahshad Koohgoli, Xiaojun Shen, Christopher Potts, Aida Malaki
  • Patent number: 10614018
    Abstract: Disclosed aspects relate to managing a set of compute nodes for processing a stream of tuples using a set of processing elements. The set of compute nodes is structured to include both a first compute node having a first configuration and a second compute node having a second configuration. The first configuration differs from the second configuration. Based on the first configuration and the set of processing elements which includes a first processing element, a determination is made to establish the first processing element on the first compute node and the first processing element is established on the first compute node. In embodiments, based on the second configuration and the set of processing elements which includes a second processing element, a determination is made to establish the second processing element on the second compute node and the second processing element is established on the second compute node.
    Type: Grant
    Filed: May 28, 2016
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bradley W. Fawcett
  • Patent number: 10528565
    Abstract: A system, method, and computer-readable medium for performing a predictive caching operation in which a hit rate is improved by pre executing statements that are predicted based upon previous use patterns. More specifically, by analyzing a stream of statements provided to a server, such as a database server, patterns of usage are detected and based upon these patterns, statements provided to the server are executed before the actual application executes the predicted statements. Thus the application executes faster because the data requested is already cached based upon the predictive execution.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 7, 2020
    Assignee: QUEST SOFTWARE INC.
    Inventors: Daniel T. Wood, Jan Henrik Jonsson
  • Patent number: 10484520
    Abstract: A first participant transmits a clocked data sequence to a second participant of a communication network, wherein one data unit of the data sequence is transmitted per clock cycle by the first participant and wherein the data sequence contains a datagram as a write datagram which contains a header, an intermediate field following the header and a data field following the intermediate header, wherein the header, the intermediate field and the data field in each case have one or more data units. The second participant reads the header of the datagram, defines input data depending on the content of the header within a response time, and records the input data in the datagram while the data sequence passes through the second participant. The length of the intermediate field of the datagram is matched to the clock frequency of the data sequence and the response time of the second participant.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 19, 2019
    Assignee: Beckhoff Automation GmbH
    Inventors: Thorsten Bunte, Holger B├╝ttner, Erik Vonnahme, Dirk Janssen, Thomas Rettig, Hans Beckhoff
  • Patent number: 10474750
    Abstract: Techniques for parsing and execution of data including multiple information classes are described herein. In some examples, a collection of data may include multiple information classes through which the data may be parsed and analyzed. In some examples, the multiple information classes may include a textual character information class, a visual style information class, and an inferred information class, such as may include data identifiable based on information external to the data collection. A plurality of tokens associated with the data collection may be generated. One or more of the plurality of tokens may be organized into a set of instructions. The set of instructions may be provided to a computer program for execution.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: November 12, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Kevin Michael McCormick, David Anthony Leen, Christopher Wiswall Greene
  • Patent number: 10372431
    Abstract: A system decouples the source code language from the eventual execution environment by compiling the source code language into a unified intermediate representation that conforms to a language model allowing both parallel graphical operations and parallel general-purpose computational operations. The intermediate representation may then be distributed to end-user computers, where an embedded compiler can compile the intermediate representation into an executable binary targeted for the CPUs and GPUs available in that end-user device. The intermediate representation is sufficient to define both graphics and non-graphics compute kernels and shaders. At install-time or later, the intermediate representation file may be compiled for the specific target hardware of the given end-user computing system.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 6, 2019
    Assignee: Apple Inc.
    Inventors: Aaftab Munshi, Rahul U. Joshi, Mon P. Wang, Kelvin C. Chiu
  • Patent number: 10261760
    Abstract: Systems and methods trace performance data generated by a hardware synthesis tool chain to model elements of a model. During code generation, an initial in-memory representation is generated for the model. The in-memory representation includes a plurality of nodes that correspond to the model elements. The in-memory representation is subjected to transformations and optimizations creating transitional in-memory representations and a final in-memory representation from which HDL code is generated. A graph builder constructs a genealogy graph that traces the transformations and optimizations. The genealogy graph includes graph objects corresponding to the nodes of the in-memory representations. The synthesis tool chain utilizes the HDL code to perform hardware synthesis. The synthesis tool chain also generates performance data. Utilizing the genealogy graph, the performance data is mapped to the nodes of the initial in-memory representation, and to the elements of the model.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 16, 2019
    Assignee: The MathWorks, Inc.
    Inventor: Yongfeng Gu
  • Patent number: 10255072
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to explicitly specify a first architectural register and is to implicitly indicate at least a second architectural register. The second architectural register is implicitly to be at a higher register number than the first architectural register. The processor also includes an architectural register replacement unit coupled with the decode unit. The architectural register replacement unit is to replace the first architectural register with a third architectural register, and is to replace the second architectural register with a fourth architectural register. The third architectural register is to be at a lower register number than the first architectural register. The fourth architectural register is to be at a lower register number than the second architectural register. Other processors are also disclosed, as are methods and systems.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Mark J. Charney, Robert Valentine, Milind B. Girkar, Ashish Jha, Bret L. Toll, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Jason W. Brandt
  • Patent number: 10223088
    Abstract: One or more processors determine whether a first procedure within a first program meets a first criterion. The first criterion is included in a plurality of criteria that are configured for pessimistic aliasing. Responsive to the determination, one or more processors determine whether to flag the first procedure for pessimistic aliasing.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Perry, David Tremaine
  • Patent number: 10191740
    Abstract: A method performed by a processor includes receiving an instruction. The instruction indicating a source operand, indicating a stride, indicating at least one set of strided data element positions out of all sets of strided data element positions for the indicated stride, and indicating at least one destination packed data register. The method also includes storing, in response to the instruction, for each of the indicated at least one set of strided data element positions, a corresponding result packed data operand, in a corresponding destination packed data register of the processor. Each result packed data operand including a plurality of data elements, which are from the corresponding indicated set of strided data element positions of the source operand. The strided data element positions of the set are separated from one another by integer multiples of the indicated stride. Other methods, processors, systems, and machine readable media are also disclosed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10127160
    Abstract: The present invention relates to methods and systems for binary scrambling, and applications for cybersecurity technology aimed at preventing cyber-attacks.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 13, 2018
    Inventors: Alexander Gounares, Christopher Warwick Fraser, Steven Craig Venema
  • Patent number: 10114750
    Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Robert D. Clancy, Thomas Philip Speier, James Norris Dieffenderfer
  • Patent number: 9990186
    Abstract: A method of compiling a sequence of program instructions, a method of parallel execution of a sequence of program instructions and apparatuses and software supporting such methods are disclosed. The sequence of program instructions is analyzed in terms of basic blocks forming a control flow graph and execution paths through that control flow graph are identified. When more than one execution path leads to a given basic block, or when a loop path is found leading from a given basic block back to the same basic block, a potential convergence point may be identified. A convergence marker is added to the computer program associated with the basic blocks identified in this way and then when the program is executed, the convergence markers found are used to trigger a determination of a subset of the multiple execution threads which are executed following that convergence marker.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Limited
    Inventors: Mohammed Javed Absar, Marco Cornero, Georgia Kouveli, Carl Von Platen
  • Patent number: 9940267
    Abstract: A processing device includes a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions. The processing device further includes a compiler to communicate with the target processor instruction memory, the compiler including: a global variable candidate detection module to identify a global memory access instruction within a set of code regions that use a set of global variable candidates to access a global memory, and a memory access optimization module to modify the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ciprian Arbone, Bogdan Florin Ditu
  • Patent number: 9928112
    Abstract: Embodiments of the present invention provide systems and methods for resource allocation. The systems and methods for resource allocation include: configuring a plan to utilize computer resources; partitioning computer resources; and applying a set of two or more hypervisors, which use a single service processor, to execute the plan to utilize computer resources. The hypervisors facilitate the partitioning of the computer resources, group partitions of the computer resources, control access to nodes, and change node boundaries.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rahul Chandrakar, Saravanan Devendran, Venkatesh Sainath, Amit J. Tendolkar
  • Patent number: 9864590
    Abstract: A method of program compilation to improve parallelism during the linking of the program by a compiler. The method includes converting statements of the program to canonical form, constructing a traversable representation, such as an abstract syntax tree (AST), for each procedure in the program, and traversing the program to construct a graph by making each non-control flow statement and each control structure into at least one node of the graph.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 9, 2018
    Inventor: Loring G. Craymer, III
  • Patent number: 9858054
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ali I Sheikh
  • Patent number: 9785484
    Abstract: Mechanisms for a presentation module to perform distributed interfacing with an application across a plurality of hardware entities. The module identifies the hardware entities that are available to interface with endpoints of an application. The presentation module performs distribution of assignment of hardware entities to interact with the endpoints by, for each of at least some of the hardware entities, determining a subset of endpoints with which the corresponding hardware entities is to interface. Furthermore, the application is operated in that state to thereby detect interaction of at least some of the hardware entities with the application via at least some of the endpoints. Thus, distributed interfacing of hardware entities with an application is facilitated.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: October 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vijay Mital, Robin Abraham, Suraj T. Poozhiyil, Nizam Anuar, Bao Quoc Nguyen, Henry Hun-Li Reid Pan, Darryl E. Rubin
  • Patent number: 9471461
    Abstract: A computer implemented method for maintaining a program's calling context correct even when a monitoring of the program goes out of a scope of a program analysis by validating function call transitions and recovering partial paths before and after the violation of the program's control flow. The method includes detecting a violation of control flow invariants in the software system including validating a source and destination of a function call in the software system, interpreting a pre-violation partial path responsive to a failure of the validating, and interpreting a post violation path after a violation of program flow.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 18, 2016
    Assignee: NEC Corporation
    Inventors: Jungwhan Rhee, Hui Zhang, Nipun Arora, Guofei Jiang, Qiang Zeng
  • Patent number: 9436447
    Abstract: A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 6, 2016
    Assignee: NVIDIA Corporation
    Inventors: Xiangyun Kong, Jian-Zhong Wang, Yuan Lin, Vinod Grover
  • Patent number: 9361207
    Abstract: Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. While executing code that includes the error inject, an indication that an event has been triggered is received, conditions defined in the one or more error inject scenarios are evaluated using the error inject data structure, and, for each of the conditions that evaluates to true, one or more actions defined in the error inject script for the condition are performed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 7, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Cheng-Chung Song
  • Patent number: 9335975
    Abstract: A technique for providing environmental impact information associated with code includes determining, based on execution of the code on a computer system, an environmental impact of a code execution sequence included in the code. A section of the code that is associated with the code execution sequence is then annotated with environmental impact information associated with the environmental impact of the code execution sequence.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rick Allen Hamilton, II, James R. Kozloski, Brian Marshall O'Connell, Clifford Alan Pickover, Keith Raymond Walker
  • Patent number: 9335987
    Abstract: Various embodiments are directed to a computer implemented method for determining a largest common series of statements from one or more sets of ordered statements. A most common statement in the one or more sets of ordered statements is determined. A first order most common sequential statement following each most common statement is determined. The most common statement and the first order most common sequential statement are stored in a data object as the largest common series.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Subhajit Bhuiya, Pramod Chandoria, Vaibhav Srivastava
  • Patent number: 9329977
    Abstract: Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. While executing code that includes the error inject, an indication that an event has been triggered is received, conditions defined in the one or more error inject scenarios are evaluated using the error inject data structure, and, for each of the conditions that evaluates to true, one or more actions defined in the error inject script for the condition are performed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Cheng-Chung Song
  • Patent number: 9311355
    Abstract: A method autonomically refreshes a materialized query table (MQT) in a computer database to improve database performance and utility. In preferred embodiments, the query optimizer autonomically initiates a refresh of MQT depending on an estimated time for the query to access the base tables. In other preferred embodiments, the query optimizer estimates the time for the query to access the base tables and compares it to the estimated time to refresh the MQT to determine whether to refresh the MQT and run the query over the MQT rather than the base tables.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventor: John M. Santosuosso
  • Patent number: 9286327
    Abstract: According to certain aspects, systems and methods are provided for automating recovery of a networked data storage environment. For instance, a system can generate a data recovery package configured to automatically carry out a process for recovering a data storage environment and/or associated data. The content of the particular workflow depends on the data storage environment, and can be defined by a user.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 15, 2016
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Sanjay Harakhchand Kripalani, Parag Gokhale
  • Patent number: 9268841
    Abstract: Systems and methods classify, organize, and retrieve data from a variety of applications based on entities associated with the data. A data classification module is configured to retrieve stored information from a repository. The data classification module is configured to receive a request to retrieve the stored information. The data classification module is configured to search the repository based on the request. Based on the search, the data classification module is configured to retrieved stored information from the repository. The data classification module is configured provide the retrieved information to a requester of the information. For example, the data classification module can be configured to provide the retrieved information in a series of interactive cascading menus.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 23, 2016
    Assignee: Red Hat, Inc.
    Inventors: John R. Mattox, Norman Lee Faus
  • Patent number: 9201758
    Abstract: A method for code analysis comprising steps of inputting program code to an analyzer, assigning an objective quality measure to components of the analyzed code; and displaying graphically the objective quality measures.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 1, 2015
    Assignee: FACEBOOK, INC.
    Inventors: Cristiano Calcagno, Dino S. Distefano
  • Patent number: 9177327
    Abstract: User data and a plurality of micro-segment definitions are received. Each micro-segment definition in the plurality of micro-segment definitions corresponds to one or more offers in an offer provider campaign. Further, a micro-segment parser parses each micro-segment definition from the plurality of micro-segment definitions into a plurality of parsed expression segments that indicate a plurality of micro-segment condition rules. In addition, a compiler compiles the plurality of parsed expression segments into an executable object that indicates a plurality of instructions to determine if the user data matches the plurality of micro-segment definitions. Each micro-segment definition is also serially processed, with a sequential evaluation engine, to apply the plurality of micro-segment condition rules to the user data to determine a match of a user belonging to a micro-segment. Further, the sequential evaluation engine assigns a score to indicate the strength of each match.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: November 3, 2015
    Assignee: Adobe Systems Incorporated
    Inventors: Walter Chang, Geoff Baum
  • Patent number: 9146718
    Abstract: Optimizing compiled code includes finding a portion of the compiled code arising from method calls in a portion of source code that were not chained method calls. Modified code is produced for the portion of the compiled code, wherein the modified code conforms to compiled code that would have arisen from source code having chained calls equivalent to the method calls that were not chained in the portion of the source code.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventor: Berthold M. Lebert
  • Patent number: 9141358
    Abstract: Provided are techniques for parsing source code file into a plurality of functions; generating a ranking corresponding to each of the plurality of functions based upon an order of occurrence in the source code file; generating a weight score corresponding to each of the plurality of functions based upon a weighing factor and the occurrence of a condition corresponding to each of the plurality of functions; and generating an object code file such that the plurality of functions are ordered in the object code file based upon the corresponding rankings and weight scores such during a startup of execution of the object code file a startup time is minimized with respect to an object code file not generated in accordance with the claimed method.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vishal Chittranjan Aslot, Aravinda Prasad
  • Patent number: 9032379
    Abstract: Embodiments include systems and methods for generating an application code binary that exploits new platform-specific capabilities, while maintaining backward compatibility with other older platforms. For example, application code is profiled to determine which code regions are main contributors to the runtime execution of the application. For each hot code region, a determination is made as to whether multiple versions of the hot code region should be produced for different target platform models. Each hot code region can be analyzed to determine if benefits can be achieved by exploiting platform-specific capabilities corresponding to each of N platform models, which can result in between one and N versions of that particular hot code region. Navigation instructions are generated as part of the application code binary to permit a target machine to select appropriate versions of the hot code sections at load time, according to the target machine's capabilities.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 12, 2015
    Assignee: Oracle International Corporation
    Inventors: Spiros Kalogeropulos, Partha P. Tirumalai
  • Patent number: 9021450
    Abstract: A disclosed method includes accessing one or more seeding specifications and a program including computer-readable code and applying the one or more seeding specifications to the program to identify for analysis seeds including strings for corresponding identified string variables. The method includes tracking flows emanating from the identified seeds. The tracking includes computing an integral offset into a tracked string variable for any statements causing such a computation. The tracking also includes providing a string representation based on the computed integral offset, wherein the provided string representation comprises a value of the integral offset and an indication of the corresponding tracked string variable. The tracking further includes modeling string manipulations of the tracked string variables using the string representations. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Salvatore Angelo Guarnieri, Marco Pistoia, Omer Tripp
  • Patent number: 9015685
    Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
  • Patent number: 9015684
    Abstract: A device generates code with a technical computing environment (TCE) based on a model and information associated with a target processor, registers an algorithm with the TCE, automatically sets optimization parameters applied during generation of the code based on the algorithm, executes the generated code, receives feedback based on execution of the generated code, and uses the feedback to automatically update the optimization parameters and to automatically regenerate the code with the TCE until an optimal code is achieved for the target processor.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: The MathWorks, Inc.
    Inventors: David Koh, Murat Belge, Pieter J. Mosterman
  • Patent number: 9009689
    Abstract: Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Hideki Saito Ido, Ernesto Su, John L. Ng, Jin Lin, Xinmin Tian, Robert Y. Geva
  • Patent number: 9009692
    Abstract: A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: April 14, 2015
    Assignee: Oracle America, Inc.
    Inventors: Spiros Kalogeropulos, Partha P. Tirumalai, Yonghong Song
  • Patent number: 9009684
    Abstract: A computer-implemented method and apparatus for transforming code to embedded environments, the method comprising: receiving program code not complying with a limitation of an embedded computing environment; transforming at least part of the program code to modified program code in order for the modified program code to be in compliance with the limitation; and storing the modified program code on a storage device. wherein the modified program code complies with the limitation of the embedded computing environment.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Yishai Feldman, Maayan Goldstein
  • Patent number: 9009691
    Abstract: A system and method for using inline stacks to improve the performance of application binaries is included. While executing a first application binary, profile data may be collected about the application that includes which callee functions are called from the application's callsites and the number of times each inline stack is executed. A context summary map may be created from the collected profile data which shows a summary of the total execution count of all instructions in the callee function for each callsite inlined in the application's normal binary. Using the context summary map, each function callsite's execution count may be compared with a predetermined threshold to determine if the function should be inlined. Then the application's profile may be annotated and a second application binary, an optimized binary, may be generated using the annotated profile.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Google Inc.
    Inventors: Dehao Chen, Xinliang David Li
  • Patent number: 8972959
    Abstract: A method of converting a program code of a program running in multi-thread to a program code which causes fewer lock collisions. The method includes reading the program code into a memory and searching the program code for a first conditional statement making a branch to a path, which is in a synchronized block and has no side effect on the synchronized block; duplicating the path having no side effect to which the branch is made by the searched first conditional statement into the outside of the synchronized block; and adding a second conditional statement into the program code in response to the duplication, wherein the second conditional statement is a conditional statement making a branch to the duplicated path having no side effect. Also provided is a system and an article of manufacture which causes a computer to carry out the steps of the above method.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 8972958
    Abstract: Systems and systems which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Convey Computer
    Inventor: Tony Brewer
  • Publication number: 20150052507
    Abstract: One aspect is a method for compiling optimization of an application and a compiler thereof. The method includes determining could-be-constant variables in source code of the application. Constant variables designated as final constant variables and values of the constant variables are obtained using the could-be-constant variables. The application is compiled using the constant variables and the values of the constant variables.
    Type: Application
    Filed: April 23, 2014
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jin Song Ji, Jian Jiang, Ke Wen Lin, Zhi Peng Liu
  • Publication number: 20150046911
    Abstract: Optimizing compiled code includes finding a portion of the compiled code arising from method calls in a portion of source code that were not chained method calls. Modified code is produced for the portion of the compiled code, wherein the modified code conforms to compiled code that would have arisen from source code having chained calls equivalent to the method calls that were not chained in the portion of the source code.
    Type: Application
    Filed: August 10, 2013
    Publication date: February 12, 2015
    Applicant: International Business Machines Corporation
    Inventor: Berthold M. Lebert
  • Publication number: 20150046913
    Abstract: Embodiments relate to data splitting for multi-instantiated objects. An aspect includes receiving a portion of source code for compilation having a dynamic object to split using object size array data splitting. Another aspect includes replacing all memory allocations for the dynamic object with a total size of an object size array and object field arrays including a predetermined padding. Another aspect includes inserting statements in the source code after the memory allocations to populate the object size array with a value of a number of elements of the object size array. Another aspect includes updating a stride for load and store operations using dynamic pointers. Yet another aspect includes modifying field references by adding a distance between the object size array and the object field array to respective address operations.
    Type: Application
    Filed: June 19, 2014
    Publication date: February 12, 2015
    Inventors: Shimin Cui, Yan Zhang
  • Publication number: 20150046912
    Abstract: The various aspects leverage the novel observation that the number of call sites in code is directly correlated with the code's compile time and provide methods implemented by a compiler operating on a computing device (e.g., a smartphone) for performing inline throttling based on a projected number of call sites in the code that would exist after performing inline expansion. The various aspects enable the compiler to improve the performance of the generated code by aggressive inlining while carefully managing increases in compile time, thereby decreasing the power required to compile the code while increasing performance of the computing device. Thus, by inlining enough call sites to reduce the costs of handling calls while accounting for the costs of inlining, the various aspects provide for an effective balance of short compile times and effective code performance.
    Type: Application
    Filed: August 30, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Christopher A. VICK, Andres Valencia
  • Patent number: 8954943
    Abstract: A method for analyzing data reordering operations in Single Issue Multiple Data source code and generating executable code therefrom is provided. Input is received. One or more data reordering operations in the input are identified and each data reordering operation in the input is abstracted into a corresponding virtual shuffle operation so that each virtual shuffle operation forms part of an expression tree. One or more virtual shuffle trees are collapsed by combining virtual shuffle operations within at least one of the one or more virtual shuffle trees to form one or more combined virtual shuffle operations, wherein each virtual shuffle tree is a subtree of the expression tree that only contains virtual shuffle operations. Then code is generated for the one or more combined virtual shuffle operations.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Kai-Ting Amy Wang, Peng Wu, Peng Zhao
  • Patent number: 8943487
    Abstract: Particular embodiments optimize a C++ function comprising one or more loops for symbolic execution, comprising for each loop, if there is a branching condition within the loop, then rewrite the loop to move the branching condition outside the loop. Particular embodiments may further optimize the C++ function through simplified symbolic expressions and adding constructs forcing delayed interpretation of symbolic expressions during the symbolic execution.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventors: Guodong Li, Sreeranga P. Rajan, Indradeep Ghosh