Optimization Patents (Class 717/151)
  • Patent number: 10831498
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10831501
    Abstract: Disclosed is a method for managing an issue queue for fused instructions and paired instructions in a microprocessor. The method includes dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10810161
    Abstract: Exemplary methods, apparatuses, and systems maintain a plurality of summary data structures corresponding to a plurality of logical file system namespaces representing a plurality of hierarchies of one or more directories having one or more files, each file being stored in the storage system as a plurality of segments in a deduplicated manner. In response to a request to estimate a storage usage by a first of the file system namespace, identify a first of the summary data structures corresponding to the first file system namespace, wherein the first summary data structure stores information summarizing deduplicated segments referenced by one or more files of the first file system namespace. Estimate the storage usage of the first file system namespace based on the first summary data structure and a global summary data structure, wherein the global summary data structure stores information summarizing deduplicated segments referenced by all of the file system namespaces.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 20, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Srikant Varadan, Dheer Moghe, Sazzala Reddy
  • Patent number: 10761819
    Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Zhigang Gong, Wenqing Fu, Peng Li, Can Que, Zhiwen Wu
  • Patent number: 10747513
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10747551
    Abstract: Embodiments of the present disclosure relate to software optimization by identifying unused/obsolete components of a software application. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 18, 2020
    Assignee: SALESFORCE.COM, INC.
    Inventors: Brian Toal, Rahul Shinde
  • Patent number: 10725788
    Abstract: A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jose Yallouz, Arkady Bramnik, Ron Gabor
  • Patent number: 10678557
    Abstract: A predicted profile is generated for target code to be executed on a processor of the computing environment. The predicted profile is based on a profile of sampled code. The sampled code is a different version of code than the target code and is a complex build of modules for which it is difficult to determine which versions of the modules have been profiled. Based on the predicted profile for the target code, a determination is made of predicted execution information for the target code. Based on the determining the predicted execution information for the target code, an action is performed to facilitate processing within the computing environment.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David K. Siegwart, Allan H. Kielstra
  • Patent number: 10671550
    Abstract: A computer-implemented method for offloading a problem having 2n size from processing circuitry to one or more accelerators is disclosed. The processing circuitry and the one or more accelerators include respective memories. In the method, a problem having 2n size is divided into a plurality of units each having 2u size. At least a part of the units is allocated to the one or more accelerators. A determination is made as to whether there is a remaining part of the units to be allocated onto the processing circuitry. A temporary buffer is prepared on each memory of at least the one or more accelerators. The temporary buffer is used for storing a copy of a dependent unit stored on a different memory, during inter-unit calculation.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jun Doi
  • Patent number: 10642644
    Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
  • Patent number: 10599496
    Abstract: Novel tools and techniques for tracing application execution and performance. Some of the tools provide a framework for monitoring the execution and/or performance of applications in an execution chain. In some cases, the framework can accomplish this monitoring with a few simple calls to an application programming interface on an application server. In other cases, the framework can provide for the passing of traceability data in protocol-specific headers of existing inter-application (and/or intra-application) communication protocols.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 24, 2020
    Assignee: Qwest Communications International Inc.
    Inventors: Igor I. Malkiman, Chauncey G. Powis, Tyson Matthew Bunch
  • Patent number: 10592387
    Abstract: An approach is provided in which an information handling system selects a first point in a software program corresponding to a compile-time assumption made by a compiler. The information handling system then selects a set of second points in the software program corresponding to a set of locations at which the compile-time assumption can be violated at runtime. Next, the information handling system starts at the first point and propagates backwards in the software program to identify one or more of the second points that are reached from the backwards propagation. The information handling system then inserts conditional transitions in the software program at each of the identified assumption violation points and executes a compiled version of the software program, resulting in an evaluation of the compile-time assumption at the conditional transitions.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew Craik, Joseph Devin Micheal Papineau, Vijay Sundaresan
  • Patent number: 10585847
    Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 10, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
  • Patent number: 10565010
    Abstract: A ladder program analyzing device that can present information for improving execution efficiency of a ladder program includes a ladder program analyzing unit and a ladder program analysis result displaying unit. The ladder program analyzing unit analyzes a ladder program including a plurality of ladder circuits and prepares an execution priority signal table in which execution priorities of the ladder circuits, reference signals indicating signals input to the ladder circuits, and update signals indicating signals output from the ladder circuits are correlated with each other. The ladder program analysis result displaying unit determines presence or absence of the ladder circuit improvable in execution efficiency by comparing the execution priorities, the reference signals, and the update signals of two of the ladder circuits on the basis of the execution priority signal table and displays the determination result.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: February 18, 2020
    Assignee: FANUC CORPORATION
    Inventors: Toshiyuki Matsuo, Mitsuru Mochizuki
  • Patent number: 10552987
    Abstract: The invention relates to the encoding and decoding of texture mapping data of a textured 3D object. A 3D object is usually represented by connectivity, geometry and property data. The texture data, belonging to the property data, include a texture image; a texture coordinates table having entries, each entry defining coordinates in the texture image; and texture indexes associating each vertex of a polygon in the 3D object with an entry in the texture coordinates table. The present invention proposes to search for and delete entry duplicates from the texture coordinates table. To reduce encoding complexity, the search and deletion are based on the connectivity data. This is to exploit redundancies between the mesh connectivity for the polygons within the 3D object and the texture connectivity for the texture polygons within the texture image.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 4, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Guillaume Laroche, Patrice Onno, Christophe Gisquet
  • Patent number: 10528331
    Abstract: Approaches presented herein enable optimization of a cache of compiled XML Path Language (XPath) expressions by removing variability from XPath expressions. More specifically, XPath expressions are identified that are the same but for one or more hardcoded values. These hardcoded values are identified and replaced in an identified XPath expression with an identifier to form a cache optimized XPath expression that lacks the hardcoded value variability of the identified XPath expressions. This cache optimized XPath expression is inserted into a cache optimized function that receives the hardcoded value as arguments and assigns the received hardcoded value to the identifier in the cache optimized XPath expression. The identified XPath expressions are then rewritten as calls to the cache optimized function or to another function wrapping the cache optimized function.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicholas K. Lincoln, Simon D. Stone
  • Patent number: 10496412
    Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: December 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kurt A. Feiste, Michael J. Genden, Paul M. Kennedy, Dung Q. Nguyen
  • Patent number: 10466985
    Abstract: Apparatus and methods related to compiling software are provided. A computing device can receive software having software-associated instructions for compilation into machine-language instructions. The computing device can perform a class hierarchy analysis to determine a class hierarchy for the software. The computing device can determine whether a particular method call is to be checked for execution as a virtual method call based on the class hierarchy. The computing device can, after determining that the particular method call is to be checked, determine particular machine-language instructions that can include: guarding machine-language instructions for checking a runtime-modifiable deoptimization indicator to determine whether the particular method call is to be executed as a virtual method call, and method-call machine-language instructions for the particular method call. The computing device can provide the particular machine-language instructions to a runtime system.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 5, 2019
    Assignee: Google LLC
    Inventors: Andreas Gampe, Nicolas Geoffray, Mingyao Yang
  • Patent number: 10416976
    Abstract: A configuration definition file created for a certain environment is easily applied to system deployment into another environment. A component information storage unit of a deployment device stores component information including, for each constituent element to constitute a system, setting information independent of deployment tools, and for each combination of each constituent element and each deployment tool available for deploying the constituent element, a deployment process for deploying the constituent element by the deployment tool. The component identification unit identifies, for each constituent element, a deployment process associated with a designated deployment tool, based on the component information. The sequence determination unit determines an execution sequence of the identified deployment processes, based on dependency relationships among the constituent elements.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 17, 2019
    Assignee: NEC CORPORATION
    Inventors: Manabu Nakanoya, Takayuki Kuroda
  • Patent number: 10419586
    Abstract: The present disclosure describes methods, systems, and computer program products for data-centric integration modeling in an application integration system. One computer-implemented method includes receiving, by operation of an integration system, a logic integration program comprising a plurality of logic integration patterns that are defined in a data-centric logic integration language; generating a logical model graph based on the logic integration program, the logical model graph being runtime-independent; converting the logical model graph into a physical model graph, the physical model graph being runtime-specific; and generating logic integration runtime codes executable by the integration system based on the physical model graph.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 17, 2019
    Assignee: SAP SE
    Inventors: Daniel Ritter, Jan Bross
  • Patent number: 10402320
    Abstract: A fused object includes a head and a tail. A head template is not modifiable. A tail template is modifiable. Modifying a tail template includes verifying the validity of a transition from a current tail template to a new tail template. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. A fused object may be associated with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 3, 2019
    Assignee: Oracle International Corporation
    Inventors: John R. Rose, Paul D. Sandoz
  • Patent number: 10360134
    Abstract: A computer-implemented method for determining infeasible conditions is disclosed. The method comprises executing a backward-bounded symbolic analysis on a control flow graph of a dynamic program.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Bardin, Robin David
  • Patent number: 10356176
    Abstract: A system and method access domain information indicating placement domains for an information handling system. The placement domains may include fault domains and optimization domains, wherein an optimization domain includes one or more resources wherein a tier instance for each tier of a multi-tier application service resource can be instantiated such that inter-tier communication is internal to the domain. Tier instances may be placed in accordance with the placement domains to achieve compliance with high availability and performance objectives. Management endpoints corresponding to each resource may be monitored and, responsive to detecting a change in the infrastructure, updated domain information indicative of updated placement domains may be accessed and used to determine whether the placement of the tier instances achieves compliance with the objectives.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Ravikanth Chaganti, Dharmesh M. Patel, Rizwan Ali
  • Patent number: 10268463
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is set to be a default application binary, to be sent to devices requesting the application for a first time, if a percentage of matching application profiles exceeds a threshold. The optimized binary for the application is transmitted to the second device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Patent number: 10268567
    Abstract: Systems, methods, and computer-readable media are disclosed for using managed runtime environment semantics to optimize record and replay frameworks. One method includes: executing, by the computing system, a managed runtime component; interacting, by the computing system, with another system during the execution of the managed runtime component; determining, by the computing system, whether a non-deterministic event is to be logged in event logs during the execution of the managed runtime component; determining, by the computing system when the non-deterministic event is to be logged, whether semantics of the non-deterministic event to be logged includes a predetermined semantic, wherein the predetermined semantic includes one or more of optimistic zero copy actions; and logging, by the computing system when the semantics of the non-deterministic event includes the predetermined semantic, a copy of contents of the non-deterministic event in event logs during the execution of the managed runtime component.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Mark Marron
  • Patent number: 10261825
    Abstract: Disclosed aspects relate to agent flow arrangement management in a distributed commit processing environment. A first set of agent utilization data may be collected with respect to a first commit processing agent. A second set of agent utilization data may be collected with respect to a second commit processing agent. An agent flow arrangement may be determined based on a first value with respect to the first set of agent utilization data exceeding a second value with respect to the second set of agent utilization data. The agent flow arrangement may have the first commit processing agent subsequent to the second commit processing agent. The distributed commit operation may be processed using the agent flow arrangement which has the first commit processing agent subsequent to the second commit processing agent.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua H. Armitage, Michael P. Clarke, John A. W. Kaputin, King-Yan Kwan, Andrew Wright
  • Patent number: 10255048
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10248394
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10241768
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 10235191
    Abstract: Methods and system are disclosed that manage behavior of a graphical user interface associated with an application during a runtime of the application. In one aspect, the graphical user interface (GUI) may be configured with attributes associated with the application by a GUI configuration manager. Upon determining application configuration information, a data field metadata manager may determine data fields to be mapped onto the GUI. The data field metadata manager may read the metadata information associated with the data fields that may include data field attributes and domain values. A GUI metadata manager may retrieve metadata information associated with the mapped data fields. A GUI runtime manager may manage the behavior of the GUI and the data received by the data fields may be saved in a data store in a data format associated with the application.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 19, 2019
    Assignee: SAP SE
    Inventors: Ashok Rao, Avinash Gopala Reddy, Arun Mathew, Sharath Prakash, Anjana Satheesh P K, Shalini Krishnamoorthy, Sona Dalsania, Prarthana Henly Onkar, Mohammed Ziyauddin
  • Patent number: 10223089
    Abstract: A method for partial redundancy elimination with a fixed number of temporaries includes determining local data values of program code that describe a temporary memory location, a set of registers, and a set of basic blocks. The method determines global data values of the program code based on the determined local data values of the program code. The method removes a first load of the temporary memory location in a first basic block in the program code. The method adds a second load on a first edge from a second basic block out of the set of basic blocks to a third basic block out of the set of basic blocks in the program code. The method performs a register move on a second edge from the third basic block to the second basic block in the program code.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Steven J. Perron
  • Patent number: 10120602
    Abstract: A data placement destination determination device enables efficiency improvement of the execution time of a program that is executed in a system mounted with a plurality of memories having differing memory bandwidth. This device includes: a program information acquisition unit acquiring required bandwidth and memory size; a system information acquisition unit acquiring the memory bandwidth and size of a candidate memory at a placement destination; a priority setting unit setting priority based on required bandwidth and priority; a first placement destination determination unit determining a placement destination for the data of the program concerned within a range that does not exceed memory size and bandwidth based on the set priorities; and a second placement destination determination unit determining a placement destination within a range that does not exceed memory size based on the set priorities, the required bandwidth of the program concerned, and the memory bandwidth of the candidate memory.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 6, 2018
    Assignee: NEC CORPORATION
    Inventor: Takamichi Miyamoto
  • Patent number: 10120363
    Abstract: A numerical controller for a machine tool is equipped with a decoding unit for analyzing a machining program and a plurality of auxiliary programs, a command element extraction unit for determining the presence or absence of a relationship between the auxiliary programs, a load computing unit for computing a processing time of the machining program and processing times of the plurality of auxiliary programs, an execution sequence computing unit for computing an execution sequence of the machining program and the plurality of auxiliary programs so as to execute the auxiliary programs that have the relationship with each other within the same execution cycle, and an execution processing unit for executing the machining program and the auxiliary programs in accordance with the computed execution sequence.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 6, 2018
    Assignee: FANUC CORPORATION
    Inventor: Yoshinori Saijo
  • Patent number: 10108405
    Abstract: A memory stores first code that compares a value of a variable with each of three or more comparison values, and that performs branch control in accordance with comparison results. A processor determines a minimum comparison value and a maximum comparison value among the comparison values. The processor converts the first code into second code that compares the value of the variable with the minimum comparison value and the maximum comparison value, and that performs the branch control without performing comparisons with the other comparison values when the value of the variable is less than the minimum comparison value or greater than the maximum comparison value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Miyoshi, Shuichi Chiba
  • Patent number: 10095490
    Abstract: Systems, methods, and computer program products are disclosed including receiving a computer program, compiling the computer program, performing data flow analysis on the computer program to identify accesses to data locations by execution units at compile-time, generating a list of data-flow paths including accesses to one or more of the data locations, determining that more than one of the execution units accesses the same data location based on the list of data-flow paths, determining the existence of a potential vulnerability in at least one of the data-flow paths based at least in part on the determination that more than one of the execution units accesses the same data location, synthesizing a scheduling constraint for the data location based at least in part on the determination of the existence of the potential vulnerability in the at least one of the data-flow paths, and implementing the scheduling constraint for the data location.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marco Pistoia, Omer Tripp
  • Patent number: 10089126
    Abstract: Function exits are instrumented in tail-call optimized code in which calls to target functions and return instructions are replaced by jump instructions. A probe engine identifies a tail-call jump and instruments the jumps to raise an exception. In response to an exception raised at the tail-call jump, an exception handler loads various registers and transferring control to a trampoline, which calls the jump target. After the target function returns, an exit probe is fired when the trampoline itself returns.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: October 2, 2018
    Assignee: VMware, Inc.
    Inventors: Radu Rugina, Ricardo E. Gonzalez, Zheng He, Alok Kataria
  • Patent number: 10067960
    Abstract: A current state of one or more entries in a mapping table that are associated with latch-free updates of a data structure that uses indirection mapping tables is accessed. A transformation of the current state of the one or more entries in the mapping table to a transformed state of the entries in the mapping table, is controlled. The controlling includes initiating an atomic multi-word compare-and-swap (MWCAS) operation on a plurality of words using a hardware transactional memory (HTM) resident in a device processor, and the MWCAS operation is performed using hardware primitive operations of the HTM, via the device processor. A transformation of a current state of the data structure to an updated state of the data structure, is controlled, via the transformation of the current state of the one or more entries in the mapping table to the transformed state of the entries in the mapping table.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Justin Levandoski, Ryan Stutsman, Darko Makreshanski
  • Patent number: 10049130
    Abstract: A method for resolving a potential in-doubt condition of a distributed transaction, is provided. A processor receives a request to commit a transaction for a distributed transaction protocol that includes an applied process, the transaction includes a transfer of a commit decision from a coordinating node to a participating node. The processor checks the service status of the connection to the participating node, and finding the service status of the connection out of service or unavailable, the processor instructs the coordinating node to back-out (rollback) the transaction. Additionally, locality meta-data is used as an indication of reliability of the connection to the participating node, and in response to determining the participating node locality to be a remote network connection, the processor instructs the coordinating node to abort the applied process and send a standard distributed transaction protocol message over unreliable connections.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Brooks, Ian J. Mitchell, Philip I. Wakelin
  • Patent number: 10042746
    Abstract: Techniques and systems for creating a function call graph for a codebase are disclosed. Graph creation includes identifying functions in the codebase by a function signature and representing a function as a first node in the call graph. For that function, identifying call-to functions, call-from functions, and inheritance parents and children, and a base class from the function signature of that function; adding child nodes to the first node based on the identified call-to and call-from functions; for an interface call to a base class method in the function, adding child nodes to the first node based on implementations of an override of the base class method; for an added child node, removing that child node from the first node if a source file that includes an implementation of an override and a source code file that includes the function don't share at least one common binary file.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 7, 2018
    Assignee: Google LLC
    Inventors: Ramakrishna Rajanna, Deepank Gupta, Arul Siva Murugan Velayutham, Abhishek Sheopory, Ankit Agarwal
  • Patent number: 10001978
    Abstract: Operations include (a) identifying bounds corresponding to two or more inference variables corresponding to a nested method invocation context, (b) determining that resolution of a first inference variable can be determined as a function of a resolution of a second inference variable, (c) propagating bounds corresponding to the second inference variable from the nested method invocation context to an outer method invocation context without propagating bounds corresponding to the first inference variable, (d) resolving a constraint set to resolve the second inference variable, and (e) resolving the first inference variable based on the resolution of the second inference variable.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 19, 2018
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, Daniel Smith
  • Patent number: 9977747
    Abstract: Memory performance in a computer system that implements large page mapping is improved even when memory is scarce by identifying page sharing opportunities within the large pages at the granularity of small pages and breaking up the large pages so that small pages within the large page can be freed up through page sharing. In addition, the number of small page sharing opportunities within the large pages can be used to estimate the total amount of memory that could be reclaimed through page sharing.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 22, 2018
    Assignee: VMware, Inc.
    Inventors: Yury Baskakov, Alexander Thomas Garthwaite, Rajesh Venkatasubramanian, Irene Zhang, Seongbeom Kim, Nikhil Bhatia, Kiran Tati
  • Patent number: 9971570
    Abstract: Techniques generate memory-optimization logic for concurrent graph analysis. A computer analyzes domain-specific language logic that analyzes a graph having vertices and edges. The computer detects parallel execution regions that create thread locals. Each thread local is associated with a vertex or edge. For each parallel region, the computer calculates how much memory is needed to store one instance of each thread local. The computer generates instrumentation that determines how many threads are available and how many vertices and edges will create thread locals. The computer generates tuning logic that determines how much memory is originally needed for the parallel region based on how much memory is needed to store the one instance, how many threads are available, and graph size. The tuning logic detects a memory shortage based on the original amount of memory needed exceeding how much memory is available and accordingly adjusts the execution of the parallel region.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 15, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9971579
    Abstract: A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-wook Ahn, Won-sub Kim, Jin-seok Lee, Seung-won Lee
  • Patent number: 9971563
    Abstract: Techniques described and suggested herein include systems and methods for logging execution of code using thread-local output buffers. For example, one or more output buffers are allocated to one or more threads executing on a computing system. A global declaration list containing information relating to log types (e.g., verbose log descriptions, templates for specific variables, and the like) may be implemented, and the global declaration list may be generated as part of an initialization process for some or all of the threads. Log events from executing threads may be stored in the output buffers in a fashion conforming to the global declaration list, and may be retrieved asynchronously relative to the executing threads.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 15, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Juhani Karppanen
  • Patent number: 9966150
    Abstract: A method to program bitcells of a ROM array uses different programming cells for programming the bitcells with a first or second data item. A first bitcell is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array as a flipped or a non-flipped memory in multi-bank instance. All other bitcells located in the same column as the first bitcell and subsequent rows are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Synopsys, Inc.
    Inventors: Anil Singh Rawat, Pritender Singh
  • Patent number: 9967257
    Abstract: A Software-Defined Network (SDN) authorizes Application Programming Interface (API) calls from user SDN applications to user SDN controllers. A user SDN application transfers an embedded code to an authorization SDN controller. The authorization SDN controller translates the embedded code into an SDN controller network address and an SDN application privilege data set. The authorization SDN controller transfers the SDN controller network address to the user SDN application. The authorization SDN controller transfers the SDN application privilege data set to the user SDN controller. The user SDN application transfers an SDN API call to the user SDN controller using the SDN controller network address. The user SDN controller determines if the SDN API call is authorized by the SDN application privilege data set. The user SDN controller services the API call if the SDN API call is authorized and inhibits an unauthorized API call.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 8, 2018
    Assignee: Sprint Communications Company L.P.
    Inventors: Marouane Balmakhtar, Arun Rajagopal
  • Patent number: 9928113
    Abstract: An analyzer (such as a compiler) searches for a program portion that matches a pattern that may suffer from workload imbalance due to nodes with high degrees (i.e., relatively many edges). Such a pattern involves iteration over at least a subset (or all) of the nodes in a graph. If a program portion that matches the pattern is found, then the analyzer determines whether the body of the iteration contains an iteration over edges or neighbors of each node in the subset. If so, then the analyzer transforms the graph analytic program by adding code and, optionally, modifying existing code so that high-degree nodes are processed differently than low-degree nodes. High-degree nodes are processed sequentially while low-degree nodes are processed in parallel. Conversely, edges of high-degree nodes are processed in parallel while edges of low-degree nodes are processed sequentially.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 27, 2018
    Assignee: Oracle International Corporation
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9886251
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9875088
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9841959
    Abstract: Provided are methods and systems for inter-procedural optimization (IPO). A new IPO architecture (referred to as “ThinLTO”) is designed to address the weaknesses and limitations of existing IPO approaches, such as traditional Link Time Optimization (LTO) and Lightweight Inter-Procedural Optimization (LIPO), and become a new link-time-optimization standard. With ThinLTO, demand-driven and summary-based fine grain importing maximizes the potential of Cross-Module Optimization (CMO), which enables as much useful CMO as possible ThinLTO also provides for global indexing, which enables fast function importing; parallelizes some performance-critical but expensive inter-procedural analyses and transformations; utilizes demand-driven, lazy importing of debug information that minimizes memory consumption for the debug build; and allows easy integration of third-party distributed build systems. In addition, ThinLTO may also be implemented using an IPO server, thereby removing the need for the serial step.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 12, 2017
    Assignee: Google LLC
    Inventors: Xinliang David Li, Teresa Louise Johnson, Rong Xu