Optimization Patents (Class 717/151)
  • Patent number: 10419586
    Abstract: The present disclosure describes methods, systems, and computer program products for data-centric integration modeling in an application integration system. One computer-implemented method includes receiving, by operation of an integration system, a logic integration program comprising a plurality of logic integration patterns that are defined in a data-centric logic integration language; generating a logical model graph based on the logic integration program, the logical model graph being runtime-independent; converting the logical model graph into a physical model graph, the physical model graph being runtime-specific; and generating logic integration runtime codes executable by the integration system based on the physical model graph.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 17, 2019
    Assignee: SAP SE
    Inventors: Daniel Ritter, Jan Bross
  • Patent number: 10416976
    Abstract: A configuration definition file created for a certain environment is easily applied to system deployment into another environment. A component information storage unit of a deployment device stores component information including, for each constituent element to constitute a system, setting information independent of deployment tools, and for each combination of each constituent element and each deployment tool available for deploying the constituent element, a deployment process for deploying the constituent element by the deployment tool. The component identification unit identifies, for each constituent element, a deployment process associated with a designated deployment tool, based on the component information. The sequence determination unit determines an execution sequence of the identified deployment processes, based on dependency relationships among the constituent elements.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 17, 2019
    Assignee: NEC CORPORATION
    Inventors: Manabu Nakanoya, Takayuki Kuroda
  • Patent number: 10402320
    Abstract: A fused object includes a head and a tail. A head template is not modifiable. A tail template is modifiable. Modifying a tail template includes verifying the validity of a transition from a current tail template to a new tail template. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. A fused object may be associated with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 3, 2019
    Assignee: Oracle International Corporation
    Inventors: John R. Rose, Paul D. Sandoz
  • Patent number: 10360134
    Abstract: A computer-implemented method for determining infeasible conditions is disclosed. The method comprises executing a backward-bounded symbolic analysis on a control flow graph of a dynamic program.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Bardin, Robin David
  • Patent number: 10356176
    Abstract: A system and method access domain information indicating placement domains for an information handling system. The placement domains may include fault domains and optimization domains, wherein an optimization domain includes one or more resources wherein a tier instance for each tier of a multi-tier application service resource can be instantiated such that inter-tier communication is internal to the domain. Tier instances may be placed in accordance with the placement domains to achieve compliance with high availability and performance objectives. Management endpoints corresponding to each resource may be monitored and, responsive to detecting a change in the infrastructure, updated domain information indicative of updated placement domains may be accessed and used to determine whether the placement of the tier instances achieves compliance with the objectives.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Ravikanth Chaganti, Dharmesh M. Patel, Rizwan Ali
  • Patent number: 10268463
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is set to be a default application binary, to be sent to devices requesting the application for a first time, if a percentage of matching application profiles exceeds a threshold. The optimized binary for the application is transmitted to the second device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Patent number: 10268567
    Abstract: Systems, methods, and computer-readable media are disclosed for using managed runtime environment semantics to optimize record and replay frameworks. One method includes: executing, by the computing system, a managed runtime component; interacting, by the computing system, with another system during the execution of the managed runtime component; determining, by the computing system, whether a non-deterministic event is to be logged in event logs during the execution of the managed runtime component; determining, by the computing system when the non-deterministic event is to be logged, whether semantics of the non-deterministic event to be logged includes a predetermined semantic, wherein the predetermined semantic includes one or more of optimistic zero copy actions; and logging, by the computing system when the semantics of the non-deterministic event includes the predetermined semantic, a copy of contents of the non-deterministic event in event logs during the execution of the managed runtime component.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Mark Marron
  • Patent number: 10261825
    Abstract: Disclosed aspects relate to agent flow arrangement management in a distributed commit processing environment. A first set of agent utilization data may be collected with respect to a first commit processing agent. A second set of agent utilization data may be collected with respect to a second commit processing agent. An agent flow arrangement may be determined based on a first value with respect to the first set of agent utilization data exceeding a second value with respect to the second set of agent utilization data. The agent flow arrangement may have the first commit processing agent subsequent to the second commit processing agent. The distributed commit operation may be processed using the agent flow arrangement which has the first commit processing agent subsequent to the second commit processing agent.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua H. Armitage, Michael P. Clarke, John A. W. Kaputin, King-Yan Kwan, Andrew Wright
  • Patent number: 10255048
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10248394
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10241768
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 10235191
    Abstract: Methods and system are disclosed that manage behavior of a graphical user interface associated with an application during a runtime of the application. In one aspect, the graphical user interface (GUI) may be configured with attributes associated with the application by a GUI configuration manager. Upon determining application configuration information, a data field metadata manager may determine data fields to be mapped onto the GUI. The data field metadata manager may read the metadata information associated with the data fields that may include data field attributes and domain values. A GUI metadata manager may retrieve metadata information associated with the mapped data fields. A GUI runtime manager may manage the behavior of the GUI and the data received by the data fields may be saved in a data store in a data format associated with the application.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 19, 2019
    Assignee: SAP SE
    Inventors: Ashok Rao, Avinash Gopala Reddy, Arun Mathew, Sharath Prakash, Anjana Satheesh P K, Shalini Krishnamoorthy, Sona Dalsania, Prarthana Henly Onkar, Mohammed Ziyauddin
  • Patent number: 10223089
    Abstract: A method for partial redundancy elimination with a fixed number of temporaries includes determining local data values of program code that describe a temporary memory location, a set of registers, and a set of basic blocks. The method determines global data values of the program code based on the determined local data values of the program code. The method removes a first load of the temporary memory location in a first basic block in the program code. The method adds a second load on a first edge from a second basic block out of the set of basic blocks to a third basic block out of the set of basic blocks in the program code. The method performs a register move on a second edge from the third basic block to the second basic block in the program code.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Steven J. Perron
  • Patent number: 10120602
    Abstract: A data placement destination determination device enables efficiency improvement of the execution time of a program that is executed in a system mounted with a plurality of memories having differing memory bandwidth. This device includes: a program information acquisition unit acquiring required bandwidth and memory size; a system information acquisition unit acquiring the memory bandwidth and size of a candidate memory at a placement destination; a priority setting unit setting priority based on required bandwidth and priority; a first placement destination determination unit determining a placement destination for the data of the program concerned within a range that does not exceed memory size and bandwidth based on the set priorities; and a second placement destination determination unit determining a placement destination within a range that does not exceed memory size based on the set priorities, the required bandwidth of the program concerned, and the memory bandwidth of the candidate memory.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 6, 2018
    Assignee: NEC CORPORATION
    Inventor: Takamichi Miyamoto
  • Patent number: 10120363
    Abstract: A numerical controller for a machine tool is equipped with a decoding unit for analyzing a machining program and a plurality of auxiliary programs, a command element extraction unit for determining the presence or absence of a relationship between the auxiliary programs, a load computing unit for computing a processing time of the machining program and processing times of the plurality of auxiliary programs, an execution sequence computing unit for computing an execution sequence of the machining program and the plurality of auxiliary programs so as to execute the auxiliary programs that have the relationship with each other within the same execution cycle, and an execution processing unit for executing the machining program and the auxiliary programs in accordance with the computed execution sequence.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 6, 2018
    Assignee: FANUC CORPORATION
    Inventor: Yoshinori Saijo
  • Patent number: 10108405
    Abstract: A memory stores first code that compares a value of a variable with each of three or more comparison values, and that performs branch control in accordance with comparison results. A processor determines a minimum comparison value and a maximum comparison value among the comparison values. The processor converts the first code into second code that compares the value of the variable with the minimum comparison value and the maximum comparison value, and that performs the branch control without performing comparisons with the other comparison values when the value of the variable is less than the minimum comparison value or greater than the maximum comparison value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Miyoshi, Shuichi Chiba
  • Patent number: 10095490
    Abstract: Systems, methods, and computer program products are disclosed including receiving a computer program, compiling the computer program, performing data flow analysis on the computer program to identify accesses to data locations by execution units at compile-time, generating a list of data-flow paths including accesses to one or more of the data locations, determining that more than one of the execution units accesses the same data location based on the list of data-flow paths, determining the existence of a potential vulnerability in at least one of the data-flow paths based at least in part on the determination that more than one of the execution units accesses the same data location, synthesizing a scheduling constraint for the data location based at least in part on the determination of the existence of the potential vulnerability in the at least one of the data-flow paths, and implementing the scheduling constraint for the data location.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marco Pistoia, Omer Tripp
  • Patent number: 10089126
    Abstract: Function exits are instrumented in tail-call optimized code in which calls to target functions and return instructions are replaced by jump instructions. A probe engine identifies a tail-call jump and instruments the jumps to raise an exception. In response to an exception raised at the tail-call jump, an exception handler loads various registers and transferring control to a trampoline, which calls the jump target. After the target function returns, an exit probe is fired when the trampoline itself returns.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: October 2, 2018
    Assignee: VMware, Inc.
    Inventors: Radu Rugina, Ricardo E. Gonzalez, Zheng He, Alok Kataria
  • Patent number: 10067960
    Abstract: A current state of one or more entries in a mapping table that are associated with latch-free updates of a data structure that uses indirection mapping tables is accessed. A transformation of the current state of the one or more entries in the mapping table to a transformed state of the entries in the mapping table, is controlled. The controlling includes initiating an atomic multi-word compare-and-swap (MWCAS) operation on a plurality of words using a hardware transactional memory (HTM) resident in a device processor, and the MWCAS operation is performed using hardware primitive operations of the HTM, via the device processor. A transformation of a current state of the data structure to an updated state of the data structure, is controlled, via the transformation of the current state of the one or more entries in the mapping table to the transformed state of the entries in the mapping table.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Justin Levandoski, Ryan Stutsman, Darko Makreshanski
  • Patent number: 10049130
    Abstract: A method for resolving a potential in-doubt condition of a distributed transaction, is provided. A processor receives a request to commit a transaction for a distributed transaction protocol that includes an applied process, the transaction includes a transfer of a commit decision from a coordinating node to a participating node. The processor checks the service status of the connection to the participating node, and finding the service status of the connection out of service or unavailable, the processor instructs the coordinating node to back-out (rollback) the transaction. Additionally, locality meta-data is used as an indication of reliability of the connection to the participating node, and in response to determining the participating node locality to be a remote network connection, the processor instructs the coordinating node to abort the applied process and send a standard distributed transaction protocol message over unreliable connections.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Brooks, Ian J. Mitchell, Philip I. Wakelin
  • Patent number: 10042746
    Abstract: Techniques and systems for creating a function call graph for a codebase are disclosed. Graph creation includes identifying functions in the codebase by a function signature and representing a function as a first node in the call graph. For that function, identifying call-to functions, call-from functions, and inheritance parents and children, and a base class from the function signature of that function; adding child nodes to the first node based on the identified call-to and call-from functions; for an interface call to a base class method in the function, adding child nodes to the first node based on implementations of an override of the base class method; for an added child node, removing that child node from the first node if a source file that includes an implementation of an override and a source code file that includes the function don't share at least one common binary file.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 7, 2018
    Assignee: Google LLC
    Inventors: Ramakrishna Rajanna, Deepank Gupta, Arul Siva Murugan Velayutham, Abhishek Sheopory, Ankit Agarwal
  • Patent number: 10001978
    Abstract: Operations include (a) identifying bounds corresponding to two or more inference variables corresponding to a nested method invocation context, (b) determining that resolution of a first inference variable can be determined as a function of a resolution of a second inference variable, (c) propagating bounds corresponding to the second inference variable from the nested method invocation context to an outer method invocation context without propagating bounds corresponding to the first inference variable, (d) resolving a constraint set to resolve the second inference variable, and (e) resolving the first inference variable based on the resolution of the second inference variable.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 19, 2018
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, Daniel Smith
  • Patent number: 9977747
    Abstract: Memory performance in a computer system that implements large page mapping is improved even when memory is scarce by identifying page sharing opportunities within the large pages at the granularity of small pages and breaking up the large pages so that small pages within the large page can be freed up through page sharing. In addition, the number of small page sharing opportunities within the large pages can be used to estimate the total amount of memory that could be reclaimed through page sharing.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 22, 2018
    Assignee: VMware, Inc.
    Inventors: Yury Baskakov, Alexander Thomas Garthwaite, Rajesh Venkatasubramanian, Irene Zhang, Seongbeom Kim, Nikhil Bhatia, Kiran Tati
  • Patent number: 9971570
    Abstract: Techniques generate memory-optimization logic for concurrent graph analysis. A computer analyzes domain-specific language logic that analyzes a graph having vertices and edges. The computer detects parallel execution regions that create thread locals. Each thread local is associated with a vertex or edge. For each parallel region, the computer calculates how much memory is needed to store one instance of each thread local. The computer generates instrumentation that determines how many threads are available and how many vertices and edges will create thread locals. The computer generates tuning logic that determines how much memory is originally needed for the parallel region based on how much memory is needed to store the one instance, how many threads are available, and graph size. The tuning logic detects a memory shortage based on the original amount of memory needed exceeding how much memory is available and accordingly adjusts the execution of the parallel region.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 15, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9971579
    Abstract: A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-wook Ahn, Won-sub Kim, Jin-seok Lee, Seung-won Lee
  • Patent number: 9971563
    Abstract: Techniques described and suggested herein include systems and methods for logging execution of code using thread-local output buffers. For example, one or more output buffers are allocated to one or more threads executing on a computing system. A global declaration list containing information relating to log types (e.g., verbose log descriptions, templates for specific variables, and the like) may be implemented, and the global declaration list may be generated as part of an initialization process for some or all of the threads. Log events from executing threads may be stored in the output buffers in a fashion conforming to the global declaration list, and may be retrieved asynchronously relative to the executing threads.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 15, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Juhani Karppanen
  • Patent number: 9966150
    Abstract: A method to program bitcells of a ROM array uses different programming cells for programming the bitcells with a first or second data item. A first bitcell is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array as a flipped or a non-flipped memory in multi-bank instance. All other bitcells located in the same column as the first bitcell and subsequent rows are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Synopsys, Inc.
    Inventors: Anil Singh Rawat, Pritender Singh
  • Patent number: 9967257
    Abstract: A Software-Defined Network (SDN) authorizes Application Programming Interface (API) calls from user SDN applications to user SDN controllers. A user SDN application transfers an embedded code to an authorization SDN controller. The authorization SDN controller translates the embedded code into an SDN controller network address and an SDN application privilege data set. The authorization SDN controller transfers the SDN controller network address to the user SDN application. The authorization SDN controller transfers the SDN application privilege data set to the user SDN controller. The user SDN application transfers an SDN API call to the user SDN controller using the SDN controller network address. The user SDN controller determines if the SDN API call is authorized by the SDN application privilege data set. The user SDN controller services the API call if the SDN API call is authorized and inhibits an unauthorized API call.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 8, 2018
    Assignee: Sprint Communications Company L.P.
    Inventors: Marouane Balmakhtar, Arun Rajagopal
  • Patent number: 9928113
    Abstract: An analyzer (such as a compiler) searches for a program portion that matches a pattern that may suffer from workload imbalance due to nodes with high degrees (i.e., relatively many edges). Such a pattern involves iteration over at least a subset (or all) of the nodes in a graph. If a program portion that matches the pattern is found, then the analyzer determines whether the body of the iteration contains an iteration over edges or neighbors of each node in the subset. If so, then the analyzer transforms the graph analytic program by adding code and, optionally, modifying existing code so that high-degree nodes are processed differently than low-degree nodes. High-degree nodes are processed sequentially while low-degree nodes are processed in parallel. Conversely, edges of high-degree nodes are processed in parallel while edges of low-degree nodes are processed sequentially.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 27, 2018
    Assignee: Oracle International Corporation
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9886251
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9875088
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9841959
    Abstract: Provided are methods and systems for inter-procedural optimization (IPO). A new IPO architecture (referred to as “ThinLTO”) is designed to address the weaknesses and limitations of existing IPO approaches, such as traditional Link Time Optimization (LTO) and Lightweight Inter-Procedural Optimization (LIPO), and become a new link-time-optimization standard. With ThinLTO, demand-driven and summary-based fine grain importing maximizes the potential of Cross-Module Optimization (CMO), which enables as much useful CMO as possible ThinLTO also provides for global indexing, which enables fast function importing; parallelizes some performance-critical but expensive inter-procedural analyses and transformations; utilizes demand-driven, lazy importing of debug information that minimizes memory consumption for the debug build; and allows easy integration of third-party distributed build systems. In addition, ThinLTO may also be implemented using an IPO server, thereby removing the need for the serial step.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 12, 2017
    Assignee: Google LLC
    Inventors: Xinliang David Li, Teresa Louise Johnson, Rong Xu
  • Patent number: 9792432
    Abstract: Methods and apparatuses are provided for automatically optimizing application program code for minimized access to privacy data. A privacy-oriented code optimizing module process and/or facilitate a processing one or more code segments, one or more execution logs associated with the one or more code segments, or a combination thereof to determine at least one privacy intrusion signature associated with the one or more code segments. Further, the privacy-oriented code optimizing module determines one or more recommendations for one or more alternate code segments based, at least in part, on the at least one privacy intrusion signature.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 17, 2017
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Igor Bilogrevic, Kevin Huguenin
  • Patent number: 9778942
    Abstract: Disclosed are various embodiments for generating a replacement binary for emulation of an application. A computer ingests native object code and identifies a central processing unit (CPU) from the native object code. The computer transforms the native object code to produce replacement object code. When executed on the computing device, the replacement code invokes an emulator for the CPU to execute the native code.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Amazon Technologies, Inc.
    Inventor: Venelin N. Efremov
  • Patent number: 9760357
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9747086
    Abstract: Extractable annotations are created and stored for different transmission points. In some instances, this occurs during compiling. One type of transmission point is a message being passed to another process. Once the transmission point is identified, a pattern defining output for the transmission point is then identified. A first extractable annotation defining the first patter is then created and stored for subsequent use.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Charles D. Garrett
  • Patent number: 9727319
    Abstract: A method for significantly reducing compilation time of an application program is provided for compiling the program using profile-directed feedback (PDF). The method applies an additional analysis process between a training run of the application program and a whole program compilation of the application. This analysis process examines a PDF profile file(s) produced during the training run and aggregates data from the PDF file to determine a maximum block counter associated with each source file of the application. Only those source files having maximum block counters in a specified top percent of all the source files of the application have their fat binaries included in the whole program compilation.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shimin Cui, William G. O'Farrell, Graham K. Yiu
  • Patent number: 9710264
    Abstract: A method for performing data flow analysis of computer code, comprising: providing computer code of a computer program having a plurality of user interface screens; dividing the computer code to a plurality of portions such that each one of the portions includes code for inducing at least one of loading and using one of the user interface screens; performing a variable usage analysis to detect which variables are at least one of calculated and used in each one of the portions; constructing a data dependence model defining dependencies among the portions based on the variable usage analysis; and identifying, for at least one of the portions and using the data dependence model, at least one unnecessary variable loaded in one of the user interface screens and not used in a respective portion and in a group of portions depending on the respective portion.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Idan Ben-Harrush
  • Patent number: 9684514
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684515
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684497
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9634912
    Abstract: Provided is a computer, comprising a memory which stores a program and a processor which executes the program which is stored in the memory for each predetermined processing unit, with which a computer resource usage is calculated by a process which is executed for each predetermined processing unit. The computer resources include overlapping resources which are used in an overlapping manner when the program is executed and non-overlapping resources which are not used in an overlapping manner when the program is executed. When calculating the computer resource usage by the process which is executed for each predetermined processing unit, the processor determines, by analyzing the computer resources, the overlapping resources which are used by the process and the non-overlapping resources which are used by the process, and calculates the computer resource usage by the process on the basis of the result of the determination.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 25, 2017
    Assignee: Hitachi, Ltd.
    Inventor: Masanobu Yamada
  • Patent number: 9626256
    Abstract: A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9626169
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9619345
    Abstract: A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9606783
    Abstract: In a method for dynamically replacing code within a software application on a device, an annotated code segment that performs a function according to a first data policy is received. The computer determines an alternate segment that performs the function according to a second data policy.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Radha M. De, Brian M. O'Connell, Cheranellore Vasudevan
  • Patent number: 9588801
    Abstract: An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Irina Calciu, Justin E Gottschlich, Tatiana Shpeisman, Gilles A Pokam
  • Patent number: 9557975
    Abstract: A method for accelerating processing of program code in a heterogeneous system may be provided. It may include identifying at runtime a code region having an acceleration potential, creating a dependency graph of the program code, expanding the dependency graph based on a first set of predefined rules to generate variants of the code region, and determining segments within the variants based on a second set of predefined rules. The segments may be dedicated and assigned and compiled for use to/by a specific execution unit such that a cost function is minimized.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christoph M. Angerer, Raphael Polig
  • Patent number: 9557976
    Abstract: A method for accelerating processing of program code in a heterogeneous system may be provided. It may include identifying at runtime a code region having an acceleration potential, creating a dependency graph of the program code, expanding the dependency graph based on a first set of predefined rules to generate variants of the code region, and determining segments within the variants based on a second set of predefined rules. The segments may be dedicated and assigned and compiled for use to/by a specific execution unit such that a cost function is minimized.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christoph M. Angerer, Raphael Polig
  • Patent number: 9535673
    Abstract: A method for significantly reducing compilation time of an application program is provided for compiling the program using profile-directed feedback (PDF). The method applies an additional analysis process between a training run of the application program and a whole program compilation of the application. This analysis process examines a PDF profile file(s) produced during the training run and aggregates data from the PDF file to determine a maximum block counter associated with each source file of the application. Only those source files having maximum block counters in a specified top percent of all the source files of the application have their fat binaries included in the whole program compilation.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shimin Cui, William G. O'Farrell, Graham K. Yiu