Abstract: A distributed computing environment is provided with a system and method for supporting rare copy-on-write data access. The system operates a data structure in a read only pattern suitable for serving a plurality of read requests with reduced overhead. The system, upon receiving a write request, creates a copy of data to execute the write request. The system defers writing the mutated data back to the read-only data structure. The system thus allows for multiple mutations to be made to the copy of the data using a read/write access pattern. After a number of read-only requests are received, the mutated data is written back to the read-only data structure. A monitor counts read and write requests in order to reduce overall read/write overhead and enhance performance of the distributed data grid.

Abstract: A computer system, designed according to a particular architecture, compiles and execute a general quantum program. Computer systems designed in accordance with the architecture are suitable for use with a variety of programming languages and a variety of hardware backends. The architecture includes a classical computer and a quantum device (which may be remote from the local computer) which includes both classical execution units and a quantum processing unit (QPU).

Abstract: There are provided systems and methods for reducing computing calls for webpage load times and resources to reduce power usage and/or carbon footprints caused by repetitive navigations. A service provider, such as an online transaction processor, may provide computing services to users, which require computing devices of the users to interact with the service provider and load data on the computing devices, including webpages and application interfaces. Each of data loading event may have a cost, where repeating events may lead to unnecessary power usage, carbon emissions and/or a carbon footprint. A graph algorithmic process may utilize state diagrams of processing flows for data loading events with attributes for each data loading event to identify problematic repeated events. Once the problematic events are identified, the service provider may identify corrective actions to avoid or reduce the repetitive events, such as by merging data into one or more events.

Abstract: Methods and systems are presented for providing a scalable communication framework for facilitating computing services to computer nodes across multiple availability zones. One or more communication servers act as a communication proxy for a processing server configured to perform the computing services. Upon receiving a service request from a computer node, the communication server establishes a synchronous communication session with the computer node. The communication server generates a request message and inserts the request message in a downstream queue accessible by the processing server. The processing server retrieves the request message from the downstream queue and performs the computing services based on the request message. Outputs from the computing services are encapsulated within a response message and then inserted in an upstream queue.

Abstract: In some implementations, there is provided a method that includes generating a user interface to enable selection of configuration information and initiation of a build of an application instance; receiving, from the user interface, an indication to initiate the build of the application instance; assigning at least one slave node to build, based on the configuration information, the application instance; obtaining, from at least one repository, build information including at least one of a command script, a dataset, and an application instance template; generating, based on the build information, a container file; storing the container file; generating the container image and storing the container image; and executing the image to provide a container. Related systems and articles of manufacture are also disclosed.

Abstract: This application describes methods, systems, and apparatus, including computer programs encoded on computer storage media, of an AI-assisted compiler. An example method includes obtaining intermediate code and executable code generated by compiling a computer program with a compiler; determining a reward based on one or more traces obtained by executing the executable code in a runtime system; generating an embedding vector based on the intermediate code and the one or more traces to represent code execution states; determining, using a reinforcement learning agent, one or more optimization actions based on the embedding vector and the reward; and updating the compiler by applying the one or more optimization actions.

Abstract: Systems, methods, and computer-readable for defining host functionalities in a computing environment include obtaining two or more snapshots comprising information pertaining to two or more processes executing in two or more hosts, the two or more snapshots being obtained at two or more points in time from the two or more hosts. One or more long-running processes amongst the two or more processes are identified based on one or more criteria associated with long-running processes. One or more priorities associated with the one or more long-running processes and used for defining functionalities for at least a subset of the two or more hosts, where high priorities are assigned to long-running processes, such as web server or database server processes, which are unique to at least the subset of the two or more hosts. Resources may be provisioned based on these host functionalities.

Abstract: A system and method for managing data storage and data access with querying data in a distributed system without buffering the results on intermediate operations in disk storage.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: Software releases can be generated based on controller metadata in some examples. In one such example, a system can receive metadata files including a set of properties for controllers executable in a distributed computing environment to manage software components collectively forming a software application. Each metadata file can specify respective properties for a respective controller. The system can extract deployment details from the set of properties included in the metadata files, where the deployment details can specify how the controllers are to be deployed in the distributed computing environment. The system can then generate combined metadata that includes the deployment details from the metadata files. The system can incorporate the combined metadata into a software release, so that the software release can be used to deploy the controllers in accordance with the combined metadata.

Abstract: A system and method automatically refactor mature program code having interdependent features to remove instructions pertaining to features that are no longer used. To facilitate reduction of the number of feature dependencies to test, instrumentation data are analyzed to determine which of the available features are in actual use. A graph of feature dependencies is built based on the program configuration, and the program code is simulated, according to existing testing protocols, with various combinations of features disabled to determine whether the program continues to function without error. When features are found that can be safely removed, the codebase is automatically refactored to eliminate the implementing code corresponding to the features. The refactored code then may be further automatically retested and deployed into the production environment.

Abstract: Devices, systems and methods for reconfigurable and/or updatable lightweight embedded devices or systems are disclosed. Via use of such a device, system, or method, various capabilities for a user are provided, simplified, secured, and/or made more convenient. The system may interact with various other devices or systems, including those that are cloud-based or communicate through the cloud, and may utilize various local sensors, in order to provide one or more of improved access, monitoring, or diagnostics, and so forth.

Abstract: This invention relates to a method of optimization of a computer program, comprising: a first step (S11, S12, S13, S14) of determination of a call of a function having at least one input parameter, said call corresponding to a first criterion according to which said input parameter is inside an interval substantially smaller than the range of possible values for said input parameter, and to a second criterion corresponding to a desired accuracy for said call; a second step (S2) of automatic generation of an executable code for implementing said function, minimizing execution time for said input parameter being within said interval and compliant with said desired accuracy; a third step (S3) of replacing the existing code implementing said function by the executable code generated at said second step.

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

Abstract: Systems and methods are described herein for translating code segments from one high-level programming language to another. The system may maintain any suitable number of decoding computing modules each configured to translate code of a corresponding language to an intermediate configuration object that represents an abstracted version of the code that identifies the operations performed on one or more variables and the order by which these operations are performed in the code. The intermediate configuration object can be used to generate new code segments expressed in different programming languages. In some embodiments, generating the a new code segment in a given programming language from the intermediate configuration object can be performed by an encoding computing module that is specific to that language.

Abstract: A model optimization system can reduce the delays caused by cache misses and page faults by converting a model of one or more decision trees into machine code that is optimized to avoid these memory faults. The model optimization system can convert a model into machine code by converting each tree of the model into a series of nested if/then statements and converting each series of nested if/then statements into optimized machine code. In some implementations, the model can be converted into optimized machine code only when an amount of processing required to convert the model into the optimized machine code is less than the expected cost savings of using the optimized machine code, instead of an unmodified version of the model, over the life of the model.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: According to an aspect of an embodiment, a method may include obtaining a computer-readable program and analyzing the computer-readable program to identify a constant in code of the computer-readable program. The method may also include obtaining context data associated with the constant from a portion of the code that includes an occurrence of the constant. The method may also include determining a location in the computer-readable program of the occurrence of the constant and analyzing the context data to identify a property of potential inputs to the computer-readable program at the location. The method may also include generating an input for the computer-readable program based on the constant and the identified property and providing the generated input to the computer-readable program during execution of the computer-readable program when execution of the computer-readable program reaches the location.

Abstract: Disclosed aspects relate to agent flow arrangement management in a distributed commit processing environment. A first set of agent utilization data may be collected with respect to a first commit processing agent. A second set of agent utilization data may be collected with respect to a second commit processing agent. An agent flow arrangement may be determined based on a first value with respect to the first set of agent utilization data exceeding a second value with respect to the second set of agent utilization data. The agent flow arrangement may have the first commit processing agent subsequent to the second commit processing agent. The distributed commit operation may be processed using the agent flow arrangement which has the first commit processing agent subsequent to the second commit processing agent.

Abstract: Markup language documents including server side scripting code using PHP syntax are executed efficiently in response to requests received by a server. The processing of the markup language document results in generation of a transformed markup language document that is returned in response to the request. The server side script code is input to a compiler that generates C++ code (or code in any object-based language based on C language) implementing the functionality of the server side script code. The C++ code is compiled to generated object code which is executed in order to process the markup language document. The generated C++ code includes functionality supported by PHP language including redeclaration of functions, dynamic variables, global variables, and the like. The generated C++ code invokes memory allocation code that allocates and deallocates objects obtained by instantiating the generated C++ classes.

Abstract: A system and method for managing data storage and data access with querying data in a distributed system without buffering the results on intermediate operations in disk storage.

Abstract: The objective of the present invention is to prevent a conflict between variable names and consequently the unintentional overwriting of data when a plurality of programs that define a shared variable exist. A control device (1) is equipped with a program management part (11), a data storage part (13a), and a shared variable symbol table (13b). The program management part (11) acquires an identifier for a first user program, generates a shared variable name that includes the identifier and a variable name of a shared variable defined in the first user program, associates the shared variable name and an address of the shared variable with each other, and records these in the shared variable symbol table (13b).

Abstract: A runtime system for distributing work between multiple threads in multi-socket shared memory machines that may support fine-grained scheduling of parallel loops. The runtime system may implement a request combining technique in which a representative thread requests work on behalf of other threads. The request combining technique may be asynchronous; a thread may execute work while waiting to obtain additional work via the request combining technique. Loops can be nested within one another, and the runtime system may provide control over the way in which hardware contexts are allocated to the loops at the different levels. An “inside out” approach may be used for nested loops in which a loop indicates how many levels are nested inside it, rather than a conventional “outside in” approach to nesting.

Abstract: The method for collecting information includes obtaining, based on a method identifier of the target method, the quantity of times of invoking the target method, recording method information of the target method based on the quantity of times of invoking the target method, a first threshold, and a second threshold, and setting a method status of the target method, the method status is one of a first state and a second state, the first state corresponds to the first threshold, the second state corresponds to the second threshold.

Abstract: According to one or more embodiments, operations may include identifying a plurality of source code edits made between a buggy version of first source code of a first software program and a repaired version of the first source code. The operations may also include identifying a plurality of clusters of the source code edits. Each cluster of the plurality of clusters includes one or more source code edits of the plurality of source code edits. The operations may also include identifying a plurality of valid clusters of the plurality of clusters and identifying one or more invalid clusters of the plurality of clusters based on compiling of the first source code. Moreover, the operations may include identifying, as a first repair of the first error, a particular set of one or more valid clusters of the plurality of valid clusters while excluding the one or more invalid clusters from consideration.

Abstract: An integrated data pipeline can take advantage of a streaming service, which can handle tasks such as automated redelivery, as well as a processing service, which can allocate workers on a task- or event-specific basis. Event data is aggregated and compressed for delivery by the streaming service. The streaming service can deliver the data asynchronously to the processing service, which can disaggregate and decompress the data to obtain the original data records. The type of event for each record can be determined to determine whether the data should be processed using online and/or offline processing. For online processing the appropriate fields are determined and data extracted to be passed to the online processing services. For offline processing the record data is concatenated sequentially into mini-batches, then compacted into larger batch files that are stored for subsequent offline processing.

Abstract: Embodiments of the present disclosure relate to anti-tamper computer systems, in particular to methods and systems which can embed protection code into software. Among other things, the protection code helps prevent (and make it more costly) to reverse engineer to tamper with the protected software with malicious intent, such as, but not restricted to: the removal of a license protection mechanism; the removal of code displaying advertisements; the injection of a malicious thread into the program memory space; illicit usage; or any other kind of unauthorized modification of the software.

Abstract: There is provided a method to optimize memory usage in hash tables by organizing data storage in the hash table with arrays instead of linked lists where sizes of arrays can be predicted with high accuracy. The method has certain conditions and range of applicability, including where hash function of key provides uniform distribution of values. The method is more applicable if the number of entries is more than 60,000.

Abstract: A system and method for accessing a tagged global variable in software, including: randomly generating tags for global variables in the software; tagging the global variables with the random tags; creating a pointer to each global variable with the random tags in unused bits of the pointer wherein the pointer points to the associated global variable; accessing one global variable indirectly using the tagged pointer; determining whether tag on the accessed global variable matches the tag on the accessed pointer; and indicating a fault when the tag on the accessed global variable does not match the tag on the accessed pointer.

Abstract: A system and method are provided for emulating a code sequence while compiling the code sequence into compiled operations for later execution of the code sequence. In one embodiment, the system includes an emulation model for executing operations and a compilation model for compiling operations. The emulation model may execute operations of the code sequence and the compilation model may compile the operations of the code sequence into compiled operations. The system may transfer execution of the operations from the emulation model to the compiled operations. In certain implementations, the transfer may include transferring flow information and program execution information. In further implementations, the transfer may occur after detecting that a current compilation level of the code sequence exceeds a compilation threshold.

Abstract: The present disclosure provides a system for monitoring I/O traffic. The system includes a memory storing information, a device, and a translation lookaside buffer (TLB). The device is configured to send a request for accessing information from the memory. The TLB includes a counter register file having counter registers, and entries having corresponding counter ID fields. The TLB is configured to receive a source identifier of the device and a virtual address associated with the request from the device, select an entry of the entries using the source identifier and the virtual address, select a counter register from the counter registers in accordance with information stored in the counter ID field of the selected entry, and update a value of the selected counter register in accordance with data transferred in association with the request.

Abstract: Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.

Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.

Abstract: An exemplary method includes obtaining a training set of code data that includes deprecated code; training a multi-layer neural network on the training set of code data to predict usage events for the deprecated code; predicting usage events for the deprecated code, in a first set of code data, using the trained multi-layer neural network; estimating a value of risk associated with the deprecated code in response to the predicted usage events; comparing the estimated value of risk to a threshold; and, in response to the estimated value of risk exceeding the threshold, implementing an ameliorative action regarding the deprecated code.

Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.

Abstract: Techniques for a service provider network to generate suitability scores that indicate how well VM instance types are performing given the workloads they are running. Using these suitability scores, users are able to easily determine the suitability of VM instance types for supporting their workloads, and diagnose potential issues with the pairings of VM instance types and workloads, such as over-utilization and under-utilization of VM instances. Further, the techniques include training a model to determine VM instance types recommended for supporting workloads. The model may receive utilization data representing resource-usage characteristics of the workload as input, and be trained to output one or more recommended VM instance types that are optimized or suitable to host the workload. Thus, the service provider network may provide users with easily-digestible suitability scores indicating the suitability of VM instance types for workloads along with VM instance types recommended for their workloads.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions structured to compute a min/max value of a vector. In one example, a processor executes a decoded single instruction to determine on a per data element position of the identified first and second operands a maximum or minimum, store the determined maximum or minimums in corresponding data element positions of the identified first operand, and determine and store, in each data element position of the identified third operand, an indication of where the maximum or minimum came from.

Abstract: An embodiment provides deferred state mutation. Information defining action chains implementing part of a client application is received. The received information includes an explicit computer executable instruction to modify a global state associated with each action chain. Computer executable instructions are automatically generated for each of the action chains to create respective private views of the global state for each of the action chains. A separate implicit computer executable instruction is automatically associated with each of the explicit computer executable instructions. The implicit computer executable instructions are executed during runtime of the client application instead of the respective explicit computer executable instructions.

Abstract: Techniques are provided for dataflow execution time estimation for distributed processing frameworks. An exemplary method comprises: obtaining an input dataset for a dataflow for execution; determining a substantially minimal data unit for a given operation of the dataflow processed by the given operation; estimating a number of rounds required to execute a number of data units in the input dataset using nodes assigned to execute the given operation; determining an execution time spent by the given operation to process one data unit; estimating the execution time for the given operation based on the execution time spent by the given operation to process one data unit and the number of rounds required to execute the number of data units in the input dataset; and executing the given operation with the input dataset. A persistent cost model is optionally employed to record the execution times of known dataflow operations.

Abstract: The invention relates to the valence-based encoding of connectivity data of a 3D mesh. A command is generated for each free edge of each vertex traversed and describes the vertex at the other end of the edge. The obtained list of commands is encoded by mapping each command onto a symbol. A mapping table associating commands with a set of respective consecutive numeral symbols is used. The list of symbols is then encoded, separately to the encoding of parameters of the commands. A joint encoding may be used to encode two or more consecutive symbols using a single coding word. A look-up table may be used based on the valence values intrinsically defined by each symbol, in order to give priority to the most frequent valence values (usually around 6). Prior to generating the commands, a vertex may be added to the 3D mesh to artificially fill any hole therein.

Abstract: Disclosed is a method for managing an issue queue for fused instructions and paired instructions in a microprocessor. The method includes dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.

Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.

Abstract: Exemplary methods, apparatuses, and systems maintain a plurality of summary data structures corresponding to a plurality of logical file system namespaces representing a plurality of hierarchies of one or more directories having one or more files, each file being stored in the storage system as a plurality of segments in a deduplicated manner. In response to a request to estimate a storage usage by a first of the file system namespace, identify a first of the summary data structures corresponding to the first file system namespace, wherein the first summary data structure stores information summarizing deduplicated segments referenced by one or more files of the first file system namespace. Estimate the storage usage of the first file system namespace based on the first summary data structure and a global summary data structure, wherein the global summary data structure stores information summarizing deduplicated segments referenced by all of the file system namespaces.

Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.

Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.

Abstract: Embodiments of the present disclosure relate to software optimization by identifying unused/obsolete components of a software application. Other embodiments may be described and/or claimed.

Abstract: A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.

Abstract: A predicted profile is generated for target code to be executed on a processor of the computing environment. The predicted profile is based on a profile of sampled code. The sampled code is a different version of code than the target code and is a complex build of modules for which it is difficult to determine which versions of the modules have been profiled. Based on the predicted profile for the target code, a determination is made of predicted execution information for the target code. Based on the determining the predicted execution information for the target code, an action is performed to facilitate processing within the computing environment.

Abstract: A computer-implemented method for offloading a problem having 2n size from processing circuitry to one or more accelerators is disclosed. The processing circuitry and the one or more accelerators include respective memories. In the method, a problem having 2n size is divided into a plurality of units each having 2u size. At least a part of the units is allocated to the one or more accelerators. A determination is made as to whether there is a remaining part of the units to be allocated onto the processing circuitry. A temporary buffer is prepared on each memory of at least the one or more accelerators. The temporary buffer is used for storing a copy of a dependent unit stored on a different memory, during inter-unit calculation.