Optimization Patents (Class 717/151)
  • Patent number: 11157321
    Abstract: A runtime system for distributing work between multiple threads in multi-socket shared memory machines that may support fine-grained scheduling of parallel loops. The runtime system may implement a request combining technique in which a representative thread requests work on behalf of other threads. The request combining technique may be asynchronous; a thread may execute work while waiting to obtain additional work via the request combining technique. Loops can be nested within one another, and the runtime system may provide control over the way in which hardware contexts are allocated to the loops at the different levels. An “inside out” approach may be used for nested loops in which a loop indicates how many levels are nested inside it, rather than a conventional “outside in” approach to nesting.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 26, 2021
    Assignee: Oracle International Corporation
    Inventor: Timothy L. Harris
  • Patent number: 11157297
    Abstract: The objective of the present invention is to prevent a conflict between variable names and consequently the unintentional overwriting of data when a plurality of programs that define a shared variable exist. A control device (1) is equipped with a program management part (11), a data storage part (13a), and a shared variable symbol table (13b). The program management part (11) acquires an identifier for a first user program, generates a shared variable name that includes the identifier and a variable name of a shared variable defined in the first user program, associates the shared variable name and an address of the shared variable with each other, and records these in the shared variable symbol table (13b).
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 26, 2021
    Assignee: OMRON Corporation
    Inventor: Wataru Arai
  • Patent number: 11138034
    Abstract: The method for collecting information includes obtaining, based on a method identifier of the target method, the quantity of times of invoking the target method, recording method information of the target method based on the quantity of times of invoking the target method, a first threshold, and a second threshold, and setting a method status of the target method, the method status is one of a first state and a second state, the first state corresponds to the first threshold, the second state corresponds to the second threshold.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yifan Lu, Haitao Huang, Yongyong Yang, Yongjian Chen, Mingliang Yi
  • Patent number: 11119889
    Abstract: According to one or more embodiments, operations may include identifying a plurality of source code edits made between a buggy version of first source code of a first software program and a repaired version of the first source code. The operations may also include identifying a plurality of clusters of the source code edits. Each cluster of the plurality of clusters includes one or more source code edits of the plurality of source code edits. The operations may also include identifying a plurality of valid clusters of the plurality of clusters and identifying one or more invalid clusters of the plurality of clusters based on compiling of the first source code. Moreover, the operations may include identifying, as a first repair of the first error, a particular set of one or more valid clusters of the plurality of valid clusters while excluding the one or more invalid clusters from consideration.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 14, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Yoshida, Mukul R. Prasad
  • Patent number: 11113244
    Abstract: An integrated data pipeline can take advantage of a streaming service, which can handle tasks such as automated redelivery, as well as a processing service, which can allocate workers on a task- or event-specific basis. Event data is aggregated and compressed for delivery by the streaming service. The streaming service can deliver the data asynchronously to the processing service, which can disaggregate and decompress the data to obtain the original data records. The type of event for each record can be determined to determine whether the data should be processed using online and/or offline processing. For online processing the appropriate fields are determined and data extracted to be passed to the online processing services. For offline processing the record data is concatenated sequentially into mini-batches, then compacted into larger batch files that are stored for subsequent offline processing.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: September 7, 2021
    Assignee: A9.COM, INC.
    Inventors: Gang Chen, Abraham Hossain Bagherjeiran, Chein-Hsin Liu
  • Patent number: 11080251
    Abstract: There is provided a method to optimize memory usage in hash tables by organizing data storage in the hash table with arrays instead of linked lists where sizes of arrays can be predicted with high accuracy. The method has certain conditions and range of applicability, including where hash function of key provides uniform distribution of values. The method is more applicable if the number of entries is more than 60,000.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 3, 2021
    Inventor: Viktor Boldyshev
  • Patent number: 11080373
    Abstract: Embodiments of the present disclosure relate to anti-tamper computer systems, in particular to methods and systems which can embed protection code into software. Among other things, the protection code helps prevent (and make it more costly) to reverse engineer to tamper with the protected software with malicious intent, such as, but not restricted to: the removal of a license protection mechanism; the removal of code displaying advertisements; the injection of a malicious thread into the program memory space; illicit usage; or any other kind of unauthorized modification of the software.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 3, 2021
    Assignee: Snap Inc.
    Inventors: Johan Wehrli, Julien Rinaldini
  • Patent number: 11055202
    Abstract: A system and method for accessing a tagged global variable in software, including: randomly generating tags for global variables in the software; tagging the global variables with the random tags; creating a pointer to each global variable with the random tags in unused bits of the pointer wherein the pointer points to the associated global variable; accessing one global variable indirectly using the tagged pointer; determining whether tag on the accessed global variable matches the tag on the accessed pointer; and indicating a fault when the tag on the accessed global variable does not match the tag on the accessed pointer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP B.V.
    Inventors: Jan Hoogerbrugge, Marcel Medwed
  • Patent number: 11029929
    Abstract: A system and method are provided for emulating a code sequence while compiling the code sequence into compiled operations for later execution of the code sequence. In one embodiment, the system includes an emulation model for executing operations and a compilation model for compiling operations. The emulation model may execute operations of the code sequence and the compilation model may compile the operations of the code sequence into compiled operations. The system may transfer execution of the operations from the emulation model to the compiled operations. In certain implementations, the transfer may include transferring flow information and program execution information. In further implementations, the transfer may occur after detecting that a current compilation level of the code sequence exceeds a compilation threshold.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 8, 2021
    Assignee: Red Hat, Inc.
    Inventor: Nathaniel Philip McCallum
  • Patent number: 11023397
    Abstract: The present disclosure provides a system for monitoring I/O traffic. The system includes a memory storing information, a device, and a translation lookaside buffer (TLB). The device is configured to send a request for accessing information from the memory. The TLB includes a counter register file having counter registers, and entries having corresponding counter ID fields. The TLB is configured to receive a source identifier of the device and a virtual address associated with the request from the device, select an entry of the entries using the source identifier and the virtual address, select a counter register from the counter registers in accordance with information stored in the counter ID field of the selected entry, and update a value of the selected counter register in accordance with data transferred in association with the request.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 1, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Jian Chen, Li Zhao, Ying Zhang
  • Patent number: 11016744
    Abstract: Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10983835
    Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 20, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chei-Yol Kim, Young-Ho Kim, Jin-Ho On, Su-Min Jang, Gyu-Il Cha
  • Patent number: 10977030
    Abstract: An exemplary method includes obtaining a training set of code data that includes deprecated code; training a multi-layer neural network on the training set of code data to predict usage events for the deprecated code; predicting usage events for the deprecated code, in a first set of code data, using the trained multi-layer neural network; estimating a value of risk associated with the deprecated code in response to the predicted usage events; comparing the estimated value of risk to a threshold; and, in response to the estimated value of risk exceeding the threshold, implementing an ameliorative action regarding the deprecated code.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Komminist Weldemariam, Abdigani Diriye, Shikhar Kwatra, Paul Krystek, Sushain Pandit
  • Patent number: 10970079
    Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kurt A. Feiste, Michael J. Genden, Paul M. Kennedy, Dung Q. Nguyen
  • Patent number: 10970123
    Abstract: Techniques for a service provider network to generate suitability scores that indicate how well VM instance types are performing given the workloads they are running. Using these suitability scores, users are able to easily determine the suitability of VM instance types for supporting their workloads, and diagnose potential issues with the pairings of VM instance types and workloads, such as over-utilization and under-utilization of VM instances. Further, the techniques include training a model to determine VM instance types recommended for supporting workloads. The model may receive utilization data representing resource-usage characteristics of the workload as input, and be trained to output one or more recommended VM instance types that are optimized or suitable to host the workload. Thus, the service provider network may provide users with easily-digestible suitability scores indicating the suitability of VM instance types for workloads along with VM instance types recommended for their workloads.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 6, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Lorenzo Luciano, Imre Attila Kiss, Esther Kadosh, Peter William Beardshear
  • Patent number: 10922074
    Abstract: An embodiment provides deferred state mutation. Information defining action chains implementing part of a client application is received. The received information includes an explicit computer executable instruction to modify a global state associated with each action chain. Computer executable instructions are automatically generated for each of the action chains to create respective private views of the global state for each of the action chains. A separate implicit computer executable instruction is automatically associated with each of the explicit computer executable instructions. The implicit computer executable instructions are executed during runtime of the client application instead of the respective explicit computer executable instructions.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: February 16, 2021
    Assignee: Oracle International Corporation
    Inventor: Christian Straub
  • Patent number: 10922080
    Abstract: Disclosed embodiments relate to systems and methods for performing instructions structured to compute a min/max value of a vector. In one example, a processor executes a decoded single instruction to determine on a per data element position of the identified first and second operands a maximum or minimum, store the determined maximum or minimums in corresponding data element positions of the identified first operand, and determine and store, in each data element position of the identified third operand, an indication of where the maximum or minimum came from.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Sunny L. Gogar, Rama Kishan V. Malladi, Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes
  • Patent number: 10901782
    Abstract: Techniques are provided for dataflow execution time estimation for distributed processing frameworks. An exemplary method comprises: obtaining an input dataset for a dataflow for execution; determining a substantially minimal data unit for a given operation of the dataflow processed by the given operation; estimating a number of rounds required to execute a number of data units in the input dataset using nodes assigned to execute the given operation; determining an execution time spent by the given operation to process one data unit; estimating the execution time for the given operation based on the execution time spent by the given operation to process one data unit and the number of rounds required to execute the number of data units in the input dataset; and executing the given operation with the input dataset. A persistent cost model is optionally employed to record the execution times of known dataflow operations.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinícius Michel Gottin, Jonas F. Dias, Edward José Pacheco Condori, Angelo E. M. Ciarlini, Bruno Carlos da Cunha Costa, Fábio André Machado Porto, Paulo de Figueiredo Pires, Yania Molina Souto, Wagner dos Santos Vieira
  • Patent number: 10861195
    Abstract: The invention relates to the valence-based encoding of connectivity data of a 3D mesh. A command is generated for each free edge of each vertex traversed and describes the vertex at the other end of the edge. The obtained list of commands is encoded by mapping each command onto a symbol. A mapping table associating commands with a set of respective consecutive numeral symbols is used. The list of symbols is then encoded, separately to the encoding of parameters of the commands. A joint encoding may be used to encode two or more consecutive symbols using a single coding word. A look-up table may be used based on the valence values intrinsically defined by each symbol, in order to give priority to the most frequent valence values (usually around 6). Prior to generating the commands, a vertex may be added to the 3D mesh to artificially fill any hole therein.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 8, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Patrice Onno, Guillaume Laroche, Christophe Gisquet
  • Patent number: 10831501
    Abstract: Disclosed is a method for managing an issue queue for fused instructions and paired instructions in a microprocessor. The method includes dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10831498
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10810161
    Abstract: Exemplary methods, apparatuses, and systems maintain a plurality of summary data structures corresponding to a plurality of logical file system namespaces representing a plurality of hierarchies of one or more directories having one or more files, each file being stored in the storage system as a plurality of segments in a deduplicated manner. In response to a request to estimate a storage usage by a first of the file system namespace, identify a first of the summary data structures corresponding to the first file system namespace, wherein the first summary data structure stores information summarizing deduplicated segments referenced by one or more files of the first file system namespace. Estimate the storage usage of the first file system namespace based on the first summary data structure and a global summary data structure, wherein the global summary data structure stores information summarizing deduplicated segments referenced by all of the file system namespaces.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 20, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Srikant Varadan, Dheer Moghe, Sazzala Reddy
  • Patent number: 10761819
    Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Zhigang Gong, Wenqing Fu, Peng Li, Can Que, Zhiwen Wu
  • Patent number: 10747551
    Abstract: Embodiments of the present disclosure relate to software optimization by identifying unused/obsolete components of a software application. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 18, 2020
    Assignee: SALESFORCE.COM, INC.
    Inventors: Brian Toal, Rahul Shinde
  • Patent number: 10747513
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10725788
    Abstract: A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jose Yallouz, Arkady Bramnik, Ron Gabor
  • Patent number: 10678557
    Abstract: A predicted profile is generated for target code to be executed on a processor of the computing environment. The predicted profile is based on a profile of sampled code. The sampled code is a different version of code than the target code and is a complex build of modules for which it is difficult to determine which versions of the modules have been profiled. Based on the predicted profile for the target code, a determination is made of predicted execution information for the target code. Based on the determining the predicted execution information for the target code, an action is performed to facilitate processing within the computing environment.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David K. Siegwart, Allan H. Kielstra
  • Patent number: 10671550
    Abstract: A computer-implemented method for offloading a problem having 2n size from processing circuitry to one or more accelerators is disclosed. The processing circuitry and the one or more accelerators include respective memories. In the method, a problem having 2n size is divided into a plurality of units each having 2u size. At least a part of the units is allocated to the one or more accelerators. A determination is made as to whether there is a remaining part of the units to be allocated onto the processing circuitry. A temporary buffer is prepared on each memory of at least the one or more accelerators. The temporary buffer is used for storing a copy of a dependent unit stored on a different memory, during inter-unit calculation.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jun Doi
  • Patent number: 10642644
    Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
  • Patent number: 10599496
    Abstract: Novel tools and techniques for tracing application execution and performance. Some of the tools provide a framework for monitoring the execution and/or performance of applications in an execution chain. In some cases, the framework can accomplish this monitoring with a few simple calls to an application programming interface on an application server. In other cases, the framework can provide for the passing of traceability data in protocol-specific headers of existing inter-application (and/or intra-application) communication protocols.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 24, 2020
    Assignee: Qwest Communications International Inc.
    Inventors: Igor I. Malkiman, Chauncey G. Powis, Tyson Matthew Bunch
  • Patent number: 10592387
    Abstract: An approach is provided in which an information handling system selects a first point in a software program corresponding to a compile-time assumption made by a compiler. The information handling system then selects a set of second points in the software program corresponding to a set of locations at which the compile-time assumption can be violated at runtime. Next, the information handling system starts at the first point and propagates backwards in the software program to identify one or more of the second points that are reached from the backwards propagation. The information handling system then inserts conditional transitions in the software program at each of the identified assumption violation points and executes a compiled version of the software program, resulting in an evaluation of the compile-time assumption at the conditional transitions.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew Craik, Joseph Devin Micheal Papineau, Vijay Sundaresan
  • Patent number: 10585847
    Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 10, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
  • Patent number: 10565010
    Abstract: A ladder program analyzing device that can present information for improving execution efficiency of a ladder program includes a ladder program analyzing unit and a ladder program analysis result displaying unit. The ladder program analyzing unit analyzes a ladder program including a plurality of ladder circuits and prepares an execution priority signal table in which execution priorities of the ladder circuits, reference signals indicating signals input to the ladder circuits, and update signals indicating signals output from the ladder circuits are correlated with each other. The ladder program analysis result displaying unit determines presence or absence of the ladder circuit improvable in execution efficiency by comparing the execution priorities, the reference signals, and the update signals of two of the ladder circuits on the basis of the execution priority signal table and displays the determination result.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: February 18, 2020
    Assignee: FANUC CORPORATION
    Inventors: Toshiyuki Matsuo, Mitsuru Mochizuki
  • Patent number: 10552987
    Abstract: The invention relates to the encoding and decoding of texture mapping data of a textured 3D object. A 3D object is usually represented by connectivity, geometry and property data. The texture data, belonging to the property data, include a texture image; a texture coordinates table having entries, each entry defining coordinates in the texture image; and texture indexes associating each vertex of a polygon in the 3D object with an entry in the texture coordinates table. The present invention proposes to search for and delete entry duplicates from the texture coordinates table. To reduce encoding complexity, the search and deletion are based on the connectivity data. This is to exploit redundancies between the mesh connectivity for the polygons within the 3D object and the texture connectivity for the texture polygons within the texture image.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 4, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Guillaume Laroche, Patrice Onno, Christophe Gisquet
  • Patent number: 10528331
    Abstract: Approaches presented herein enable optimization of a cache of compiled XML Path Language (XPath) expressions by removing variability from XPath expressions. More specifically, XPath expressions are identified that are the same but for one or more hardcoded values. These hardcoded values are identified and replaced in an identified XPath expression with an identifier to form a cache optimized XPath expression that lacks the hardcoded value variability of the identified XPath expressions. This cache optimized XPath expression is inserted into a cache optimized function that receives the hardcoded value as arguments and assigns the received hardcoded value to the identifier in the cache optimized XPath expression. The identified XPath expressions are then rewritten as calls to the cache optimized function or to another function wrapping the cache optimized function.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicholas K. Lincoln, Simon D. Stone
  • Patent number: 10496412
    Abstract: Parallel dispatching of multi-operation instructions in a multi-slice computer processor, including: determining whether an instruction must be broken into a plurality of smaller operations; marking each of the smaller operations as instructions to be dispatched in parallel; determining whether each of the operations can be dispatched to distinct instruction issue queues during a same clock cycle; and responsive to determining that each of the operations can be dispatched to distinct instruction issue queues during the same clock cycle, dispatching each of the operations to distinct instruction issue queues during the same clock cycle.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: December 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kurt A. Feiste, Michael J. Genden, Paul M. Kennedy, Dung Q. Nguyen
  • Patent number: 10466985
    Abstract: Apparatus and methods related to compiling software are provided. A computing device can receive software having software-associated instructions for compilation into machine-language instructions. The computing device can perform a class hierarchy analysis to determine a class hierarchy for the software. The computing device can determine whether a particular method call is to be checked for execution as a virtual method call based on the class hierarchy. The computing device can, after determining that the particular method call is to be checked, determine particular machine-language instructions that can include: guarding machine-language instructions for checking a runtime-modifiable deoptimization indicator to determine whether the particular method call is to be executed as a virtual method call, and method-call machine-language instructions for the particular method call. The computing device can provide the particular machine-language instructions to a runtime system.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 5, 2019
    Assignee: Google LLC
    Inventors: Andreas Gampe, Nicolas Geoffray, Mingyao Yang
  • Patent number: 10416976
    Abstract: A configuration definition file created for a certain environment is easily applied to system deployment into another environment. A component information storage unit of a deployment device stores component information including, for each constituent element to constitute a system, setting information independent of deployment tools, and for each combination of each constituent element and each deployment tool available for deploying the constituent element, a deployment process for deploying the constituent element by the deployment tool. The component identification unit identifies, for each constituent element, a deployment process associated with a designated deployment tool, based on the component information. The sequence determination unit determines an execution sequence of the identified deployment processes, based on dependency relationships among the constituent elements.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 17, 2019
    Assignee: NEC CORPORATION
    Inventors: Manabu Nakanoya, Takayuki Kuroda
  • Patent number: 10419586
    Abstract: The present disclosure describes methods, systems, and computer program products for data-centric integration modeling in an application integration system. One computer-implemented method includes receiving, by operation of an integration system, a logic integration program comprising a plurality of logic integration patterns that are defined in a data-centric logic integration language; generating a logical model graph based on the logic integration program, the logical model graph being runtime-independent; converting the logical model graph into a physical model graph, the physical model graph being runtime-specific; and generating logic integration runtime codes executable by the integration system based on the physical model graph.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 17, 2019
    Assignee: SAP SE
    Inventors: Daniel Ritter, Jan Bross
  • Patent number: 10402320
    Abstract: A fused object includes a head and a tail. A head template is not modifiable. A tail template is modifiable. Modifying a tail template includes verifying the validity of a transition from a current tail template to a new tail template. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. A fused object may be associated with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 3, 2019
    Assignee: Oracle International Corporation
    Inventors: John R. Rose, Paul D. Sandoz
  • Patent number: 10360134
    Abstract: A computer-implemented method for determining infeasible conditions is disclosed. The method comprises executing a backward-bounded symbolic analysis on a control flow graph of a dynamic program.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Bardin, Robin David
  • Patent number: 10356176
    Abstract: A system and method access domain information indicating placement domains for an information handling system. The placement domains may include fault domains and optimization domains, wherein an optimization domain includes one or more resources wherein a tier instance for each tier of a multi-tier application service resource can be instantiated such that inter-tier communication is internal to the domain. Tier instances may be placed in accordance with the placement domains to achieve compliance with high availability and performance objectives. Management endpoints corresponding to each resource may be monitored and, responsive to detecting a change in the infrastructure, updated domain information indicative of updated placement domains may be accessed and used to determine whether the placement of the tier instances achieves compliance with the objectives.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Ravikanth Chaganti, Dharmesh M. Patel, Rizwan Ali
  • Patent number: 10268567
    Abstract: Systems, methods, and computer-readable media are disclosed for using managed runtime environment semantics to optimize record and replay frameworks. One method includes: executing, by the computing system, a managed runtime component; interacting, by the computing system, with another system during the execution of the managed runtime component; determining, by the computing system, whether a non-deterministic event is to be logged in event logs during the execution of the managed runtime component; determining, by the computing system when the non-deterministic event is to be logged, whether semantics of the non-deterministic event to be logged includes a predetermined semantic, wherein the predetermined semantic includes one or more of optimistic zero copy actions; and logging, by the computing system when the semantics of the non-deterministic event includes the predetermined semantic, a copy of contents of the non-deterministic event in event logs during the execution of the managed runtime component.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Mark Marron
  • Patent number: 10268463
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is set to be a default application binary, to be sent to devices requesting the application for a first time, if a percentage of matching application profiles exceeds a threshold. The optimized binary for the application is transmitted to the second device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Patent number: 10261825
    Abstract: Disclosed aspects relate to agent flow arrangement management in a distributed commit processing environment. A first set of agent utilization data may be collected with respect to a first commit processing agent. A second set of agent utilization data may be collected with respect to a second commit processing agent. An agent flow arrangement may be determined based on a first value with respect to the first set of agent utilization data exceeding a second value with respect to the second set of agent utilization data. The agent flow arrangement may have the first commit processing agent subsequent to the second commit processing agent. The distributed commit operation may be processed using the agent flow arrangement which has the first commit processing agent subsequent to the second commit processing agent.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua H. Armitage, Michael P. Clarke, John A. W. Kaputin, King-Yan Kwan, Andrew Wright
  • Patent number: 10255048
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10248394
    Abstract: Provided is a method for string comparison. The method includes receiving a plurality of target strings. Each target string of the plurality of target strings comprises a sequence of characters. The method further includes creating a character index for the plurality of target strings having a plurality of entries corresponding to the sequence of characters. The method further includes prioritizing the plurality of entries. The method further includes determining an evaluation method for the plurality of target strings based on the plurality of prioritized entries. The method further includes performing the evaluation method for the plurality of target strings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xing Xing Pan, Jiu Fu Guo, Xiao Feng Guan, Allan Kielstra
  • Patent number: 10241768
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 10235191
    Abstract: Methods and system are disclosed that manage behavior of a graphical user interface associated with an application during a runtime of the application. In one aspect, the graphical user interface (GUI) may be configured with attributes associated with the application by a GUI configuration manager. Upon determining application configuration information, a data field metadata manager may determine data fields to be mapped onto the GUI. The data field metadata manager may read the metadata information associated with the data fields that may include data field attributes and domain values. A GUI metadata manager may retrieve metadata information associated with the mapped data fields. A GUI runtime manager may manage the behavior of the GUI and the data received by the data fields may be saved in a data store in a data format associated with the application.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 19, 2019
    Assignee: SAP SE
    Inventors: Ashok Rao, Avinash Gopala Reddy, Arun Mathew, Sharath Prakash, Anjana Satheesh P K, Shalini Krishnamoorthy, Sona Dalsania, Prarthana Henly Onkar, Mohammed Ziyauddin
  • Patent number: 10223089
    Abstract: A method for partial redundancy elimination with a fixed number of temporaries includes determining local data values of program code that describe a temporary memory location, a set of registers, and a set of basic blocks. The method determines global data values of the program code based on the determined local data values of the program code. The method removes a first load of the temporary memory location in a first basic block in the program code. The method adds a second load on a first edge from a second basic block out of the set of basic blocks to a third basic block out of the set of basic blocks in the program code. The method performs a register move on a second edge from the third basic block to the second basic block in the program code.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Steven J. Perron