Optimization Patents (Class 717/151)
  • Patent number: 9977747
    Abstract: Memory performance in a computer system that implements large page mapping is improved even when memory is scarce by identifying page sharing opportunities within the large pages at the granularity of small pages and breaking up the large pages so that small pages within the large page can be freed up through page sharing. In addition, the number of small page sharing opportunities within the large pages can be used to estimate the total amount of memory that could be reclaimed through page sharing.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 22, 2018
    Assignee: VMware, Inc.
    Inventors: Yury Baskakov, Alexander Thomas Garthwaite, Rajesh Venkatasubramanian, Irene Zhang, Seongbeom Kim, Nikhil Bhatia, Kiran Tati
  • Patent number: 9971570
    Abstract: Techniques generate memory-optimization logic for concurrent graph analysis. A computer analyzes domain-specific language logic that analyzes a graph having vertices and edges. The computer detects parallel execution regions that create thread locals. Each thread local is associated with a vertex or edge. For each parallel region, the computer calculates how much memory is needed to store one instance of each thread local. The computer generates instrumentation that determines how many threads are available and how many vertices and edges will create thread locals. The computer generates tuning logic that determines how much memory is originally needed for the parallel region based on how much memory is needed to store the one instance, how many threads are available, and graph size. The tuning logic detects a memory shortage based on the original amount of memory needed exceeding how much memory is available and accordingly adjusts the execution of the parallel region.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 15, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9971563
    Abstract: Techniques described and suggested herein include systems and methods for logging execution of code using thread-local output buffers. For example, one or more output buffers are allocated to one or more threads executing on a computing system. A global declaration list containing information relating to log types (e.g., verbose log descriptions, templates for specific variables, and the like) may be implemented, and the global declaration list may be generated as part of an initialization process for some or all of the threads. Log events from executing threads may be stored in the output buffers in a fashion conforming to the global declaration list, and may be retrieved asynchronously relative to the executing threads.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 15, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Juhani Karppanen
  • Patent number: 9971579
    Abstract: A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-wook Ahn, Won-sub Kim, Jin-seok Lee, Seung-won Lee
  • Patent number: 9966150
    Abstract: A method to program bitcells of a ROM array uses different programming cells for programming the bitcells with a first or second data item. A first bitcell is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array as a flipped or a non-flipped memory in multi-bank instance. All other bitcells located in the same column as the first bitcell and subsequent rows are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Synopsys, Inc.
    Inventors: Anil Singh Rawat, Pritender Singh
  • Patent number: 9967257
    Abstract: A Software-Defined Network (SDN) authorizes Application Programming Interface (API) calls from user SDN applications to user SDN controllers. A user SDN application transfers an embedded code to an authorization SDN controller. The authorization SDN controller translates the embedded code into an SDN controller network address and an SDN application privilege data set. The authorization SDN controller transfers the SDN controller network address to the user SDN application. The authorization SDN controller transfers the SDN application privilege data set to the user SDN controller. The user SDN application transfers an SDN API call to the user SDN controller using the SDN controller network address. The user SDN controller determines if the SDN API call is authorized by the SDN application privilege data set. The user SDN controller services the API call if the SDN API call is authorized and inhibits an unauthorized API call.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 8, 2018
    Assignee: Sprint Communications Company L.P.
    Inventors: Marouane Balmakhtar, Arun Rajagopal
  • Patent number: 9928113
    Abstract: An analyzer (such as a compiler) searches for a program portion that matches a pattern that may suffer from workload imbalance due to nodes with high degrees (i.e., relatively many edges). Such a pattern involves iteration over at least a subset (or all) of the nodes in a graph. If a program portion that matches the pattern is found, then the analyzer determines whether the body of the iteration contains an iteration over edges or neighbors of each node in the subset. If so, then the analyzer transforms the graph analytic program by adding code and, optionally, modifying existing code so that high-degree nodes are processed differently than low-degree nodes. High-degree nodes are processed sequentially while low-degree nodes are processed in parallel. Conversely, edges of high-degree nodes are processed in parallel while edges of low-degree nodes are processed sequentially.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 27, 2018
    Assignee: Oracle International Corporation
    Inventors: Martin Sevenich, Sungpack Hong, Hassan Chafi
  • Patent number: 9886251
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9875088
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9841959
    Abstract: Provided are methods and systems for inter-procedural optimization (IPO). A new IPO architecture (referred to as “ThinLTO”) is designed to address the weaknesses and limitations of existing IPO approaches, such as traditional Link Time Optimization (LTO) and Lightweight Inter-Procedural Optimization (LIPO), and become a new link-time-optimization standard. With ThinLTO, demand-driven and summary-based fine grain importing maximizes the potential of Cross-Module Optimization (CMO), which enables as much useful CMO as possible ThinLTO also provides for global indexing, which enables fast function importing; parallelizes some performance-critical but expensive inter-procedural analyses and transformations; utilizes demand-driven, lazy importing of debug information that minimizes memory consumption for the debug build; and allows easy integration of third-party distributed build systems. In addition, ThinLTO may also be implemented using an IPO server, thereby removing the need for the serial step.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 12, 2017
    Assignee: Google LLC
    Inventors: Xinliang David Li, Teresa Louise Johnson, Rong Xu
  • Patent number: 9792432
    Abstract: Methods and apparatuses are provided for automatically optimizing application program code for minimized access to privacy data. A privacy-oriented code optimizing module process and/or facilitate a processing one or more code segments, one or more execution logs associated with the one or more code segments, or a combination thereof to determine at least one privacy intrusion signature associated with the one or more code segments. Further, the privacy-oriented code optimizing module determines one or more recommendations for one or more alternate code segments based, at least in part, on the at least one privacy intrusion signature.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 17, 2017
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Igor Bilogrevic, Kevin Huguenin
  • Patent number: 9778942
    Abstract: Disclosed are various embodiments for generating a replacement binary for emulation of an application. A computer ingests native object code and identifies a central processing unit (CPU) from the native object code. The computer transforms the native object code to produce replacement object code. When executed on the computing device, the replacement code invokes an emulator for the CPU to execute the native code.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Amazon Technologies, Inc.
    Inventor: Venelin N. Efremov
  • Patent number: 9760357
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9747086
    Abstract: Extractable annotations are created and stored for different transmission points. In some instances, this occurs during compiling. One type of transmission point is a message being passed to another process. Once the transmission point is identified, a pattern defining output for the transmission point is then identified. A first extractable annotation defining the first patter is then created and stored for subsequent use.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Charles D. Garrett
  • Patent number: 9727319
    Abstract: A method for significantly reducing compilation time of an application program is provided for compiling the program using profile-directed feedback (PDF). The method applies an additional analysis process between a training run of the application program and a whole program compilation of the application. This analysis process examines a PDF profile file(s) produced during the training run and aggregates data from the PDF file to determine a maximum block counter associated with each source file of the application. Only those source files having maximum block counters in a specified top percent of all the source files of the application have their fat binaries included in the whole program compilation.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shimin Cui, William G. O'Farrell, Graham K. Yiu
  • Patent number: 9710264
    Abstract: A method for performing data flow analysis of computer code, comprising: providing computer code of a computer program having a plurality of user interface screens; dividing the computer code to a plurality of portions such that each one of the portions includes code for inducing at least one of loading and using one of the user interface screens; performing a variable usage analysis to detect which variables are at least one of calculated and used in each one of the portions; constructing a data dependence model defining dependencies among the portions based on the variable usage analysis; and identifying, for at least one of the portions and using the data dependence model, at least one unnecessary variable loaded in one of the user interface screens and not used in a respective portion and in a group of portions depending on the respective portion.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Idan Ben-Harrush
  • Patent number: 9684515
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684514
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 9684497
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9634912
    Abstract: Provided is a computer, comprising a memory which stores a program and a processor which executes the program which is stored in the memory for each predetermined processing unit, with which a computer resource usage is calculated by a process which is executed for each predetermined processing unit. The computer resources include overlapping resources which are used in an overlapping manner when the program is executed and non-overlapping resources which are not used in an overlapping manner when the program is executed. When calculating the computer resource usage by the process which is executed for each predetermined processing unit, the processor determines, by analyzing the computer resources, the overlapping resources which are used by the process and the non-overlapping resources which are used by the process, and calculates the computer resource usage by the process on the basis of the result of the determination.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 25, 2017
    Assignee: Hitachi, Ltd.
    Inventor: Masanobu Yamada
  • Patent number: 9626256
    Abstract: A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9626169
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9619345
    Abstract: A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions into the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W Cain, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9606783
    Abstract: In a method for dynamically replacing code within a software application on a device, an annotated code segment that performs a function according to a first data policy is received. The computer determines an alternate segment that performs the function according to a second data policy.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Radha M. De, Brian M. O'Connell, Cheranellore Vasudevan
  • Patent number: 9588801
    Abstract: An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Irina Calciu, Justin E Gottschlich, Tatiana Shpeisman, Gilles A Pokam
  • Patent number: 9557976
    Abstract: A method for accelerating processing of program code in a heterogeneous system may be provided. It may include identifying at runtime a code region having an acceleration potential, creating a dependency graph of the program code, expanding the dependency graph based on a first set of predefined rules to generate variants of the code region, and determining segments within the variants based on a second set of predefined rules. The segments may be dedicated and assigned and compiled for use to/by a specific execution unit such that a cost function is minimized.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christoph M. Angerer, Raphael Polig
  • Patent number: 9557975
    Abstract: A method for accelerating processing of program code in a heterogeneous system may be provided. It may include identifying at runtime a code region having an acceleration potential, creating a dependency graph of the program code, expanding the dependency graph based on a first set of predefined rules to generate variants of the code region, and determining segments within the variants based on a second set of predefined rules. The segments may be dedicated and assigned and compiled for use to/by a specific execution unit such that a cost function is minimized.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christoph M. Angerer, Raphael Polig
  • Patent number: 9535673
    Abstract: A method for significantly reducing compilation time of an application program is provided for compiling the program using profile-directed feedback (PDF). The method applies an additional analysis process between a training run of the application program and a whole program compilation of the application. This analysis process examines a PDF profile file(s) produced during the training run and aggregates data from the PDF file to determine a maximum block counter associated with each source file of the application. Only those source files having maximum block counters in a specified top percent of all the source files of the application have their fat binaries included in the whole program compilation.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shimin Cui, William G. O'Farrell, Graham K. Yiu
  • Patent number: 9524175
    Abstract: Methods and apparatus for target typing of overloaded method and constructor arguments are described. A method comprises determining whether source code of a program includes, as an argument to an overloaded operation invocation, an expression whose type is context-dependent. The method further comprises, if the source code includes such an argument, providing the expression as an input to an overload resolver, and determining at the overload resolver whether (a) each argument of the invocation is compatible with types of corresponding parameters in one or more declarations and (b) whether a particular declaration among such a set of declarations can be identified as the most specific. If both conditions are met, the method comprises generating executable instructions for the invocation.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 20, 2016
    Assignee: Oracle International Corporation
    Inventors: Maurizio Cimadamore, Daniel Lee Smith, Brian Goetz
  • Patent number: 9524153
    Abstract: A template function is received. The template function includes one or more data types. A single abstract instantiation of the template function is created. An abstract internal descriptor for each data type is created. A map set for each abstract internal descriptor is created. The number of instantiations required and the type of instantiation required is provided. A finished object is created using each map set. The finished object is a translation of the intermediate representation into assembly code.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: December 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Xiao Feng Guan, JiuFu Guo, Jin Song Ji, Jia Bing Liu
  • Patent number: 9495542
    Abstract: A method for software inspection analyzes a body of computer code to assess whether the body of computer code contains malware. Various embodiments extract the executable elements of the body of computer code and modify those elements using rules defining the format of instructions for the programming language in which the computer code was written, and using rules defined from the security specification of that programming language, to produce a model of the body of computer code. The method then analyzes the model using a model checking system, which determines whether any of the language rules have been violated, in which case the method flags the computer code as potentially including malware.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 15, 2016
    Assignee: Trustees of Boston University
    Inventors: Mark C. Reynolds, Azer Bestavros, Assaf J. Kfoury
  • Patent number: 9489182
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for transparently instrumenting a build system. One of the methods includes setting, in an execution environment of a computer system, a first environment variable that specifies a custom agent to be executed in the execution environment. A request by the system to create a virtual machine using a default create VM function is intercepted by a custom create VM function. The custom create VM function removes the first environment variable from the execution environment, and the custom create VM function executes the default create VM function to invoke a VM having the custom agent without the execution environment having the first environment variable being set.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 8, 2016
    Assignee: Semmle Limited
    Inventor: Peter Cawley
  • Patent number: 9483271
    Abstract: Provided herein is a compressed cache design to predict indirect branches in a microprocessor based on the characteristics of the addresses of the branch instructions. In one aspect, a method for predicting a branch target T in a microprocessor includes the following steps. A compressed count cache table (CTABLE) of branch targets indexed using a function combining a branch address and a branch history vector for each of the targets is maintained, wherein entries in the CTABLE contain only low-order bits of each of the targets in combination with an index bit(s) I. A given one of the entries is obtained related to a given one of the branch targets and it is determined from the index bits I whether A) high-order bits of the target are equal to the branch address, or B) the high-order bits of the target are contained in an auxiliary cache table (HTABLE).
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Tejas Karkhanis, David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9477461
    Abstract: Method for generation of a live update including compiling original source code into a first intermediate representation (IR) code; compiling modified source code into second IR code; analyzing and comparing the first and second IR codes to identify variables and functions that were changed generating a part of final IR code with all the original variables and functions; generating an additional part of final IR code with new code for modified portions of the changed original functions, added functions and variables, and marking it for compilation into special code/data sections; and compiling a new object code and a final executable binary based on the final IR. The final executable object code includes the original code and data from original application binary, and a live update code and data from additional part of final IR generated. The live update code and data refer to original code and data where needed via standard object code relocation information.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: October 25, 2016
    Assignee: Cloud Linux Zug GmbH
    Inventor: Kirill Korotaev
  • Patent number: 9430205
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9417872
    Abstract: A computer-readable recording medium stores a program for causing an apparatus to execute an address managing process including: associating information that identifies a branch destination routine of a branch instruction with a jump instruction in which a relative address to the branch destination routine, and generating the associated information and jump instruction in a branch destination management entry on a memory; setting a relative address to a position of the jump instruction that corresponds to the information that identifies the branch destination routine of the branch instruction, as a branch destination relative address of the branch instruction; and changing the jump destination of the jump instruction that corresponds to the information that identifies the branch destination routine, to a relative address to a position of the branch destination routine of the movement destination, with reference to the branch destination management entry when the branch destination routine is moved.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: August 16, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Masafumi Hashiguchi
  • Patent number: 9411964
    Abstract: An example process includes identifying, by one or more processing devices, a location in computer code that is subject to vulnerability, where the location corresponds to a memory access that is repeatable and that operates on a particular type of variable; and performing processes, by one or more processing devices, to heal the vulnerability. The memory access may be part of a system-to-system or a user-to-system interaction that is repeatable.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 9, 2016
    Assignee: BlueRISC, Inc.
    Inventors: Csaba Andras Moritz, Kristopher Carver, Jeffry Gummeson
  • Patent number: 9400663
    Abstract: A method, system, and computer program product for managing a managing a middleware architecture is disclosed. As such, a plurality of specification levels can be managed concurrently within a same runtime. An application manager and a set of runtime execution stacks are established to form a middleware. The application manager is configured to establish an interface to the set of runtime execution stacks. The runtime execution stacks are configured to run independent of one another using representative specification technology runtimes. A request to start an application is received. The application includes an application manifest. A particular runtime execution stack of the set of runtime execution stacks on which to run the application is determined. The determination is made based on the application manifest and the representative specification technology runtimes. Using the particular application runtime execution stack, the application is started.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dana M. Duffield, Dana L. Price, James I. Knutson, King Shing K. Lui, Leho Nigul
  • Patent number: 9400889
    Abstract: A computer readable medium includes executable instructions to analyze program instructions for security vulnerabilities. The executable instructions convert diverse program instruction formats to a common format. A system model is derived from the common format. A static analysis is performed on the system model to identify security vulnerabilities. Security vulnerabilities are then reported.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: July 26, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brian Chess, Arthur Do, Sean Fay, Roger Thornton
  • Patent number: 9367560
    Abstract: Disclosed are methods of synchronizing changes in a directory service, comprising receiving a sync request comprising a token from a sync client and returning a response to the sync client comprising a token and changes. Embodiments include collecting and returning changes that are new to the sync client, collecting and returning changes from first and second directory servers, and returning a unified token. The changes may include changes to a dataset that is partitioned over first and second directory servers, and the partitioning may include entry-balancing. Also disclosed are embodiments of a directory service comprising first and second directory servers, each comprising a change set with changes, and a proxy server configured to collect and send changes in the change sets that are new to a sync client, and proxy server and a directory server for use in synchronizing changes in a directory service.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 14, 2016
    Assignee: UNBOUNDID, CORP.
    Inventors: David Ely, Andrew Coulbeck, Trevor Thompson, James Synder
  • Patent number: 9355019
    Abstract: The present invention provides a method of test cases reduction based on program behavior slices. In the present invention, during a static analysis stage, analyzing a control flow and an information flow of a program according to input program codes, extracting control dependence and data dependence of the program; calculating potential dependence of the program according to the control dependence and the data dependence of the program; on the basis of the control dependence, the data dependence and the potential dependence, constructing combination dependence of the program; during a dynamic execution stage, according to an execution path and the dependence relation, calculating program behavior slices covered by the path and program behavior slices uncovered by the path, and guiding symbolic execution to generate a path capable of covering new program slices according to the uncovered program behavior slices.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 31, 2016
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Xiaohong Guan, Qinghua Zheng, Ting Liu, Haijun Wang
  • Patent number: 9342283
    Abstract: The technology is directed to profiling binary code based on a computed “density” of functions in the code. The density of a function can be computed as the frequency of execution of the function divided by the size of the function. Functions that execute more often and are smaller in size (“dense functions”) are moved towards the “front” (e.g., beginning) of the binary code. The frequency of execution can be measured at runtime using a performance measurement tool without requiring modification of the binary code or corresponding source code. After density is computed (e.g., over a period of time) for functions, it can be used to cause linkers to rearrange the binary code to place denser functions closer to the “front” of the binary code. By loading denser functions first (e.g., into processor caches and translation lookaside buffer (“TLB”)), the technology reduces cache and TLB misses, and thereby improves system performance.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 17, 2016
    Assignee: Facebook, Inc.
    Inventor: Bertrand Allen Maher
  • Patent number: 9342340
    Abstract: A virtual runtime module that omits an internal functional implementation of an associated executable module and that includes a runtime-resolvable public interface of the associated executable module is obtained using a processor within a module-based system. The virtual runtime module within the module-based system is resolved, using the runtime-resolvable public interface of the virtual runtime module, to satisfy dependencies associated with the executable module within the module-based system. At least a portion of the internal functional implementation of the associated executable module within the module-based system is installed during runtime using the resolved virtual runtime module.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Graham C. Charters, David J. Vines, Timothy J. Ward
  • Patent number: 9342389
    Abstract: An address is received. One or more neighbors associated with the received address is/are determined. One or more neighboring hot metrics is/are determined for the one or more neighbors associated with the received address. A hot metric for the received address is determined based at least in part on the neighboring hot metrics.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 17, 2016
    Assignee: SK Hynix Inc.
    Inventors: Xiangyu Tang, Frederick K. H. Lee, Jason Bellorado, Lingqi Zeng, Zheng Wu
  • Patent number: 9335946
    Abstract: A method includes, if functional units assigned with multiple reserved areas is not driven, storing data with one of a data withdrawal condition set in the multiple reserved areas, and if the functional unit is driven, processing data stored in the one of the multiple reserved areas to restore the multiple reserved areas for driving the functional units based on the one of the data withdrawal condition set. An apparatus comprises a memory including multiple reserved areas and multiple non-reserved areas, wherein if a functional unit assigned with one of the multiple reserved areas is not driven, data is stored in the one of the multiple reserved areas with one of a data withdrawal condition set, and when the functional units is driven, data stored in the one of the multiple reserved areas is processed to restore the one of the multiple reserved areas.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee-Sub Shin
  • Patent number: 9335817
    Abstract: A method and apparatus to maintain a plurality of executables for a task in a device are described. Each executable may be capable of performing the task in response to a change in an operating environment of the device. Each executable may be executed to perform a test run of the task. Each execution can consume an amount of power under the changed operating environment in the device. One of the executables may be selected to perform the task in the future based on the amounts of power consumed for the test runs of the task. The selected one executable may require no more power than each of remaining ones of the executables.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: May 10, 2016
    Assignee: Apple Inc.
    Inventor: Charles R. Overbeck
  • Patent number: 9311103
    Abstract: An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes and at least one operand are received and corresponding executions are performed by the arithmetic logic units on a single clock cycle. The result of the execution from one arithmetic logic unit is used as an operand by a further arithmetic logic unit. The decoding of the instruction is performed in an immediately preceding single clock cycle.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: April 12, 2016
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: David Smith
  • Patent number: 9298437
    Abstract: Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax tree into an automaton having in-transitions and out-transitions. Converting can include unrolling the quantification as a function of in-degree limitations wherein in-degree limitations includes a limit on the number of transitions into a state of the automaton. The compiler can also convert the automaton into an image for programming a parallel machine, and publishes the image. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Junjuan Xu, Paul Glendenning
  • Patent number: 9286039
    Abstract: A front-end compiler compiles source code into intermediate code, that may later be compiled into binary code. The source code defines an execution scope and includes a contract. When a contract is encountered at runtime of an execution scope, further execution of that execution scope is conditioned on whether a predicate associated with the contract is true. The front-end compiler operates so as to preserve the contract so that the contract continues to be semantically structured such that the predicate may be removed from the intermediate language code. The contract may thus continue to be understood by semantic analysis of the contract. Thus, the predicate may be understood by static analysis tools that operate on the intermediate code.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 15, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John J. Duffy, Jared Porter Parsons, Colin Stebbins Gordon, Alexander Daniel Bromfield, Martin Taillefer, David Allen Bartolomeo, Michael Barnett
  • Patent number: 9262210
    Abstract: A method, computer program product and system for workload management for an Extract, Transform, and Load (ETL) system. A priority of each workload in a set of workloads is determined using a priority rule. In response to determining that the priority of a workload to be checked has a highest priority, it is indicated that the workload has the highest priority. It is determined whether at least one logical resource representing an ETL metric is available for executing the workload. In response to determining that the workload has the highest priority and that the at least one logical resource is available, it is determined that the workload is runnable.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian K. Caufield, Yong Li, Xiaoyan Pu