Abstract: A deep learning model trained to learn to predict source code is tuned for a target source code generation task through reinforcement learning using a reward score that considers the quality of the source code predicted during the tuning process. The reward score is adjusted to consider code-quality factors and source code metrics. The code-quality factors account for the predicted source code having syntactic correctness, successful compilation, successful execution, successful invocation, readability, functional correctness, and coverage. The source code metrics generate a score based on how close the predicted source code is to a ground truth code.

Abstract: Methods, systems, apparatuses, devices, and computer program products are described. A virtual machine may receive, from an application associated with a tenant, a request to perform a cryptographic operation for the application at the virtual machine. Based on receiving the request, the virtual machine may determine that the tenant is limited to using a designated set of cryptographic operations in accordance with a cryptographic operation validation policy associated with the tenant. In some examples, the virtual machine may identify a designated version of the cryptographic operation, from the designated set of cryptographic operations, that corresponds to the cryptographic operation indicated by the request in satisfaction of the cryptographic operation validation policy. The virtual machine may execute the designated version of the cryptographic operation and return a result of the execution to the application.

Abstract: According to an embodiment, an electronic device includes: at least one processor and a memory configured to store instructions that can be executed by the processor, wherein the processor may be configured to: monitor information about the storage space of the memory and usage histories of a plurality of objects executed by the processor, determine a target object, of which the compile scheme is to be changed, among the plurality of objects based on at least one of the information and the usage histories; and increase the free storage space of the memory by changing the compile scheme of the target object.

Abstract: A first firmware source code portion corresponding to an immutable firmware portion of specific firmware to be deployed with embedded devices is identified. A second different firmware source code portion corresponding to a mutable firmware portion of the specific firmware to be deployed with the embedded devices is identified. The first firmware source code portion is used to generate the immutable firmware portion of the specific firmware. The second firmware source code portion is used to generate the mutable firmware portion of the specific firmware. The immutable firmware portion of the specific firmware is caused to be installed in fixed storage drives of an embedded device in the embedded devices. The mutable firmware portion of the specific firmware is caused to be installed in swappable storage drives of the same embedded device.

Abstract: A system and method for building a hardware accelerator. The system has at least one processor including at least one core configured to perform based on machine code an operation for a specific algorithm of the hardware accelerator. The system has a code analyzer for reconfiguring the at least one processor to execute with the machine code the specific algorithm. The code analyzer is configured to repeatedly execute at least one of a) a static analysis on a software program for performance of the specific algorithm and b) a dynamic analysis regarding the machine code on different input sets of data. The code analyzer is configured to analyze results of the static analysis or the dynamic analysis to determine a configuration of the machine code for execution of the specific algorithm on the hardware accelerator.

Abstract: A system for executing a software program comprising processing units and a hardware processor configured to: for at least one set of blocks, each set comprising a calling block and a target block of an intermediate representation of the software program, generate control-transfer information describing at least one value of the software program at an exit of the calling block (out-value) and at least one other value of the software program at an entry to the target block (in-value); select a set of blocks according to at least one statistical value collected while executing the software program; generate a target set of instructions using the target block and the control-transfer information; generate a calling set of instructions using the calling block and the control-transfer information; configure a calling processing unit to execute the calling set of instructions; and configure a target processing unit to execute the target set of instructions.

Abstract: A method includes generating output code based on input code using a compiler or translator and providing the output code to one or more platforms for execution. The method also includes receiving feedback associated with the execution of the output code, where the feedback identifies at least one of: one or more failures during the execution of the output code and one or more performance characteristics of the execution of the output code. The method further includes modifying the compiler or translator based on the feedback and generating additional output code using the modified compiler or translator.

Abstract: The present disclosure relates to a method for generating a program for use in an accelerator for deep learning. The method may include receiving, by a computing device, a deep learning application, generating an element-wise operation list included in the deep learning application, generating an intermediate expression from the element-wise operation list, and generating, based on the intermediate expression, a program for use in an accelerator for the deep learning application.

Abstract: Example embodiments of the present disclosure provide, in one example aspect, an example computer-implemented method for verification of a shared cache. The example method can include retrieving a precompiled shared cache entry corresponding to a shared cache key, the shared cache key being associated with an operation request. The example method can include obtaining a directly compiled resource associated with the operation request. The example method can include certifying one or more portions of the shared cache based at least in part on a comparison of the precompiled shared cache entry and the directly compiled resource.

Abstract: A computing device may access a target code for implementing an application. The device may identify addresses for one or more functions or one or more variables associated with the target code. The device may generate an interval tree comprising a root node and one or more function nodes. The device may in response to the target code invoking a function or variable: generate an intercept function configured to intercept communication between the target code and a call address for the at least one of the one or more functions or the one or more variables invoked by the target code. The device may intercept data communicated between the target code and the call address. The device may store the intercepted data as a function node in the interval tree. The device may transmit the interval tree to a user device.

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

Abstract: Provided herein are an electronic apparatus and a method for controlling thereof. The method for controlling an electronic apparatus may include: acquiring a voice command, performing voice recognition of the voice command and acquiring a first text, identifying a prestored indexed word among a plurality of words included in the first text, identifying a rule template among a plurality of prestored rule templates including the indexed word and slots matched to at least one word excluding the indexed word among the plurality of words, and acquiring a control command corresponding to the voice command based on the identified rule template.

Abstract: A programming support program causes an electronic computer to execute: a first conversion step of converting a first program described in a ladder language into a second program described in an intermediate language; a second conversion step of converting the second program into a third program described in a procedural language; a circuit display component generation step of, when a result of analysis of each block of the second program satisfies a predetermined condition, generating a circuit display component representing a content of a block satisfying the condition; and a display step of displaying the third program and the circuit display component in a format enabling recognition of correspondence between the circuit display component and a block of the third program.

Abstract: A method, a computer system, and a computer program product for security risk analysis is provided. Embodiments of the present invention may include collecting operational data. Embodiments of the present invention may include building pipelines. Embodiments of the present invention may include localizing security issues using the operational data on an unsupervised model. Embodiments of the present invention may include constructing a semantic graph using shift-left data. Embodiments of the present invention may include constructing a mapping between the operational data and the shift-left data. Embodiments of the present invention may include clustering collected datasets. Embodiments of the present invention may include creating an active learning cycle using ground truth.

Abstract: Embodiments for providing intelligent land use planning recommendations using heterogeneous temporal datasets in a computing environment. One or more positive land-use interventions, one or more negative land-use interventions, or a combination thereof may be recommended for a selected geographical region from heterogeneous chronological data.

Abstract: An apparatus and a method for executing a customized production line using an artificial intelligence development platform, a computing device and a computer readable storage medium are provided. The apparatus includes: a production line executor configured to generate a native form of the artificial intelligence development platform based on a file set, the native form to be sent to a client accessing the artificial intelligence development platform so as to present a native interactive page of the artificial intelligence development platform; and a standardized platform interface configured to provide an interaction channel between the production line executor and the artificial intelligence development platform. The production line executor is further configured to generate an intermediate result by executing processing logic defined in the file set and to process the intermediate result by interacting with the artificial intelligence development platform via the standardized platform interface.

Abstract: Generation of an executable file derived from a parent executable file having ranges of physical addresses referencing a binary code of at least one core feature (CR), a binary code of a set of native features (F), bytecodes of a set of java features (Pkg), by selecting at least one native feature from the set of native features to be removed, defining the range of physical addresses where the binary code of the selected native feature is stored, selecting at least one java feature from the set of java features to be relocated, and relocating the bytecodes of said at least one selected java feature in the defined range of physical addresses.

Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Abstract: A parametric constant resolves to different values in different contexts, but a single value within a particular context. An anchor constant is a parametric constant that allows for a degree of parametricity for an API point. The context for the anchor constant is provided by a caller to the API point. The anchor constant resolves to an anchor value that records specialization decisions for the API point within the provided context. Specialization decisions may include type restrictions, memory layout, and/or memory size. The anchor value together with an unspecialized type of the API point result in a specialized type of the API point. A class object representing the specialized type is created. The class object may be accessible to the caller, but the full value of the anchor value is not accessible to the caller. The API point is executed based on the specialization decisions embodied in the anchor value.

Abstract: The present disclosure relates to systems and methods for code optimization. The methods include generating, based on a first macro of a user code, an assembly code corresponding to the user code. The first macro includes one or more parameters relating to one or more branch codes, and the assembly code includes assembly branch codes corresponding to the branch codes and jump codes corresponding to the assembly branch codes. The methods further include obtaining, based on a second macro of the user code, target information for identifying an execution condition of the one or more branch codes, and determining, based on the assembly code and the target information, a compiled user code. When being executed, the compiled user code may call, based on the target information, a procedure to determine a value of the execution condition. The procedure is configured to modify an execution flow of the compiled user code.

Abstract: An industrial automation component, a computer program and a computer-readable medium and method for configuring an industrial automation component, wherein at least one feature of the industrial automation component that is not configurable with an engineering system supporting the component, non-supported feature, is configured by interpreting a description of a configuration of the at least one non-supported feature with an on-board compiler of the component and integrating the interpreted description to a basic configuration having been generated with the engineering system and with respect to at least one further feature, supported feature, of the component.

Abstract: Methods and systems provide for a notebook interactive programming environment, having out-of-order code-cell execution, which communicates potential cell execution outcomes. If an event handler receives an event (e.g., open notebook, code change, code execution, etc.) for a cell, without a request for a specific type of analysis (e.g., data-leakage, stale-state), intra-cell analysis is executed based-on the cell's abstract semantics, and an abstract state and pre-summaries are output that indicate the cell's propagation dependency (unbounded variables). If an analysis is associated with the event, starting with the stored abstract state, inter-cell analysis is recursively executed on successor cells having propagation dependencies, until a terminating criteria is reached. Outcomes (e.g., affected cell, line number, bug type, metrics, etc.) are sent via the notebook user-interface to warn users, ahead of concrete code execution, of hypothetical unsafe or safe actions in executing the notebook's code cells.

Abstract: A processing system includes a compiler that automatically identifies sequences of instructions of tileable source code that can be replaced with tensor operations. The compiler generates enhanced code that replaces the identified sequences of instructions with tensor operations that invoke a special-purpose hardware accelerator. By automatically replacing instructions with tensor operations that invoke the special-purpose hardware accelerator, the compiler makes the performance improvements achievable through the special-purpose hardware accelerator available to programmers using high-level programming languages.

Abstract: In a presentation control, another presentation request of another content is accepted from another application while presenting a content of one application, which content is preferentially presented is arbitrated based on a rule definition including: an attribute of the content that defines either a cancellation for withdrawing the presentation request or an on-standby without withdrawing the presentation request; and a constraint equation that defines an exception rule for defining a setting of the content that has lost arbitration as either the on-standby or the cancellation; and one of the contents arbitrated is presented to a presentation area.

Abstract: A non-transitory computer-readable recording medium stores a program for causing a computer to execute a process, the process includes extracting an optimization method and an optimization non-applicable condition indicating a reason why the optimization method is not applicable, from an optimization report created at a time of compiling software, determining an index value of optimization application easiness for each of a plurality of processing blocks included in the software, based on the optimization method and the optimization non-applicable condition, and determining an optimization target processing block to be optimized among the plurality of processing blocks included in the software, based on the index value.

Abstract: A system and method for load fusion fuses small load operations into fewer, larger load operations. The system detects that a pair of adjacent operations are consecutive load operations, where the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive load micro-operations refers to both of the adjacent micro-operations being load micro-operations. The consecutive load operations are then reviewed to determine if the data sizes are the same and if the load operation addresses are consecutive. The two load operations are then fused together to form one load micro-operation with twice the data size and one load data micro-operation with no load component.

Abstract: Apparatus and methods are disclosed for performing block floating-point (BFP) operations, including in implementations of neural networks. All or a portion of one or more matrices or vectors can share one or more common exponents. Techniques are disclosed for selecting the shared common exponents. In some examples of the disclosed technology, a method includes producing BFP representations of matrices or vectors, at least two elements of the respective matrices or vectors sharing a common exponent, performing a mathematical operation on two or more of the plurality of matrices or vectors, and producing an output matrix or vector. Based on the output matrix or vector, one or more updated common exponents are selected, and an updated matrix or vector is produced having some elements that share the updated common exponents.

Abstract: Certain embodiments described herein relate to methods and systems for detecting unexpected behavior associated with a process. In certain embodiments, a method comprises receiving a memory allocation request, the request indicating one or more memory segments to be allocated in memory of a computing system. The method further comprises allocating the one or more memory segments in the memory based on the memory allocation request. The method further comprises allocating one or more decoy memory segments in the memory based on the memory allocation request. The method further comprises trapping an input/output (I/O) operation. The method further comprises detecting an unexpected behavior associated with the I/O operation based on determining that the I/O operation impacts at least one of the one or more decoy memory segments. The method further comprises performing one or more actions based on the detection.

Abstract: Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.

Abstract: A data processing apparatus adapted to output recommendation information for modifying source code, includes: compiler circuitry to compile the source code and to output compiled code for the source code, processing circuitry to execute the compiled code, profile circuitry to monitor the execution of the compiled code by the processing circuitry and to generate profile information for the execution of the compiled code, the profile information including one or more statistical properties for the execution of the compiled code, and recommendation circuitry to output the recommendation information for the source code, the recommendation circuitry including a machine learning model to receive at least a portion of the profile information and trained to output the recommendation information for the source code in dependence upon one or more of the statistical properties, in which the recommendation information is indicative of one or more editing instructions for modifying the source code.

Abstract: The present disclosure provides computer-executable tools which, implemented in a programming language library, may enable source code written using the library to be compiled to object code instrumented for function-level dynamic analysis of memory allocation functions. By tracking heap reads and writes of each target function, symbols may be mapped to memory addresses allocated therefor, and values of input arguments of functions may be mapped to values of output returns. Based on this information, pure functions which embody redundant computations across multiple executions thereof may be identified, while non-pure functions may be screened out.

Abstract: Systems and methods of cyber hardening software by modifying one or more assembly source files. In some embodiments, the disclosed SME tool transparently and seamlessly integrates into the build process of the assembly source files being modified. For example, upon integration of the disclosed SME tool into the application's development environment, the modifications in the final executable are transparent to the developer and can support other cyber hardening techniques. The SME tool includes a preprocessing tool for identifying attributes (e.g., functions) associated with the assembly source file. The SME tool also includes a transformation tool for making modifications of the assembly source file. In some embodiments, the transformations correspond to applying one or more transformations to the attributes associated with the assembly source file.

Abstract: Various systems and methods are provided for implementing a software defined industrial system. In an example, self-descriptive control applications and software modules are provided in the context of orchestratable distributed systems. The self-descriptive control applications may be executed by an orchestrator or like control device, configured to: identify available software modules adapted to perform functional operations in a control system environment; identify operational characteristics that identify characteristics of execution of the available software modules that are available to implement a control system application; select a software module for execution based on the operational configuration and the operational characteristics identified in the manifest; and cause the execution of the selected software module in the control system environment based on an application specification for the control system application.

Abstract: Provided are techniques for using relocatable debugging information entries to save compile time when there are changes to source code. While compiling source code, for an unchanged function, a copy is made of a relocatable debugging information entries table and of a relocation information table. In addition, for a changed function, a new relocatable debugging information entries table and a new relocation information table are generated. The copy of the relocatable debugging information entries table and the new relocatable debugging information entries table are merged. The copy of the relocation information table and the new relocation information table are merged. The relocatable debugging information entries in the merged relocatable debugging information entries table are resolved according to information in the merged relocation information table to generate relocated Debugging with Attributed Record Formats information, which is stored in an object file that corresponds to the source code.

Abstract: A distributed computing environment is provided with a system and method for supporting rare copy-on-write data access. The system operates a data structure in a read only pattern suitable for serving a plurality of read requests with reduced overhead. The system, upon receiving a write request, creates a copy of data to execute the write request. The system defers writing the mutated data back to the read-only data structure. The system thus allows for multiple mutations to be made to the copy of the data using a read/write access pattern. After a number of read-only requests are received, the mutated data is written back to the read-only data structure. A monitor counts read and write requests in order to reduce overall read/write overhead and enhance performance of the distributed data grid.

Abstract: A computer system, designed according to a particular architecture, compiles and execute a general quantum program. Computer systems designed in accordance with the architecture are suitable for use with a variety of programming languages and a variety of hardware backends. The architecture includes a classical computer and a quantum device (which may be remote from the local computer) which includes both classical execution units and a quantum processing unit (QPU).

Abstract: There are provided systems and methods for reducing computing calls for webpage load times and resources to reduce power usage and/or carbon footprints caused by repetitive navigations. A service provider, such as an online transaction processor, may provide computing services to users, which require computing devices of the users to interact with the service provider and load data on the computing devices, including webpages and application interfaces. Each of data loading event may have a cost, where repeating events may lead to unnecessary power usage, carbon emissions and/or a carbon footprint. A graph algorithmic process may utilize state diagrams of processing flows for data loading events with attributes for each data loading event to identify problematic repeated events. Once the problematic events are identified, the service provider may identify corrective actions to avoid or reduce the repetitive events, such as by merging data into one or more events.

Abstract: Methods and systems are presented for providing a scalable communication framework for facilitating computing services to computer nodes across multiple availability zones. One or more communication servers act as a communication proxy for a processing server configured to perform the computing services. Upon receiving a service request from a computer node, the communication server establishes a synchronous communication session with the computer node. The communication server generates a request message and inserts the request message in a downstream queue accessible by the processing server. The processing server retrieves the request message from the downstream queue and performs the computing services based on the request message. Outputs from the computing services are encapsulated within a response message and then inserted in an upstream queue.

Abstract: In some implementations, there is provided a method that includes generating a user interface to enable selection of configuration information and initiation of a build of an application instance; receiving, from the user interface, an indication to initiate the build of the application instance; assigning at least one slave node to build, based on the configuration information, the application instance; obtaining, from at least one repository, build information including at least one of a command script, a dataset, and an application instance template; generating, based on the build information, a container file; storing the container file; generating the container image and storing the container image; and executing the image to provide a container. Related systems and articles of manufacture are also disclosed.

Abstract: Systems, methods, and computer-readable for defining host functionalities in a computing environment include obtaining two or more snapshots comprising information pertaining to two or more processes executing in two or more hosts, the two or more snapshots being obtained at two or more points in time from the two or more hosts. One or more long-running processes amongst the two or more processes are identified based on one or more criteria associated with long-running processes. One or more priorities associated with the one or more long-running processes and used for defining functionalities for at least a subset of the two or more hosts, where high priorities are assigned to long-running processes, such as web server or database server processes, which are unique to at least the subset of the two or more hosts. Resources may be provisioned based on these host functionalities.

Abstract: This application describes methods, systems, and apparatus, including computer programs encoded on computer storage media, of an AI-assisted compiler. An example method includes obtaining intermediate code and executable code generated by compiling a computer program with a compiler; determining a reward based on one or more traces obtained by executing the executable code in a runtime system; generating an embedding vector based on the intermediate code and the one or more traces to represent code execution states; determining, using a reinforcement learning agent, one or more optimization actions based on the embedding vector and the reward; and updating the compiler by applying the one or more optimization actions.

Abstract: A system and method for managing data storage and data access with querying data in a distributed system without buffering the results on intermediate operations in disk storage.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: Software releases can be generated based on controller metadata in some examples. In one such example, a system can receive metadata files including a set of properties for controllers executable in a distributed computing environment to manage software components collectively forming a software application. Each metadata file can specify respective properties for a respective controller. The system can extract deployment details from the set of properties included in the metadata files, where the deployment details can specify how the controllers are to be deployed in the distributed computing environment. The system can then generate combined metadata that includes the deployment details from the metadata files. The system can incorporate the combined metadata into a software release, so that the software release can be used to deploy the controllers in accordance with the combined metadata.

Abstract: A system and method automatically refactor mature program code having interdependent features to remove instructions pertaining to features that are no longer used. To facilitate reduction of the number of feature dependencies to test, instrumentation data are analyzed to determine which of the available features are in actual use. A graph of feature dependencies is built based on the program configuration, and the program code is simulated, according to existing testing protocols, with various combinations of features disabled to determine whether the program continues to function without error. When features are found that can be safely removed, the codebase is automatically refactored to eliminate the implementing code corresponding to the features. The refactored code then may be further automatically retested and deployed into the production environment.

Abstract: Devices, systems and methods for reconfigurable and/or updatable lightweight embedded devices or systems are disclosed. Via use of such a device, system, or method, various capabilities for a user are provided, simplified, secured, and/or made more convenient. The system may interact with various other devices or systems, including those that are cloud-based or communicate through the cloud, and may utilize various local sensors, in order to provide one or more of improved access, monitoring, or diagnostics, and so forth.

Abstract: This invention relates to a method of optimization of a computer program, comprising: a first step (S11, S12, S13, S14) of determination of a call of a function having at least one input parameter, said call corresponding to a first criterion according to which said input parameter is inside an interval substantially smaller than the range of possible values for said input parameter, and to a second criterion corresponding to a desired accuracy for said call; a second step (S2) of automatic generation of an executable code for implementing said function, minimizing execution time for said input parameter being within said interval and compliant with said desired accuracy; a third step (S3) of replacing the existing code implementing said function by the executable code generated at said second step.

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

Abstract: Systems and methods are described herein for translating code segments from one high-level programming language to another. The system may maintain any suitable number of decoding computing modules each configured to translate code of a corresponding language to an intermediate configuration object that represents an abstracted version of the code that identifies the operations performed on one or more variables and the order by which these operations are performed in the code. The intermediate configuration object can be used to generate new code segments expressed in different programming languages. In some embodiments, generating the a new code segment in a given programming language from the intermediate configuration object can be performed by an encoding computing module that is specific to that language.