Abstract: A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture, computing a set of candidate configurations of resources required for vectorizing the data in the architecture, where the computing step includes configuring a vector pointer register of the architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of the architecture, selecting one of the candidates in accordance with predefined selection criteria, and implementing the selected vectorization configuration in the architecture.

Abstract: A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prologue and epilogue are implicitly created and maintained within the hardware in the invention, a significant reduction in code size can be achieved compared to software-only modulo scheduling. Furthermore, loops with iteration counts less than the number of concurrent iterations present in the kernel are also automatically handled. This hardware enhanced scheme achieves the same performance as the fully-specified standard method. Furthermore, the hardware reduces the power requirement as the entire fetch unit can be deactivated for a portion of the loop's execution.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.

Abstract: One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data references to be prefetched. This analysis can involve: using a two-phase marking process in which blocks that are certain to execute are considered before other blocks; and analyzing complex array subscripts. Next, the system inserts prefetch instructions into the code in advance of the identified data references. This insertion can involve: dealing with non-constant or unknown stride values; moving prefetch instructions into preceding basic blocks; and issuing multiple prefetches for the same data reference.

Abstract: A code optimizer is used to optimize a computer program that references a database by determining the characteristics of the database and making suitable optimizations based on the characteristics of the database. By taking into account the characteristics of a database referenced in the computer program, the optimizer may make suitable optimizations to the computer program. Such optimizations include, without limitation, removing unnecessary calls to the database, removing unnecessary loops, removing unnecessary database operations, providing compile-time errors, and replacing dynamic calls with static data.

Abstract: An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.

Abstract: A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a main loop structure having indexing expressions based on the original loop structure is included. The indexing expressions included in the main loop preferably cannot produce an underflow or an overflow. Also included in the range check elimination loop structure is a post-loop structure based on the original loop structure that is capable of testing indexing expressions for overflow.

Abstract: A computer implemented method to be implemented by a computer, which sequentially consecutively performs a plurality of predetermined process, when the computer receives an interrupt request to supply monitoring information which represents the processing state of the computer. The computer implemented method determines whether or not to execute an interrupt process, in which the monitoring information is supplied to the monitoring unit based on the information received when the computer receives the interrupt request. The interrupt program module further supplies the monitoring information which corresponds to the computer process which occurred immediately before deciding to execute an interrupt process. The interrupt program module also cancels an interrupt process after the monitoring information is sent to the monitoring unit.

Abstract: A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.

Abstract: A method for statically allocating a procedure return address includes separating a software program including multiple procedures into a cyclic part and an acyclic part, allocating a static address for the return address of a procedure in the acyclic part and modifying at least one of the procedures to refer to the static address for the procedure return address.

Abstract: Parallelization of loops is performed for loops having indirect loop index variables and embedded conditional statements in the loop body. Loops having any finite number of array variables in the loop body, and any finite number of indirect loop index variables can be parallelized. There are two particular limitations of the described techniques: (i) that there are no cross-iteration dependencies in the loop other than through the indirect loop index variables; and (ii) that the loop index variables (either direct or indirect) are not redefined in the loop body.

Abstract: A method is provided for co-simulating a digital circuit using a simulation engine (45) which communicates with one or more first programming languages by means of a foreign language interface and which communicates directly with one or more second programming language. At least one first model (2, 3) or at least one first part of the digital circuit is provided in at least one high-level hardware description language which supports concurrent processes communicating with each other. The at least one first model is converted (50, 51) to at least one software model in the at least one first language.

Abstract: Techniques that allow the operations of a program to be intercepted and intervened with are known. These techniques are restricted by the same limited view of the program's data that is currently available at a base level of an object or method. Some aspects need access to more information about the program's data of one or more objects than is available at the base level. An aspect of aspect-oriented programming systems, methods and environments examines the results of a computation at one stage. That aspect affects only subsequent stages of the computation, so that no circularity exists. Custom flow analyses, whether local or global, can also be performed at each stage to propagate non-local information. “Macro” style programming can be reduced or avoided, as programming can be facilitated in terms of manipulating the results of various computational stages instead of in terms of manipulating blocks of code.

Abstract: A transformation technique for nested loops. A virtual iteration space may be determined based on an unroll factor (UF). The virtual iteration space, which includes the actual iteration space, is fanned such that, the virtual iteration space may be evenly divided by a selected UF. Once the virtual iteration space has been calculated or determined, the virtual iteration space is “cut” into regular portions by one or more unroll factors. Portions of the actual iteration space which do not fill the cut portions of the virtual iteration space or which fall outside these cuts which have been evenly divided by the unroll factor form a residue which is calculated. The portions of the actual iteration space which remain arc also evenly divided by the unroll factor(s). An outer loop for this remaining portion of the actual iteration space is then unrolled. This unrolled portion forms a perfect nested loop.

Abstract: A code optimizing procedure involves isolating code from a loop construct, executed a predetermined number of times, and optimizing the code for execution conditions which cause the loop to be executed that number of times. This code is compared against corresponding code which has not be optimized, and it is determined whether the inclusion of this code is favorable. If the benefits of including this code are judged to be significant, the code is modified by inclusion of this optimized code, which is conditionally executed when the loop is encountered.

Abstract: In one embodiment, disambiguation of memory references, such as structure field accesses, of a computer program is performed. Disambiguation may be effected by identifying pure pointer variables within the computer program and applying at least one disambiguation rule to memory references associated with the pure pointers to determine whether the references are disjoint.

Abstract: Methods and apparatus are disclosed for improved loop unrolling by a compiler. A large class of loops exists for which effective loop unrolling has not previously been performed because they are too large to be completely unrolled, but which do not have a single hot trace that covers an entire loop iteration. The present invention recognizes such loops that have partial hot traces identified using profile data. A set of instructions which constitute a proper superset of the hot trace and a proper subset of the entire loop, and which forms a complete loop iteration is identified. This set of instructions can then be unrolled without unrolling the entire loop.

Abstract: Interlocked floating-point instructions are detected, and a register address referring to and assigning an operand in the interlocked instructions is changed to an odd-number address not assigned as any operation at the time of compiling. Next, an instruction not in any register-dependency relation with the interlocked instructions is detected, and the detected instruction is inserted between instructions interlocked with each other. Thus a program can be executed with an improved efficiency.

Abstract: An apparatus may include a first storage location to store a key value of an activated correlated data values (CDV) pair and a second storage location to store a correlated value corresponding to the key value. An apparatus may also include a first storage location to store an instruction to activate a CDV pair and a second storage location to store an instruction to deactivate the CDV pair. A system may comprise a processor to fetch and execute a native instruction set including an instruction to activate a CDV pair and an instruction to deactivate the CDV pair, as well as a memory to store a table that includes the CDV pair. A machine-readable medium may include instructions causing a machine to perform a method comprising activating a CDV pair and performing a first task using the correlated value in parallel with a second task using the key value.

Abstract: A method for compiling a program to reduce the possibility of cache thrashing is provided. The method comprises identifying a loop in a program, identifying each vector memory reference in the loop, and determining dependencies between the vector memory references in the loop. Determining the dependencies includes determining unidirectional and circular dependencies. Thereafter, the vector memory references are distributed into a plurality of detail loops, wherein the vector memory references that have circular dependencies therebetween are included in a common detail loop, and the detail loops are ordered according to the unidirectional dependencies between the memory references.

Abstract: This invention relates to a method, system and program product to detect reduction variables in assignment statements in the source code for enabling the parallel execution of program loops. The reduction variables found using the method herein described can be tagged to the respective loops and passed to a compiler through compiler directives for parallelizing the reduction operation, along with the information about each variable's respective associative operator.

Abstract: A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language (100) and identifying a loop construct within the language independent model (705). A determination can be made as to whether the loop construct is bounded (725). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences 735). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique (740, 755).

Abstract: A parallel loop transformation method for race detection during an execution of parallel programs that includes generating a data structure of a condition statement branch determinant string Cstr required for loop transformation by taking an original parallel loop as an input and extracting execution path information, transforming the original parallel loop into a full race covering loop using the data structure of the condition statement branch determinant string Cstr required for loop transformation and the execution path information as an input statement, instrumenting the race detection function in order to activate the race detection function for the transformed parallel loop which are previously generated, and executing the race detection while running the parallel programs according to instrumented detection functions.

Abstract: A method and a system for scheduling a software pipelined loop with indirect loads. The system may include a data structure in communication with a processor and a memory. The processor may determine a condition associated with a potential for saturation of the data structure. Accordingly, the processor may provide a number of instructions associated with the software pipelined loop from the memory to a queue of the data structure prior to processing of the instructions by the processor based on the condition associated with a potential for saturation of the data structure.

Abstract: A method, system and program product for optimizing software in which procedure clones are created based on the control flow information for the procedure body. In an example, a control flow graph for a called procedure is constructed and, for a branching node which can direct program flow to two or more code branches of the procedure, respective clones or new procedures are formed one for each code branch. A list containing pointers to the clones and the respective branch conditions for those clones is formed. Then, for each call site, the list is scanned to see if a particular call could be replaced by a call to a clone. Meanwhile, each clone is optimized and this may lead to removal of dead code or the replacement of a particular call statement by a constant.

Abstract: Embodiments of the invention, given a conventional makefile which builds targets in serial mode, will process (e.g., compile, link, pre-process, execute, etc.) commands in parallel on those targets which, as a result of a lack of interdependency, can be built in any order. Embodiments may first identify one or more targets (i.e., object files) which are candidates for parallel compilation (“parallelization”). From the targets identified instructions are generated, which may be stored in a file, which provides the identity of targets for parallelization and the order in which these targets should be built. The instructions may then be executed (resulting in some instructions being executed in parallel) thus providing reduced compiling time and, thus, improving productivity.

Abstract: One embodiment of the present invention provides a system that facilitates multi-versioning loops to facilitate modulo scheduling. Upon receiving a computer program, the system analyzes the code to locate loops within the program. When a loop is located, the system examines the loop termination condition to determine if it is based on a “not-equal-to” condition that makes it hard to determine beforehand whether the loop will terminate. If the loop termination condition is based on a “not-equal-to” condition, the system creates multiple versions of the loop, at least one of which will terminate and can be modulo scheduled, and at least one of which might be an infinite loop and consequently cannot be modulo scheduled.

Abstract: An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating an initiation interval time (IN) for a pipelined stage of the loop. A loop operation time latency (Tld) and a number of loop operations (Np) from the pipelined stages to peel based on IN and Tld is then determined. The loop operation is peeled Np times and copied before the loop in the software code. A vector of registers is allocated and the results of the peeled loop operations and a result of an original loop operation is assigned to the vector of registers. Memory addresses for the results of the peeled loop operations and original loop operation are also assigned.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A system and method of automatically configuring memory in a data processing system, including the steps of: receiving source code containing a loop nest, wherein the loop nest includes data arrays with affine indexes; optimizing source code by relocating elements from a first array in memory to a second array in memory; and executing the optimized source code.

Abstract: A profile-based loop optimizer generates an execution frequency table for each loop that gives more detailed profile data that allows making a more intelligent decision regarding if and how to optimize each loop in the computer program. The execution frequency table contains entries that correlate a number of times a loop is executed each time the loop is entered with a count of the occurrences of each number during the execution of an instrumented instruction stream. The execution frequency table is used to determine whether there is one dominant mode that appears in the profile data, and if so, optimizes the loop according to the dominant mode. The optimizer may perform optimizations by peeling a loop, by unrolling a loop, and by performing both peeling and unrolling on a loop according to the profile data in the execution frequency table for the loop.

Abstract: A method and device for generating mapping source code to establish mapping connections between enterprise system nested array object fields and legacy system nested array object fields is disclosed. For each desired mapping connection in a received list of desired connections, a determination of an enterprise system field and legacy system field to be mapped, as well as a connection nesting level, is made. The identity of the system arrays containing the enterprise and legacy system fields is also determined. A logical tree is created which includes a root node, one leaf node for each desired connection, and, for each leaf node, N intermediate nodes interconnecting the leaf node with the root node, where N is equivalent to the determined nesting level of the connection associated with that leaf node, and where each of the N intermediate nodes that is successively further from the root node is associated with a successively more deeply nested target system array.

Abstract: A first type of debugger impact reduction includes removing, from within a loop, an initial conditional breakpoint (“ICB”); extracting a first Boolean expression (“BE_1”) therefrom; setting a special conditional breakpoint (“SCB”) including the BE_1; and reestablishing the ICB if the SCB is satisfied. Optionally, the first type may further include extracting, from code within the loop, a second Boolean expression (“BE_2”); disjunctively including its complement in the SCB; and setting a reset breakpoint at loop exit program positions to remove reset breakpoints and/or the ICB. A second type includes setting the SCB with the complement of BE_1; and removing the ICB when the SCB is satisfied. Optionally, the second type may further include conjunctively including the BE_2 in the SCB; and setting a reset breakpoint to remove reset breakpoints and/or reestablish the ICB. The above may be embodied in a method, a program debugger and an article of manufacture.

Abstract: A method for software pipelining of irregular conditional control loops including pre-processing the loops so they can be safely software pipelined. The pre-processing step ensures that each original instruction in the loop body can be over-executed as many times as necessary. During the pre-processing stage, each instruction in the loop body is processing in turn (N4). If the instruction can be safely speculatively executed, it is left alone (N6). If it could be safely speculatively executed except that it modifies registers that are live out of the loop, then the instruction can be pre-processed using predication or register copying (N7, N8, N9). Otherwise, predication must be applied (N10). Predication is the process of guarding an instruction. When the guard condition is true, the instruction executes as though it were unguarded. When the guard condition is false, the instruction is nullified.

Abstract: Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.

Abstract: Code restructuring or reordering based on profiling information and memory hierarchy is provided by constructing a Program Execution Graph (PEG) corresponding to a level of the memory hierarchy, partitioning this PEG to reduce estimated memory overhead costs below an upper bound, and constructing a PEG for a next level of the memory hierarchy from the partitioned PEG. The PEG is constructed from control flow and frequency information from a profile of the program to be restructured. The PEG is a weighted undirected graph comprising nodes representing basic blocks and edges representing transfer of control between pairs of basic blocks. The weight of a node is the size of the basic block it represents and the weight of an edge is the frequency of transition between the pair of basic blocs it connects.

Abstract: A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.

Abstract: A method of compiling an executable program from a source code file, the method includes partitioning the source code file into code regions, determining register usage of at least two instructions in a first code region, and out-lining a first of the at least two instructions to be compiled as an executable instruction.

Abstract: A method for employing architectural support for modulo-scheduled loop pipelining provided in modern processors in order to write more flexible, more efficient, and a greater variety of enhanced modulo-scheduled loops. A described embodiment of the present invention allows for arbitrary selection of any rotating predicate register to control the transition from kernel phase to epilog phase, and thereby enable multiple, parallel streams of execution within a software-pipelined loop.

Abstract: The present invention provides a technique for reducing the number of write barriers executed in mutator code without compromising garbage collector performance. To that end, when mutator instructions located within an inner-most nested loop (“inner loop”) modify references stored in one or more arrays, a compiler defers emitting write barriers corresponding to the reference modifications until after the inner loop is emitted. By deferring emission of write barriers, the mutator may execute a write barrier for each card spanned by the array instead of executing a typically larger number of write barriers corresponding to each reference modification made in an array. Thus, the invention enables the compiler to reduce the amount of write-barrier overhead performed by the mutator, consequently enabling the mutator to execute faster and more efficiently.

Abstract: A method for processing scalar and vector executions, where vector executions may be “true” vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed using one architecture. In one embodiment, a compiler analyzes code to identify sections that are vectorizable, and applies either CVA, PVA, or a combination of the two to process these sections. Register overlay is provided for storing load address information and data in PVA mode. Within each CVA and PVA instruction, enable bits describe the data streaming function of the operation. A temporary memory, TM, accommodates variable size vectors, and is used in vector operations, similar to a vector register, to store temporary vectors.

Abstract: A mechanism and method for hoisting invariant computations from loops analyzes the lifetimes of fixed processor resources defined by an instruction, and determines whether a group of computations present in multiple instructions within the lifetime are, taken together, loop-invariant and legal to hoist from the loop. If the group of computations within the lifetime of the fixed processor resource are loop-invariant and hoistable, all of the computations are hoisted out of the loop as a group. By determining the lifetimes of fixed processor resources defined in an instruction, the hoisting mechanism succeeds in hoisting out groups of computations that cannot be individually hoisted out of a loop, thereby achieving better performance when the computer program executes.

Abstract: This invention relates to a method, system and program product to detect reduction variables in assignment statements in the source code for enabling the parallel execution of program loops. The reduction variables found using the method herein described can be tagged to the respective loops and passed to a compiler through compiler directives for parallelizing the reduction operation, along with the information about each variable's respective associative operator.

Abstract: In systems and methods for land-use development, planning and management, the creation of an organized environment evolving in time and space is disclosed. The system and method is sustained by a smart infrastructure centrally or de-centrally managed to link, in a given perimeter, on developed or undeveloped sites, private and/or public equipments and deliver services to customers that generate a quality of life based on qualified and quantified parameters. The systems and methods use a definition of services and an open architecture, flexible and scalable to integrate social, economic and technology changes. In one embodiment, a framework is used to propose or offer services.

Abstract: The present invention provides a highly-flexible compiler that a user can control optimization by the compiler precisely.