Mesh Structure Patents (Class 977/767)
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Patent number: 8834967Abstract: A method of reducing the diameter of pores formed in a graphene sheet includes forming at least one pore having a first diameter in the graphene sheet such that the at least one pore is surrounded by passivated edges of the graphene sheet. The method further includes chemically reacting the passivated edges with a chemical compound. The method further includes forming a molecular brush at the passivated edges in response to the chemical reaction to define a second diameter that is less than the initial diameter of the at least one pore.Type: GrantFiled: August 14, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Ahmed A. Maarouf, Glenn J. Martyna
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Patent number: 8796024Abstract: A method for culturing neural cells using a culture medium is provided. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The culture medium includes a substrate and a carbon nanotube structure located on the substrate. A surface of the carbon nanotube structure is polarized to form a polar surface. The neural cells are cultured on the polar surface to grow neurites along the carbon nanotube wires. The carbon nanotube structure includes a number of carbon nanotube wires spaced apart from each other. A distance between adjacent carbon nanotube wires is greater than or equal to a diameter of the neural cell body.Type: GrantFiled: August 1, 2012Date of Patent: August 5, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Li Fan, Chen Feng, Wen-Mei Zhao
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Patent number: 8692716Abstract: A method of fabricating an antenna. In one embodiment, the method includes the steps of providing a substrate treated with a plasma treatment, providing a nanoparticle ink comprising nanoparticles, painting the nanoparticle ink on the substrate to form an antenna member in which the nanoparticles are connected, determining a feed point of the antenna member, and attaching an feeding port onto the substrate at the feed point to establish a contact between the feeding port and the antenna member.Type: GrantFiled: February 16, 2009Date of Patent: April 8, 2014Assignee: Board of Trustees of the University of ArkansasInventors: Alexandru S. Biris, Hussain Al-Rizzo, Taha Elwi, Daniel Rucker
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Publication number: 20130143769Abstract: A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene in a periodic way to create a graphene nanomesh with a patterned array of multiple holes, passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh, and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicants: EGYPT NANOTECHNOLOGY CENTER (EGNC), INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Shu-jen Han, Amal Kasry, Ahmed Maarouf, Glenn J. Martyna, Razvan Nistor, Hsinyu Tsai
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Patent number: 8443647Abstract: A multi-sensor as disclosed herein can include a substrate and at least three sensing elements disposed on the substrate. Each sensing element includes two electrodes separated by a distance and a nanowire mat adjacent to and in contact with the electrodes. The nanowire mats include nanowires which define a percolation network. The density of the nanowires in the nanowire mat of one sensing element is different than the density of the nanowires in the nanowire mat of either of the other at least two sensing elements.Type: GrantFiled: October 9, 2009Date of Patent: May 21, 2013Assignee: Southern Illinois UniversityInventors: Andrei Kolmakov, Victor V. Sysoev
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Patent number: 8357980Abstract: Various embodiments of the present invention are directed to photonic devices that can be used to collect and convert incident ER into surface plasmons that can be used to enhance the operation of microelectronic devices. In one embodiment of the present invention, a photonic device comprises a dielectric layer having a top surface and a bottom surface, and a planar nanowire network covering at least a portion of the top surface of the dielectric layer. The bottom surface of the dielectric layer is positioned on the top surface of a substrate, and the planar nanowire network is configured to convert incident electromagnetic radiation into surface plasmons that penetrate through the dielectric layer and into at least a portion of the substrate.Type: GrantFiled: October 15, 2007Date of Patent: January 22, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: R. Stanley Williams, David Fattal
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Patent number: 8232561Abstract: Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.Type: GrantFiled: September 10, 2008Date of Patent: July 31, 2012Assignee: University of Florida Research Foundation, Inc.Inventors: Andrew Gabriel Rinzler, Bo Liu, Mitchell Austin McCarthy, John Robert Reynolds, Franky So
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Patent number: 8173033Abstract: In a nano filter structure for breathing and a manufacturing method of the nano filter structure, a semiconductor process technology is used for manufacturing a nano filter structure comprising a top gate, a bottom gate, a plurality of sidewall gates and a plurality of supports. The sidewall gates include a plurality of filterable gratings, and the filterable gratings are controlled precisely to a nanoscale by a semiconductor process technology. Therefore, the nano filterable gratings can be manufactured easily and quickly, and the multilayer design of the filterable gratings enhances the aperture ratio of a filter material, such that users can inhale or exhale easily through the filter material.Type: GrantFiled: December 9, 2011Date of Patent: May 8, 2012Inventor: Shu-Yuan Chuang
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Patent number: 8168495Abstract: A technique of the invention reduces significantly the distance between the gate and single-walled carbon nanotubes to improve performance and efficiency of a carbon nanotube transistor device. Without using a porous template structure, single-walled carbon nanotubes are grown perpendicularly to a substrate between a base metal layer and a middle mesh layer. The nanotubes are insulated with a thin insulator and then gate regions are formed.Type: GrantFiled: December 28, 2007Date of Patent: May 1, 2012Assignee: Etamota CorporationInventors: Brian Y. Lim, Jon W. Lai
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Patent number: 7786467Abstract: Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed in three independent directions, and in which electronic components can be fabricated at junctions interconnected by internal signal lines. The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.Type: GrantFiled: April 25, 2005Date of Patent: August 31, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: R. Stanley Williams, Philip J. Kuekes
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Patent number: 7692952Abstract: Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further show how to generate different code permutations through random misalignment and how to promote uniform code probability selection.Type: GrantFiled: August 24, 2004Date of Patent: April 6, 2010Assignee: California Institute of TechnologyInventor: André DeHon
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Patent number: 7423285Abstract: The difficulty of miniaturization of large-scale integrated circuits in electric devices based on the conventional techniques involving three-dimensional device structures or the introduction of novel materials is solved. Wires 2 and 3 are disposed to intersect one another in midair in a matrix. The ends of the wires 2 and 3 in midair are designed to be in direct contact with the insides of a package which contains a semiconductor device so that electrical connection and/or physical support can be acquired. Cross point 1 where wires 2 and 3 are in contact with each other is a region which has current switching function similar to the function of a channel of a common MOSFET. Cross point 1 is a region where base wire 2 functioning as a substrate and gate electrode wire 3 functioning as a control electrode (gate electrode) intersect in contact with one another, or a region where base wire 2 and a lead wire 4 overlap.Type: GrantFiled: January 10, 2006Date of Patent: September 9, 2008Assignee: Sharp Kabushiki KaishaInventor: Hiroshi Ohki
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Patent number: 7416993Abstract: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric.Type: GrantFiled: September 8, 2004Date of Patent: August 26, 2008Assignee: Nantero, Inc.Inventors: Brent M. Segal, Thomas Rueckes, Claude L. Bertin