Abstract: A method for culturing neural cells using a culture medium is provided. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The culture medium includes a substrate and a carbon nanotube structure located on the substrate. A surface of the carbon nanotube structure is polarized to form a polar surface. The neural cells are cultured on the polar surface to grow neurites along the carbon nanotube wires. The carbon nanotube structure includes a number of carbon nanotube wires spaced apart from each other. A distance between adjacent carbon nanotube wires is greater than or equal to a diameter of the neural cell body.
Type:
Grant
Filed:
August 1, 2012
Date of Patent:
August 5, 2014
Assignees:
Tsinghua University, Hon Hai Precision Industry Co., Ltd.
Abstract: Disclosed herein are a method for synthesizing one-dimensional helical mesoporous structure, in which a self-assembled structure of a glycine-derived surfactant is used as a template at room temperature to synthesize the one-dimensional helical mesoporous silica structures having a uniform pore size and a method for synthesizing a glycine-derived surfactant for synthesizing the helical nanoporous structures, in which relatively expensive surfactant can be easily recovered using an organic solvent and reused, which provides economical and environment friendly effects and the glycine-derived surfactant is synthesized by homogeneously heating a reaction product of glycine and phthalic anhydride by dielectric heating with irradiation of microwave, whereby it is possible to realize high yield of the glycine-derived surfactant, shortened synthesis time and increase in energy efficiency, leading to improvement in productivity and reduction in production cost.
Type:
Grant
Filed:
April 10, 2009
Date of Patent:
May 7, 2013
Assignee:
Thermolon Korea Co., Ltd.
Inventors:
Sang Cheol Han, Yang Kim, Chung Kwon Park
Abstract: Method and apparatus for storing hydrogen. One embodiment of such a method comprises providing a storage apparatus having a substrate and a nanostructure mat on at least a portion of a side of the substrate. The nanostructure mat comprises a plurality of nanostructures having a surface ionization state which causes more than one layer of hydrogen to adsorb onto the nanostructures. The method can also include exposing the nanostructure mat to hydrogen such that more than one layer of hydrogen adsorbs onto the nanostructures.
Type:
Grant
Filed:
July 15, 2010
Date of Patent:
March 26, 2013
Assignees:
Washington State University Research Foundation, Idaho Research Foundation, Inc.
Abstract: Catalytic converters and insert materials for catalytic converters comprising metalized nanostructures coated on metal or ceramic honeycomb substrates are described. The nanostructures can be bonded directly to the channel walls of the metal or ceramic honeycomb substrates, and generally extend approximately 0.1 mm into the open pore volume of the substrates. The nanostructured coating can be used to support various catalyst formulations, where the nanostructured coating can provide advantages such as increasing reactivity of the catalysts by providing higher accessible surface area, decreasing light-off temperature through enabling smaller particle size of the catalysts, improving durability and lifetime of the catalysts through increased thermal stability, decreasing costs through reduced amounts of precious metals, and/or functioning as a filter for particulate matter.
Type:
Application
Filed:
October 5, 2012
Publication date:
February 7, 2013
Applicant:
GONANO TECHNOLOGIES, INC.
Inventors:
Timothy C. Cantrell, Giancarlo Corti, David N. McIlroy, Murray Grant Norton, Miles F. Beaux, II
Abstract: Various embodiments of the present invention are directed to photonic devices that can be used to collect and convert incident ER into surface plasmons that can be used to enhance the operation of microelectronic devices. In one embodiment of the present invention, a photonic device comprises a dielectric layer having a top surface and a bottom surface, and a planar nanowire network covering at least a portion of the top surface of the dielectric layer. The bottom surface of the dielectric layer is positioned on the top surface of a substrate, and the planar nanowire network is configured to convert incident electromagnetic radiation into surface plasmons that penetrate through the dielectric layer and into at least a portion of the substrate.
Type:
Grant
Filed:
October 15, 2007
Date of Patent:
January 22, 2013
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.
Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.
Type:
Grant
Filed:
October 5, 2007
Date of Patent:
October 25, 2011
Assignees:
Hitachi Chemical Co., Ltd., Hitachi Chemical Research Center, Inc.
Abstract: Disclosed herein are heterostructure semiconductor nanowires. The heterostructure semiconductor nanowires comprise semiconductor nanocrystal seeds and semiconductor nanocrystal wires grown in a selected direction from the surface of the semiconductor nanocrystal seeds wherein the semiconductor nanocrystal seeds have a composition different from that of the semiconductor nanocrystal wires. Further disclosed is a method for producing the heterostructure semiconductor nanowires.
Abstract: Provided are nano wires and a method of manufacturing the same. The method includes forming microgrooves having a plurality of microcavities, the microgrooves forming a regular pattern on a surface of a silicon substrate; forming a metal layer on the silicon substrate by depositing a material which acts as a catalyst to form nano wires on the silicon substrate; agglomerating the metal layer within the microgrooves on the surface of the silicon substrate by heating the metal layer to form catalysts; and growing the nano wires between the catalysts and the silicon substrate using a thermal process.