Including Etching/cutting Patents (Class 977/856)
  • Patent number: 8927988
    Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Hongbo Peng
  • Patent number: 8865268
    Abstract: A method and apparatus, the method including: forming a recess in a graphene layer wherein the recess creates a boundary between a first portion of the graphene layer and a second portion of the graphene layer; depositing electrically insulating material within the recess; and depositing an electrically conductive material over the insulating material.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: October 21, 2014
    Assignee: Nokia Corporation
    Inventors: Samiul Haque, Reijo K. Lehtiniemi, Asta M. Karkkainen, Lorenz Lechner, Pertti Hakonen
  • Patent number: 8858815
    Abstract: Nanofibers are formed using electrospray deposition from microfluidic source. The source is brought close to a surface, and scanned in one embodiment to form oriented or patterned fibers. In one embodiment, the surface has features, such as trenches on a silicon wafer. In further embodiments, the surface is rotated to form patterned nanofibers, such as polymer nanofibers. The nanofibers may be used as a mask to create features, and as a sacrificial layer to create nanochannels.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Harold G. Craighead, Jun Kameoka
  • Patent number: 8790863
    Abstract: In a method for imaging a solid state substrate, a vapor is condensed to an amorphous solid water condensate layer on a surface of a solid state substrate. Then an image of at least a portion of the substrate surface is produced by scanning an electron beam along the substrate surface through the water condensate layer. The water condensate layer integrity is maintained during electron beam scanning to prevent electron-beam contamination from reaching the substrate during electron beam scanning. Then one or more regions of the layer can be locally removed by directing an electron beam at the regions. A material layer can be deposited on top of the water condensate layer and any substrate surface exposed at the one or more regions, and the water condensate layer and regions of the material layer on top of the layer can be removed, leaving a patterned material layer on the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: President and Fellows of Harvard College
    Inventors: Daniel Branton, Anpan Han, Jene A. Golovchenko
  • Patent number: 8518829
    Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Hongbo Peng
  • Patent number: 8431034
    Abstract: The present invention relates to nanopore membranes, methods for manufacturing such nanopore membranes, and uses thereof. In the methods for manufacturing the membranes colloidal lithography is used, which results in production of nanosize pores in a short time and on a large scale. The nanopore membranes have a narrow size distribution and are randomly arranged. Furthermore, the inter-pore distance shows very little variation.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: April 30, 2013
    Inventors: Sarunas Petronis, Bengt Kasemo
  • Patent number: 8384069
    Abstract: A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Carole Pernel, Cécilia Dupre
  • Patent number: 8273257
    Abstract: In a method for processing a nanotube, a vapor is condensed to a solid condensate layer on a surface of the nanotube and then at least one selected region of the condensate layer is locally removed by directing a beam of energy at the selected region. The nanotube can be processed with at least a portion of the solid condensate layer maintained on the nanotube surface and thereafter the solid condensate layer removed. Nanotube processing can include, e.g., depositing a material layer on an exposed nanotube surface region where the condensate layer was removed. After forming a solid condensate layer, an electron beam can be directed at a selected region along a nanotube length corresponding to a location for cutting the nanotube, to locally remove the condensate layer at the region, and an ion beam can be directed at the selected region to cut the nanotube at the selected region.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 25, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A Golovchenko, Gavin M King, Gregor M Schurmann, Daniel Branton
  • Patent number: 8193095
    Abstract: A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silicon nanostructures in the etching area; immersing the silicon substrate in a second etching solution thereby resulting in the silicon nanostructures being side-etched and detached from the silicon substrate, thus forming the silicon trench.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: June 5, 2012
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Shih-Che Hung, Shu-Jia Syu
  • Patent number: 8192795
    Abstract: Lithographic and nanolithographic methods that involve patterning a first compound on a substrate surface, exposing non-patterned areas of the substrate surface to a second compound and removing the first compound while leaving the second compound intact. The resulting hole patterns can be used as templates for either chemical etching of the patterned area of the substrate or metal deposition on the patterned area of the substrate.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 5, 2012
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Khalid Salaita
  • Patent number: 8187673
    Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN, including submicrometer combinatorial arrays, and kits, devices and software for performing DPN. The invention further provides a method of performing AFM imaging in air.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 29, 2012
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
  • Patent number: 8093474
    Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: January 10, 2012
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Saleem Zaidi, Joseph W. Tringe, Ganesh Vanamu, Rajiv Prinja
  • Patent number: 8058089
    Abstract: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 15, 2011
    Assignee: Nantero Inc.
    Inventors: Brent M. Segal, Darren K. Brock, Thomas Rueckes
  • Patent number: 8029681
    Abstract: Provided are a master recording medium and a method of manufacturing the master recording medium. The master recording medium includes: a plate; and a magnetic layer which is formed on the plate for magnetically transferring of a servo pattern that is to be formed on a magnetic recording medium. The method of manufacturing a master recording medium includes: engraving a polymer layer by nano imprinting to form an engraved pattern corresponding to a servo pattern to be formed on a magnetic recording medium; forming a magnetic layer which fills in the engraved pattern of the polymer layer; forming a back plate layer on the magnetic layer; and performing processing to expose the servo pattern on a surface of the magnetic layer that is opposite a surface of the magnetic layer on which the back plate layer is formed.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-won Na, Sang-chul Sul, Du-hyun Lee, Myung-bok Lee, Hae-sung Kim, Jin-seung Sohn
  • Patent number: 8029851
    Abstract: Techniques for making nanowires with a desired diameter are provided. The nanowires can be grown from catalytic nanoparticles, wherein the nanowires can have substantially same diameter as the catalytic nanoparticles. Since the size or the diameter of the catalytic nanoparticles can be controlled in production of the nanoparticles, the diameter of the nanowires can be subsequently controlled as well. The catalytic nanoparticles are melted and provided with a gaseous precursor of the nanowires. When supersaturation of the catalytic nanoparticles with the gaseous precursor is reached, the gaseous precursor starts to solidify and form nanowires. The nanowires are separate from each other and not bind with each other to form a plurality of nanowires having the substantially uniform diameter.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: October 4, 2011
    Assignee: Korea University Research and Business Foundation
    Inventor: Kwangyeol Lee
  • Patent number: 7993538
    Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing a beam of energy at the selected regions. The structure can then be processed, with at least a portion of the patterned solid condensate layer on the structure surface, and then the solid condensate layer removed. Further there can be stimulated localized reaction between the solid condensate layer and the structure by directing a beam of energy at at least one selected region of the condensate layer.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: August 9, 2011
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Gavin M. King, Gregor M. Schurmann, Daniel Branton
  • Patent number: 7985686
    Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Kathryn Wilder Guarini
  • Patent number: 7887885
    Abstract: The invention provides methods of nanolithography and products therefor and produced thereby. In particular, the invention provides a nanolithographic method referred to as high force nanografting (HFN). HFN utilizes a tip (e.g., a scanning probe microscope (SPM) tip such as an atomic force microscope (AFM) tip) to pattern a substrate passivated with a resist. In the presence of a patterning compound, the tip is used to apply a high force to the substrate to remove molecules of the resist from the substrate, whereupon molecules of the patterning compound are able to attach to the substrate the form the desired pattern.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: February 15, 2011
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Peter V. Schwartz, James J. Storhoff, So-Jung Park
  • Patent number: 7863111
    Abstract: Provided are a thin film transistor for display devices and a manufacturing method of the thin film transistor. The thin film transistor for display devices includes: a flexible substrate; a gate electrode layer formed on the flexible substrate; a first insulating layer formed on the flexible substrate and the gate electrode; a source and a drain formed on the first insulating layer; an active layer formed on the first insulating layer between the source and the drain; a second insulating layer formed on the first insulating layer, the source, the drain, and the active layer; and a drain electrode that opens the second insulating layer to be connected to the drain and is formed of a CNT dispersed conductive polymer.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-seong Kim, Euk-che Hwang, Ki-deok Bae, Chang-seung Lee, Hyeon-Jin Shin
  • Patent number: 7790051
    Abstract: A method is disclosed for isolating single atoms of an atomic species of interest by locating the atoms within silicon nanocrystals. This can be done by implanting, on the average, a single atom of the atomic species of interest into each nanocrystal, and then measuring an electrical charge distribution on the nanocrystals with scanning capacitance microscopy (SCM) or electrostatic force microscopy (EFM) to identify and select those nanocrystals having exactly one atom of the atomic species of interest therein. The nanocrystals with the single atom of the atomic species of interest therein can be sorted and moved using an atomic force microscope (AFM) tip. The method is useful for forming nanoscale electronic and optical devices including quantum computers and single-photon light sources.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 7, 2010
    Assignee: Sandia Corporation
    Inventor: Malcolm S. Carroll
  • Patent number: 7737381
    Abstract: This invention relates to a method and apparatus for controlling the length of a carbon nanotube, in cooperation with a substrate having at least one reference level on a surface of the substrate on which at least one carbon nanotube is formed, comprising at least one positioning platform for mounting and calibrating the substrate; a discharging electrode mounted on one side of the positioning platform to cut the carbon nanotube wherein the position of the discharging electrode can be calibrated with the positioning platform; a piezoelectric actuator for calibrating the position of the discharging electrode or the height of the discharging electrode relative to the substrate reference level; a position sensor for detection of the height of the substrate; and a voltage pulse supplying means for applying a voltage pulse to the discharging electrode to cut the carbon nanotube.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: June 15, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hung-Ming Tai, Nang-Chian Shie, Tsan-Lin Chen
  • Patent number: 7674389
    Abstract: Methods of shape modifying a nanodevice by contacting it with a low-energy focused electron beam are disclosed here. In one embodiment, a nanodevice may be permanently reformed to a different geometry through an application of a deforming force and a low-energy focused electron beam. With the addition of an assist gas, material may be removed from the nanodevice through application of the low-energy focused electron beam. The independent methods of shape modification and material removal may be used either individually or simultaneously. Precision cuts with accuracies as high as 10 nm may be achieved through the use of precision low-energy Scanning Electron Microscope scan beams. These methods may be used in an automated system to produce nanodevices of very precise dimensions. These methods may be used to produce nanodevices of carbon-based, silicon-based, or other compositions by varying the assist gas.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: March 9, 2010
    Assignee: The Regents of the University of California
    Inventors: Alex Zettl, Thomas David Yuzvinsky, Adam Fennimore
  • Patent number: 7645625
    Abstract: The present invention provides a method for fine processing of a substrate, a method for fabrication of a substrate, and a light emitting device. In the method for fine processing of a substrate, after removing a single particle layer from the substrate having the single particle layer, a hole having an inner diameter smaller than a diameter of a particle and centering on a position on the substrate where each particle constructing the single particle layer has been placed is formed by etching.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: January 12, 2010
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yoshinobu Ono, Kenji Kasahara, Kazumasa Ueda
  • Patent number: 7544523
    Abstract: A method of batch fabrication using established photolithographic techniques allowing nanoparticles or nanodevices to be fabricated and mounted into a macroscopic device in a repeatable, reliable manner suitable for large-scale mass production. Nanoparticles can be grown on macroscopic “modules” which can be easily manipulated and shaped to fit standard mounts in various devices.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 9, 2009
    Assignee: FEI Company
    Inventors: Gregory Schwind, Gerald Magera, Lawrence Scipioni
  • Patent number: 7524431
    Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing a beam of energy at the selected regions, exposing the structure at the selected regions. A material layer is then deposited on top of the solid condensate layer and the exposed structure at the selected regions. Then the solid condensate layer and regions of the material layer that were deposited on the solid condensate layer are removed, leaving a patterned material layer on the structure.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 28, 2009
    Assignee: President and Fellows of Harvard College
    Inventors: Daniel Branton, Jene A. Golovchenko, Gavin M. King, Warren J. MoberlyChan, Gregor M. Schürmann
  • Patent number: 7501069
    Abstract: This invention provides free-standing structures, functionalized free-standing structures and functional devices that are flexible, including nano- and micromachined flexible fabrics comprising woven networks and mesh networks. The present invention provides processing methods for making and functionalizing flexible free-standing structures having a wide range of integrated materials, devices and device components. The methods of the present invention are capable of providing large area functional electronic, optoelectronic, fluidic, and electromechanical devices and device arrays which exhibit good device performance in stretched, bent and/or deformed configurations.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 10, 2009
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Chang Liu, Nannan Chen
  • Patent number: 7452432
    Abstract: Disclosed herein are an apparatus for and a method of bonding a nano-tip using electrochemical etching, in which a good bonding stability can be provided. The nano-tip bonding apparatus comprises a glass plate having a top surface of a certain desired area. An electrolytic solution having conductivity is placed on the top surface of the glass plate by means of surface tension. Means for moving reciprocally a base material having conductivity in opposite direction is provided. A carbon nano-tube is adhered to a pointed tip of the base material by means of an adhesive. An end portion of the carbon nano-tube is to be immersed in the electrolytic solution. A power supply is provided for applying an electric power to the electrolytic solution and the base material.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: November 18, 2008
    Assignee: Korean Advanced Institute of Science and Technology
    Inventors: Soo Hyun Kim, Jun Sok Lee, Jai Seong Choi, Gyung Soo Kang
  • Patent number: 7435353
    Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing a beam of energy at the selected regions. The structure can then be processed, with at least a portion of the patterned solid condensate layer on the structure surface, and then the solid condensate layer removed. Further there can be stimulated localized reaction between the solid condensate layer and the structure by directing a beam of energy at at least one selected region of the condensate layer.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: October 14, 2008
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Gavin M. King, Gregor M. Schürmann, Daniel Branton
  • Publication number: 20080230763
    Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Inventors: Saleem Zaidi, Joseph W. Tringe, Ganesh Vanamu, Rajiv Prinja
  • Patent number: 7422696
    Abstract: Multicomponent nanorods having segments with differing electronic and/or chemical properties are disclosed. The nanorods can be tailored with high precision to create controlled gaps within the nanorods or to produce diodes or resistors, based upon the identities of the components-making up the segments of the nanorods. Macrostructural composites of these nanorods also are disclosed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 9, 2008
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Lidong Qin, Sungho Park, Ling Huang, Sung-Wook Chung
  • Patent number: 7416993
    Abstract: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: August 26, 2008
    Assignee: Nantero, Inc.
    Inventors: Brent M. Segal, Thomas Rueckes, Claude L. Bertin
  • Patent number: 7375324
    Abstract: An improved method for rapidly and accurately modifying small structures, including structures on a micron or nanometer scale, suitable for the repair of defects in lithographic photo-masks and semiconductors on a nano-scopic level. Features or samples repaired may be conductive or non-conductive. A single instrument can be employed to both observe the surface of the mask or wafer, and to effectuate the repair of conductive and non-conductive features thereon. Using a Stylus-Nano-Profilometer probe, rapid lateral strokes across the sample surface in a definable pattern at known high applied pressure are used to effectuate defect repair. The tip of the probe can also be dithered rapidly in a pattern or used as to create a jackhammer effect to more effectively remove material from the sample surface.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: May 20, 2008
    Assignee: Fei Company
    Inventors: Robert Linder, Eric Kneedler
  • Patent number: 7253442
    Abstract: A thermal interface material (40) includes a macromolecular material (32), and a plurality of carbon nanotubes (22) embedded in the macromolecular material uniformly. The thermal interface material includes a first surface (42) and an opposite second surface (44). Each carbon nanotube is open at both ends thereof, and extends from the first surface to the second surface of the thermal interface material. A method for manufacturing the thermal interface material includes the steps of: (a) forming an array of carbon nanotubes on a substrate; (b) submerging the carbon nanotubes in a liquid macromolecular material; (c) solidifying the liquid macromolecular material; and (d) cutting the solidified liquid macromolecular material to obtain the thermal interface material with the carbon nanotubes secured therein.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: August 7, 2007
    Assignees: Tsing Hua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hua Huang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 7253119
    Abstract: A plurality of semiconductor nanoparticles having an elementally passivated surface are provided. These nanoparticles are capable of being suspended in water without substantial agglomeration and substantial precipitation on container surfaces for at least 30 days. The method of making the semiconductor nanoparticles includes reacting at least a first reactant and a second reactant in a solution to form the semiconductor nanoparticles in the solution. A first reactant provides a passivating element which binds to dangling bonds on a surface of the nanoparticles to passivate the surface of the nanoparticles. The nanoparticle size can be tuned by etching the nanoparticles located in the solution to a desired size.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: August 7, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventor: Partha Dutta
  • Patent number: 7151209
    Abstract: Nanostructure manufacturing methods and methods for assembling nanostructures into functional elements such as junctions, arrays and devices are provided. Systems for practicing the methods are also provided.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: December 19, 2006
    Assignee: Nanosys, Inc.
    Inventors: Stephen Empedocles, Larry Bock, Calvin Y. H. Chow, Xianfeng Duan, Chunming Niu, George Pontis, Vijendra Sahi, Linda T. Romano, David Stumbo