For Manufacture Of Nanostructure Patents (Class 977/855)
  • Patent number: 8999458
    Abstract: A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, Hendrik F. Hamann, Herschel M. Marchman, Robert J. Von Gutfeld
  • Patent number: 8871623
    Abstract: Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: October 28, 2014
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8865268
    Abstract: A method and apparatus, the method including: forming a recess in a graphene layer wherein the recess creates a boundary between a first portion of the graphene layer and a second portion of the graphene layer; depositing electrically insulating material within the recess; and depositing an electrically conductive material over the insulating material.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: October 21, 2014
    Assignee: Nokia Corporation
    Inventors: Samiul Haque, Reijo K. Lehtiniemi, Asta M. Karkkainen, Lorenz Lechner, Pertti Hakonen
  • Patent number: 8764681
    Abstract: Carbon nanotube needles and needle arrays are described in which the precursor pillars are etched by oxygen plasma treatment to provide tapered and/or sharp-tip needles. Processes, products by process, and devices incorporating the sharp-tip needles are further described.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: July 1, 2014
    Assignee: California Institute of Technology
    Inventors: Adrianus I. Aria, Bradley Lyon, Morteza Gharib
  • Patent number: 8735226
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 27, 2014
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8727112
    Abstract: Methods and articles of manufacture for storage and shipping of nanowires are disclosed. One disclosed method includes: (a) providing a nanowire suspension including nanowires suspended in a liquid; and (b) disposing the nanowire suspension in a container for storage and shipping, where the container is configured to inhibit agglomeration of nanowires from the nanowire suspension.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: May 20, 2014
    Assignee: Innova Dynamics, Inc.
    Inventors: Michael Eugene Young, Arjun Daniel Srinivas, Matthew R. Robinson
  • Patent number: 8689361
    Abstract: A probe for atomic force microscopy may be provided by depositing a thin film onto a wafer substrate and etching the substrate to leave the thin film behind in the form of a handle, a cantilever, and a probe tip in the cantilever. In some embodiments, a thin film substrate for the probe may be accomplished by forming the probe mold on a first wafer, bonding a second wafer onto the first wafer, and patterning out the second wafer to define the substrate for the probe on the first wafer. The thin film may be deposited onto the exposed portions of the first wafer. Thereafter, portions of the first and second wafers may be removed to leave behind the probe.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: April 1, 2014
    Assignee: Oicmicro, LLC
    Inventor: Salleh Ismail
  • Patent number: 8647957
    Abstract: A method for making semi-conductor nanocrystals, including at least the steps of: forming solid carbon chemical species on a semi-conductor thin layer provided on at least one dielectric layer, the dimensions and the density of the carbon chemical species formed on the semi-conductor thin layer being a function of the desired dimensions and density of the semi-conductor nanocrystals; annealing the semi-conductor thin layer, performing a dewetting of the semi-conductor and forming, on the dielectric layer, the semi-conductor nanocrystals.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: February 11, 2014
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, Centre National de la Recherche Scientifique
    Inventors: Lukasz Borowik, Jean-Charles Barbe, Ezra Bussmann, Fabien Cheynis, Frederic Leroy, Denis Mariolle, Pierre Muller
  • Patent number: 8641873
    Abstract: A method for synthesizing nano particles, including: moving material in a plasma generating space in a first direction; and synthesizing nano particles by cooling the material moved along the first direction, wherein the synthesizing the nano particles may be performed by cooling the material at gradually lower temperatures during the moving thereof in the first direction.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 4, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Soon Mo Song, Hyo Sub Kim, Gun Woo Kim, Sang Hyuk Kim, Sang Hoon Kwon, Kang Heon Hur
  • Patent number: 8641976
    Abstract: Disclosed herein is an apparatus for synthesizing nano particles. The apparatus for synthesizing nano particles is configured to include: a plasma generator that generates plasma; a recovery device that recovers the synthesized nano particles; and a cooler that is disposed between the plasma generator and the recovery device and includes a cooling path where the nano particles are synthesized, while material supplied from the plasma generator is cooled, wherein the cooling path is set to have lower cooling temperatures for each section as going to the moving direction of the nano particles.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 4, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Soon Mo Song, Hyo Sub Kim, Gun Woo Kim, Sang Hyuk Kim, Sang Hoon Kwon, Kang Heon Hur
  • Patent number: 8536015
    Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 17, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Schricker
  • Patent number: 8507390
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 13, 2013
    Assignee: Sandisk Corporation
    Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8507778
    Abstract: Self-assembling multimeric physical models of closed polyhedral structures made of structurally symmetric units, and which mimic the structure and self-assembly characteristics of naturally occurring systems such as viral capsids, are provided. Also provided are methods of creating structurally symmetric units, kits for forming self-assembling physical models of polyhedral structures, and methods of forming the same.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: August 13, 2013
    Inventor: Arthur J. Olson
  • Patent number: 8480946
    Abstract: An imprint method, in which pattern forming is performed by having a light curable material applied on a sample face of a substrate being a processing target hardened by being exposed to light in a state where the light curable material and a pattern formed surface of a template contact each other, the pattern formed surface having a concave-convex pattern formed thereon; wherein in one exposure performed with respect to a predetermined shot of the light curable material, an exposure amount at a light curable material on a first region which contacts a pattern formed region including the concave-convex pattern of the template is greater than an exposure amount at a light curable material on a second region which at least contacts a part of a pattern periphery region of the template, the pattern periphery region existing in a periphery of the pattern formed region of the template.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Mikami, Ikuo Yoneda
  • Patent number: 8384069
    Abstract: A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Carole Pernel, Cécilia Dupre
  • Patent number: 8349667
    Abstract: The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: January 8, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Thierry Poiroux
  • Patent number: 8227033
    Abstract: A method for applying membrane lipids to a substrate includes providing a substrate and an ink reservoir having an ink including a membrane lipid. The tip of a scanning probe microscope is dipped into the ink so as to dispose the membrane lipid on the tip. The tip of the scanning probe microscope is brought into contact with a surface of the substrate. The tip is moved over regions of the surface so that the membrane lipid migrates from the tip of the scanning probe microscope onto the surface of the substrate in the regions and the membrane lipid organizes itself in the regions in a form of a single lipid layer or in a form of one or a plurality of mutually superposed lipid bilayers. The tip is removed from the surface of the substrate.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 24, 2012
    Assignee: Forschungszentrum Karlsruhe GmbH
    Inventors: Steven Lenhert, Harald Fuchs
  • Patent number: 8192795
    Abstract: Lithographic and nanolithographic methods that involve patterning a first compound on a substrate surface, exposing non-patterned areas of the substrate surface to a second compound and removing the first compound while leaving the second compound intact. The resulting hole patterns can be used as templates for either chemical etching of the patterned area of the substrate or metal deposition on the patterned area of the substrate.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 5, 2012
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Khalid Salaita
  • Patent number: 8187673
    Abstract: The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN, including submicrometer combinatorial arrays, and kits, devices and software for performing DPN. The invention further provides a method of performing AFM imaging in air.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 29, 2012
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Richard Piner, Seunghun Hong
  • Patent number: 8178165
    Abstract: A long range, periodically ordered array of discrete nano-features (10), such as nano-islands, nano-particles, nano-wires, non-tubes, nano-pores, nano-composition-variations, and nano-device-components, are fabricated by propagation of a self-assembling array or nucleation and growth of periodically aligned nano-features. The propagation may be induced by a laterally or circularly moving heat source, a stationary heat source arranged at an edge of the material to be patterned (12), or a series of sequentially activated heaters or electrodes. Advantageously, the long-range periodic array of nano-features (10) may be utilized as a nano-mask or nano-implant master pattern for nano-fabrication of other nano-structures.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: May 15, 2012
    Assignee: The Regents of the University of California
    Inventor: Sungho Jin
  • Patent number: 8110476
    Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Shricker
  • Patent number: 8039380
    Abstract: The present invention relates to a process for producing a carbon nanotube (CNT) mat on a conductive or semiconductor substrate. According to this process, a catalytic complex comprising at least one metal layer is firstly deposited on said substrate. Said metal layer then undergoes an oxidizing treatment. Finally, carbon nanotubes are grown from the metal layer thus oxidized. The present invention also relates to a process for producing a via using said CNT mat production process.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: October 18, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean Dijon, Adeline Fournier
  • Patent number: 7998528
    Abstract: An all-additive method for direct fabrication of nanometer-scale planar and multilayer structures comprises the steps of acquiring a transferable material with a submillimeter-scale tip, depositing at least a portion of the acquired first transferable material at a predetermined location onto a substrate without a bridging medium, and repeating to create a structure using the transferable material.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 16, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Brian Hubert, Joseph Jacobson, Aggelos Bletsas
  • Publication number: 20110081526
    Abstract: The present invention includes a method of fabricating organic/inorganic composite nanostructures on a substrate comprising depositing a solution having a block copolymer and an inorganic precursor on the substrate using dip pen nanolithography. The nanostructures comprises arrays of lines and/or dots having widths/diameters less than 1 micron. The present invention also includes a device comprising an organic/inorganic composite nanoscale region chemically bonded to a substrate, wherein the nanoscale region, wherein the nanoscale region has a nanometer scale dimension other than height.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 7, 2011
    Inventors: Chad A. Mirkin, Vinayak P. Dravid, Ming Su, Xiaogang Liu
  • Patent number: 7919400
    Abstract: A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having a first impurity concentration within a vicinity of the surface region. In a specific embodiment, the method includes applying a driving force to one or more portions of at least the nanostructured material to cause the first region to form a second region having a second impurity concentration.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 5, 2011
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 7888271
    Abstract: A method for making silicon nano-structure, the method includes the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of catalyst separately into the reacting room. Thirdly, introducing a silicon-containing gas and hydrogen gas into the reacting room. Lastly, heating the reacting room to a temperature of 500˜1100° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: February 15, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 7862858
    Abstract: A resist medium in which features are lithographically produced by scanning a surface of the medium with an AFM probe positioned in contact therewith. The resist medium comprises a substrate; and a polymer resist layer within which features are produced by mechanical action of the probe. The polymer contains thermally reversible crosslinkages. Also disclosed are methods that generally includes scanning a surface of the polymer resist layer with an AFM probe positioned in contact with the resist layer, wherein heating the probe and a squashing-type mechanical action of the probe produces features in the layer by thermally reversing the crosslinkages.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michel Despont, Urs T. Duerig, Jane E. Frommer, Bernd W. Gotsmann, James L. Hedrick, Craig Jon Hawker, Robert D. Miller
  • Patent number: 7849424
    Abstract: Systems, devices, and methods for designing and/or manufacturing transparent conductors. A system is operable to evaluate optical and electrical manufacturing criteria for a transparent conductor. The system includes a database including stored reference transparent conductor data, and a controller subsystem configured to compare input acceptance manufacturing criteria for a transparent conductor to stored reference transparent conductor data.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: December 7, 2010
    Assignee: Cambrios Technologies Corporation
    Inventors: Jeffrey Wolk, Haixia Dai, Xina Quan, Michael A. Spaid
  • Patent number: 7811635
    Abstract: The present invention includes a method of fabricating organic/inorganic composite nanostructures on a substrate comprising depositing a solution having a block copolymer and an inorganic precursor on the substrate using dip pen nanolithography. The nanostructures comprises arrays of lines and/or dots having widths/diameters less than 1 micron. The present invention also includes a device comprising an organic/inorganic composite nanoscale region chemically bonded to a substrate, wherein the nanoscale region, wherein the nanoscale region has a nanometer scale dimension other than height.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: October 12, 2010
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Vinayak P. Dravid, Ming Su, Xiaogang Liu
  • Patent number: 7799291
    Abstract: An apparatus for fabricating ZnO nanostructures includes a heating element, a horizontal reaction tube having an inlet and an outlet. The reaction tube is positioned inside the interior cavity of the heating element with the inlet disposed to introduce a carrier gas into the reaction tube. The apparatus includes a source of a carrier gas in flow communication with the inlet, a container within the reaction tube that is disposed to receive and contain source materials comprising ZnO and graphite. An array of solid substrates is located on the container above the source materials. Adjacent substrates in the array are positioned with a space in between to allow the carrier gas to impinge on the source materials in the container.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: September 21, 2010
    Assignee: Korea Institute of Science and Technology
    Inventors: Jae-Hwan Park, Heon-Jin Choi, Jae-Gwan Park
  • Patent number: 7790051
    Abstract: A method is disclosed for isolating single atoms of an atomic species of interest by locating the atoms within silicon nanocrystals. This can be done by implanting, on the average, a single atom of the atomic species of interest into each nanocrystal, and then measuring an electrical charge distribution on the nanocrystals with scanning capacitance microscopy (SCM) or electrostatic force microscopy (EFM) to identify and select those nanocrystals having exactly one atom of the atomic species of interest therein. The nanocrystals with the single atom of the atomic species of interest therein can be sorted and moved using an atomic force microscope (AFM) tip. The method is useful for forming nanoscale electronic and optical devices including quantum computers and single-photon light sources.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 7, 2010
    Assignee: Sandia Corporation
    Inventor: Malcolm S. Carroll
  • Patent number: 7786402
    Abstract: A method and apparatus for assembly of small structures is disclosed. The present invention discloses electron beams created from one or more nanotips in an array operated in a field emission mode that can be controlled to apply heat to very well defined spots. The multiple electron beams may be generated and deflected and applied to electron beam heating and welding applications.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: August 31, 2010
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Richard Fink, Zvi Yaniv, Igor Pavlovsky, Leif Thuesen
  • Patent number: 7618599
    Abstract: Disclosed are a reaction chamber for manufacturing a carbon nanotube, an apparatus for manufacturing a carbon nanotube and a system for manufacturing a carbon nanotube. The reaction chamber includes a reaction furnace, a gas inlet, a gas outlet and a heat transfer member. The reaction furnace has a box structure for receiving a substrate wherein the reaction furnace provides a space for forming the carbon nanotube on the substrate. The gas inlet having a through-hole structure formed at a first portion of the reaction furnace and the gas outlet has a through-hole structure formed at a second portion of the reaction furnace. The heat transfer member has at least one rectangular through-hole structure formed at a third portion of the reaction furnace along a direction substantially in parallel to the substrate. The apparatus includes the reaction furnace, a gas supply member, a gas exhausting member and a heating member. The system includes the apparatus and a transfer apparatus.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: November 17, 2009
    Assignee: Semes Co., Ltd.
    Inventors: Sung-Soo Kim, Jong-Kwan Jeon
  • Patent number: 7575933
    Abstract: An electronic system for selectively detecting and identifying a plurality of chemical species, which comprises an array of nanostructure sensing devices, is disclosed. Within the array, there are at least two different selectivities for sensing among the nanostructure sensing devices. Methods for fabricating the electronic system are also disclosed. The methods involve modifying nanostructures within the devices to have different selectivity for sensing chemical species. Modification can involve chemical, electrochemical, and self-limiting point defect reactions. Reactants for these reactions can be supplied using a bath method or a chemical jet method. Methods for using the arrays of nanostructure sensing devices to detect and identify a plurality of chemical species are also provided.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: August 18, 2009
    Assignee: Nanomix, Inc.
    Inventors: Jean-Christophe P. Gabriel, Philip G. Collins, Keith Bradley, George Gruner
  • Patent number: 7541062
    Abstract: The present invention describes an apparatus for nanolithography and a process for thermally controlling the deposition of a solid organic “ink” from the tip of an atomic force microscope to a substrate. The invention may be used to turn deposition of the ink to the substrate on or off by either raising its temperature above or lowing its temperature below the ink's melting temperature. This process may be useful as it allows ink deposition to be turned on and off and the deposition rate to change without the tip breaking contact with the substrate. The same tip can then be used for imaging purposes without fear of contamination. This invention can allow ink to be deposited in a vacuum enclosure, and can also allow for greater spatial resolution as the inks used have lower surface mobilities once cooled than those used in other nanolithography methods.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 2, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Paul E. Sheehan, Lloyd J. Whitman, William P. King
  • Patent number: 7501315
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: March 10, 2009
    Assignee: Nanosys, Inc.
    Inventors: David L. Heald, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 7491425
    Abstract: A resist medium in which features are lithographically produced by scanning a surface of the medium with an AFM probe positioned in contact therewith. The resist medium comprises a substrate; and a polymer resist layer within which features are produced by mechanical action of the probe. The polymer contains thermally reversible crosslinkages. Also disclosed is a method that generally includes scanning a surface of the polymer resist layer with an AFM probe positioned in contact with the resist layer, wherein heating the probe and a squashing-type mechanical action of the probe produces features in the layer by thermally reversing the crosslinkages.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michel Despont, Urs T. Duerig, Jane E. Frommer, Bernd W. Gotsmann, James L. Hedrick, Craig Jon Hawker, Robert D. Miller
  • Patent number: 7462498
    Abstract: Substantially enhanced field emission properties are achieved by using a process of covering a non-adhesive material (for example, paper, foam sheet, or roller) over the surface of the CNTs, pressing the material using a certain force, and removing the material.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: December 9, 2008
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Dongsheng Mao, Richard Fink, Zvi Yaniv
  • Patent number: 7402736
    Abstract: A probe of a scanning probe microscope having a sharp tip and an increased electric characteristic by fabricating a planar type of field effect transistor and manufacturing a conductive carbon nanotube on the planar type field effect transistor. To achieve this, the present invention provides a method for fabricating a probe having a field effect transistor channel structure including fabricating a field effect transistor, making preparations for growing a carbon nanotube at a top portion of a gate electrode of the field effect transistor, and generating the carbon nanotube at the top portion of the gate electrode of the field effect transistor.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: July 22, 2008
    Assignee: POSTECH Foundation
    Inventors: Wonkyu Moon, Geunbae Lim, Sang Hoon Lee
  • Patent number: 7378654
    Abstract: A processing probe for repairing a defective portion in a sample has a cantilever and a probe separate and independent from the cantilever and integrally connected to an end portion of the cantilever for scratch-processing a defective portion of a sample. The cantilever and the probe are conductive for preventing the generation of electrostatic charges by friction of the probe against the sample during scratch-processing of the defective portion of the sample.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: May 27, 2008
    Assignee: SII NanoTechnology Inc.
    Inventors: Shigeru Wakiyama, Osamu Takaoka, Masatoshi Yasutake
  • Patent number: 7273636
    Abstract: The present invention includes a method of fabricating organic/inorganic composite nanostructures on a substrate comprising depositing a solution having a block copolymer and an inorganic precursor on the substrate using dip pen nanolithography. The process can comprise providing a substrate, providing a nanoscopic tip having an inking composition thereon, wherein the inking composition comprises at least one metal oxide precursor; and transferring the inking composition from the nanoscopic tip to the substrate to form a deposit on the substrate comprising at least one metal oxide precursor, and optionally further comprising the step of converting the metal oxide precursor on the substrate to form the metal oxide. The nanostructures comprises arrays of lines and/or dots having widths/diameters less than 1 micron.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 25, 2007
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Vinayak P. Dravid, Ming Su, Xiaogang Liu
  • Patent number: 7272511
    Abstract: Described herein are a molecular memory obtained using DNA strand molecular switches and carbon nanotubes, and a manufacturing method thereof. In particular, the nonvolatile memory is manufactured according to an architecture that envisages the use of carbon nanotubes as electrical connectors and DNA strands as physical means on which to write the information. In other words, the nonvolatile memory is made by means of a set of molecular DNA strand switches, the addressing of which is controlled by molecular wires made up of carbon nanotubes.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: September 18, 2007
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Luigi Occhipinti, Francesco Buonocore, Vincenzo Vinciguerra, Gianguido Rizzotto, Giuseppe Panzera, Floriana San Biagio, Francesco Italia
  • Patent number: 7253442
    Abstract: A thermal interface material (40) includes a macromolecular material (32), and a plurality of carbon nanotubes (22) embedded in the macromolecular material uniformly. The thermal interface material includes a first surface (42) and an opposite second surface (44). Each carbon nanotube is open at both ends thereof, and extends from the first surface to the second surface of the thermal interface material. A method for manufacturing the thermal interface material includes the steps of: (a) forming an array of carbon nanotubes on a substrate; (b) submerging the carbon nanotubes in a liquid macromolecular material; (c) solidifying the liquid macromolecular material; and (d) cutting the solidified liquid macromolecular material to obtain the thermal interface material with the carbon nanotubes secured therein.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: August 7, 2007
    Assignees: Tsing Hua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hua Huang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 7211143
    Abstract: Methods of fabricating uniform nanotubes are described in which nanotubes were synthesized as sheaths over nanowire templates, such as using a chemical vapor deposition process. For example, single-crystalline zinc oxide (ZnO) nanowires are utilized as templates over which gallium nitride (GaN) is epitaxially grown. The ZnO templates are then removed, such as by thermal reduction and evaporation. The completed single-crystalline GaN nanotubes preferably have inner diameters ranging from 30 nm to 200 nm, and wall thicknesses between 5 and 50 nm. Transmission electron microscopy studies show that the resultant nanotubes are single-crystalline with a wurtzite structure, and are oriented along the <001> direction. The present invention exemplifies single-crystalline nanotubes of materials with a non-layered crystal structure. Similar “epitaxial-casting” approaches could be used to produce arrays and single-crystalline nanotubes of other solid materials and semiconductors.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: May 1, 2007
    Assignee: The Regents of the University of California
    Inventors: Peidong Yang, Rongrui He, Joshua Goldberger, Rong Fan, Yi-Ying Wu, Deyu Li, Arun Majumdar
  • Patent number: 7180107
    Abstract: A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: February 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Joerg Appenzeller, Joachim Knoch