Search Patents
  • Efficient electromagnetic modeling of irregular metal planes
    Patent number: 7827514
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Grant
    Filed: September 3, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Beattie, Anirudh Devgan, Byron L. Krauter, Hui Zheng
  • Ring oscillator row circuit for evaluating memory cell performance
    Publication number: 20070086232
    Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan
  • INTERNALLY ASYMMETRIC METHOD FOR EVALUATING STATIC MEMORY CELL DYNAMIC STABILITY
    Publication number: 20070165471
    Abstract: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 19, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
  • Method for evaluating leakage effects on static memory cell access time
    Patent number: 7515491
    Abstract: A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: April 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
  • Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
    Patent number: 7558136
    Abstract: A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
  • INTERNALLY ASYMMETRIC METHODS AND CIRCUITS FOR EVALUATING STATIC MEMORY CELL DYNAMIC STABILITY
    Publication number: 20070291562
    Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Application
    Filed: August 14, 2007
    Publication date: December 20, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
  • Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions
    Publication number: 20060203581
    Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 14, 2006
    Inventors: Rajiv Joshi, Anirudh Devgan
  • RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE
    Publication number: 20080094878
    Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Application
    Filed: December 22, 2007
    Publication date: April 24, 2008
    Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan
  • Method for determining the leakage power for an integrated circuit
    Patent number: 6842714
    Abstract: A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Ying Liu, Sani R. Nassif, Haihua Su
  • Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
    Publication number: 20050044515
    Abstract: An integrated circuit design has circuit macros made up of device cells. The cells are characterized by determining the leakage current dependency on various process, environmental and voltage parameters. When circuit macros are designed their leakage power is calculated using this data and multi-dimensional models for power and temperature distribution. Circuit macros are identified as timing-critical and timing-noncritical macros. Statistical methods are used to determine the average leakage sensitivities for the specific circuit macros designed. The designer uses the sensitivity data to determine how to redesign selected circuit macros to reduce leakage power. Reducing leakage power in these selected circuits may be used to reduce overall IC power or the improved power margins may be used in timing-critical circuits to increase performance while keeping power dissipation unchanged.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 24, 2005
    Applicant: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Sani Nassif
  • Bitline variable methods and circuits for evaluating static memory cell dynamic stability
    Patent number: 7304895
    Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
  • Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
    Publication number: 20070058466
    Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
  • Efficient electromagnetic modeling of irregular metal planes
    Patent number: 7302661
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Beattie, Anirudh Devgan, Byron L. Krauter, Hui Zheng
  • coupled noise estimation method for on-chip interconnects
    Patent number: 6029117
    Abstract: An efficient method for identifying potential noise failures in an integrated circuit design by predicting peak noise within a victim circuit of an integrated circuit. Initially, a victim circuit within an integrated circuit is located. An aggressor circuit within the integrated circuit is located which has a physical relationship with the victim circuit, normally proximity. The slope of a signal within the aggressor circuit is analyzed and the coupling currents induced in the victim circuit by the aggressor circuit are computed. The input slope of the aggressor circuit and the physical relationship between the victim circuit and the aggressor circuit are utilized to determine a peak current induced into the victim circuit utilizing modelled coupling capacitance. The peak current and the equivalent impedance of the victim circuit can be utilized to determine peak noise. Noise failures on integrated circuits can be avoided by detecting peak noise which is above acceptable levels.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: February 22, 2000
    Assignee: International Business Machines Corporation
    Inventor: Anirudh Devgan
  • EFFICIENT METHOD AND COMPUTER PROGRAM FOR MODELING AND IMPROVING STATIC MEMORY PERFORMANCE ACROSS PROCESS VARIATIONS AND ENVIRONMENTAL CONDITIONS
    Publication number: 20080319717
    Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.
    Type: Application
    Filed: August 27, 2008
    Publication date: December 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Anirudh Devgan
  • Optimum buffer placement for noise avoidance
    Patent number: 6117182
    Abstract: A method for optimal insertion of buffers into an integrated circuit design. A model representative of a plurality of circuits is created where each circuit has a receiving node coupled to a conductor and a source. A receiving node is selected from the modeled plurality of circuits and circuit noise is calculated for the selected receiving node utilizing the circuit model. If the calculated circuit noise exceeds an acceptable value an optimum distance is computed from the receiving node on the conductor for buffer insertion. In a multi-sink circuit merging of the noise calculation for the two receiving circuits must be accomplished. If an intersection of conductors exists between the receiving node and the optimum distance a set of candidate buffer locations is generated. The method then prunes inferior solutions to provide an optimal insertion of buffers.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: September 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Stephen Thomas Quay, Anirudh Devgan
  • Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
    Patent number: 7137080
    Abstract: An integrated circuit design has circuit macros made up of device cells. The cells are characterized by determining the leakage current dependency on various process, environmental and voltage parameters. When circuit macros are designed their leakage power is calculated using this data and multi-dimensional models for power and temperature distribution. Circuit macros are identified as timing-critical and timing-noncritical macros. Statistical methods are used to determine the average leakage sensitivities for the specific circuit macros designed. The designer uses the sensitivity data to determine how to redesign selected circuit macros to reduce leakage power. Reducing leakage power in these selected circuits may be used to reduce overall IC power or the improved power margins may be used in timing-critical circuits to increase performance while keeping power dissipation unchanged.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Anirudh Devgan, Sani R. Nassif
  • Row circuit ring oscillator method for evaluating memory cell performance
    Patent number: 7376001
    Abstract: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan, Anirudh Devgan
  • Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
    Patent number: 6968306
    Abstract: A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceff is computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceff is characterized by: Ceff=Cfj(1?e?T/?dj) where Cfj is the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and ?dj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap
  • Internally asymmetric method for evaluating static memory cell dynamic stability
    Patent number: 7561483
    Abstract: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: July 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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