Abstract: The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.

Abstract: In some embodiments, the invention involves a method including segmenting an utterance into at least a first segment and a second segment, wherein a boundary between the first and second segments corresponds to a break in the utterance. The method further includes selecting potential hypothetical paths of potential words in the first and second segments that cross the boundary. The method also includes applying a language model to the potential hypothetical paths crossing to determine whether to merge the first and second segments and to apply decoding to the merged segments.

Abstract: In some embodiments, the invention includes a controller that has clock signal transmitters to transmit Clk signals and data signal transmitters to transmit Data signals. Multi-phase producing circuitry includes multiple taps to receive a clock signal and in response thereto to produce phases on the taps. Delay determining circuitry determines relative delays to be provided between the Clk signals and Data signals and to provide signals regarding the relative delays, and delay adjustment circuitry receives the signals regarding relative delays and select amongst the taps to achieve the relative delays between the Clk and Data signals. Other embodiments are described and claimed.

Abstract: One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

Abstract: In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

Abstract: A spatial footprint predictor includes a mechanism to measure spatial footprints of nominating cache-lines and hold the footprints. In some embodiments, the mechanism includes an active macro-block table (AMBT) to measure the spatial footprints and a spatial footprint table (SFT) to hold the spatial footprints. In other embodiments, the mechanism includes a macro-block table (MBT) in which macro-blocks may be active or inactive.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads. The processor also includes detection circuitry to detect speculation errors in the execution of the threads. In another embodiment, the processor includes thread management logic to control dynamic creation of threads from a program.

Abstract: In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.

Abstract: In some embodiments, the invention includes receiving a digital image including text and background. The method includes vector quantizing the digital image such that the digital image is divided into certain colors, and creating a text color histogram from a portion of the text and a first portion of the background. The method also includes creating at least one background color histogram from a second portion of the background, and creating a difference color histogram from a difference between the text color histogram and the at least one background color histogram, and wherein an estimated color of the text is derived from the difference color histogram. In other embodiments, the invention includes receiving a text object including bounding boxes of multiple frames of a video signal.

Abstract: In some embodiments, the invention includes a method for locating text in digital images. The method includes scaling a digital image into images of multiple resolutions and classifying whether pixels in the multiple resolutions are part of a text region. The method also includes integrating scales to create a scale integration saliency map and using the saliency map to create initial text bounding boxes through expanding the boxes from rectangles of pixels including at least one pixel to include groups of at least one pixel adjacent to the rectangles, wherein the groups have a particular relationship to a first threshold. The initial text bounding boxes are consolidated.

Abstract: In one embodiment of the invention, a processor includes a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

Abstract: A method and a system for implementing leaf node proxy in a network are disclosed. In one embodiment, a leaf node is switched to a standby state in response to a standby command. A leaf node self-identification (“self-ID”) packet is synthesized in response to leaf node information, which is stored in a parent node. The leaf node self-ID packet is transmitted from the parent node in response to a request.

Abstract: In some embodiments, the invention includes a method of compiling instructions of a program. The method includes receiving instructions for code motion and controlling the code motion while interacting with block ordering. The code motion may be done as part of various activities including instruction scheduling, partial redundancy elimination, and loop invariant removal. The scheduling may involve making an assessment of the cost of scheduling an instruction that takes into account generation and/or elimination of branches due to resulting block order update and determining whether to make the code motion based on the cost. Instruction scheduling may involve regeneration of predicate expressions to invert conditional branches.

Abstract: One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA).

Abstract: In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

Abstract: In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals.

Abstract: In some embodiments, a ring based multiprocessor system includes nodes in a ring, at least some of the nodes including network interface circuitry to transmit messages beginning at a first flit of multi-flit virtual slots. In some embodiments, a ring based multiprocessor system includes nodes in a ring at least some of the nodes including network interface circuitry to transmit messages in virtual slots between nodes. The interface circuitry includes control circuitry to determine whether to retain or release ownership of the virtual slots based on values in an insig buffer and an ownership history table.

Abstract: In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.

Abstract: In some embodiments, In some embodiments, the invention includes an electrical system having a functional unit block (FUB) including field effect transistors (FETs). A distributed forward body bias (FBB) voltage generation system provides at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant FBB. In some embodiments, the system includes a constant differential voltage generator and a distributed body bias generator to receive a set of differential signals from the constant differential voltage generator and provide at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant forward body bias. In some embodiments, the system includes multiple body bias generators coupled to corresponding FUBs receive a set of differential signals from a single constant differential voltage generator.

Abstract: In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node. In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes. In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.