Abstract: In one embodiment of the invention, an access point for use in a powerline based network includes first physical layer circuitry to interface with a powerline and second physical layer circuitry to interface with an antenna. The access point also includes circuitry to interface between the first and second physical layer circuitry. The first and second physical layer circuitry and the circuitry to interface between the first and second physical layer circuitry allow an untethered electrical device to have data communication through the powerline with an electrical device tethered to the powerline. Under another embodiment of the invention, a powerline based network includes a powerline and an access point connected to the powerline and capable of wireless communication.

Abstract: Under one aspect of the invention, the invention includes a multilayered substrate. The substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip. The substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip. The substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.

Abstract: In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations.

Abstract: In one embodiment, the present invention includes a method of storing and retrieving data. The method includes performing mutations of a cell array in a mutation cycle until a storage phase is reached. The data is stored in storage regions of the cell array at the storage phase. The cell array is mutated through additional phases and the data stored in the cell array during the storage phase and is encrypted by the mutations through the additional phases. In response to a retrieval request, mutations continue until a retrieval phase is reached and the data is decrypted. In various embodiments, the invention includes a computer-readable medium, a binary structure, a system, and a method of creating a cell array.

Abstract: A microprocessor includes a register file that contains registers for storing pieces of data for use by execution units that receive the pieces of data through source ports. A bypass cache includes data registers into which pieces of data from the execution units are written. Data can be written to and read from the bypass cache in fewer clocks cycles than it can be written to and read from the register file. A content addressable memory array (CAM) includes address registers into which destination addresses are written which correspond to the pieces of data in the data registers. In the case of a particular piece of data, the particular data register into which the piece of data is written and the particular address register into which the corresponding destination address is written is controlled by the position of a write pointer provided by a rotating write pointer unit. The CAM includes a comparators that compare the destination address with a source address.

Abstract: The present invention includes a computer system having an on-processor predictor tag array, an off-processor cache memory, and comparison circuitry. The on-processor predictor tag array contains first portions of tag information for multiple ways and multiple sets. The off-processor cache memory includes memory locations to store data and second portions of tag information. The comparison circuitry makes a first comparison of a first portion of an address with the first portions of tag information for the ways of one of the sets and uses results of the first comparison in predicting which of the ways, if any, correspond to the address. The comparison circuitry also makes a second comparison of the second portion of the address with sections of the second portions of tag information identified by the predicted way and the address.

Abstract: In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals.

Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.

Abstract: The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal and a data signal responsive to the clocking signal. A receiving component receives the strobe signal and data signal. The receiving component includes delay circuitry to delay the strobe signal so as to position edges of the strobe signal with respect to data cells of the data signal. The delay circuitry includes a loaded delay elements and DC level restoration circuitry to control the load of the loaded delay element. The delay elements may be a series of inverters loaded with RC loads. The DC level restoration circuitry may be pulse generation circuitry.

Abstract: A video monitor color control system including means for calibrating the intensity response of CRT phosphor sets to each of a plurality of electron gun control levels. Provided is a processor (24) that generates a sequence of discrete DAC signals, each DAC signal identifying an electron gun and a DAC value for driving the electron gun at a selected control level. Also provided is a monitor driver (22) connected to the processor (24) and to the monitor (20) and controllable in response to a DAC signal for driving the electron gun identified by the DAC signal at the control level identified by the DAC signal. The driven electron gun excites the associated phosphor set. A sensor (28) is provided for detecting the luminous intensity level of the phosphor excited by the electron gun, and for converting the detected intensity into a representative signal.

Abstract: A FRU assembly (10) comprises a melt chamber (20) including multiple subchambers (30) in which sticks of phase change ink (38, 40) are inserted and melted. Melted ink flows through apertures (54) to a reservoir (28) comprising multiple compartments (56). Each compartment contains a channel (90) and a siphon plate (114) that allow a siphon action that siphons melted ink in the compartments to an orifice (100) that leads to an ink jet print head (16). Heaters (52, 82, and 142) under the control of a CPU (154) melt the ink and keep the melted ink at a desired temperature during various modes of operation.

Abstract: A drop-on-demand ink jet has an ink chamber coupled to a source of ink, and an ink drop orifice with an outlet. An acoustic driver produces a pressure wave in the ink and causes the ink to pass outwardly through the ink drop orifice and outlet. The driver is driven with bipolar drive pulses having a refill pulse component and an eject pulse component of a polarity which is opposite to the refull pulse component. The refill and eject pulse components are separated by a wait period. The drive pulses may be adjusted to minimize their energy content at a frequency corresponding to the dominant acoustic resonance frequency of the ink jet. This will accelerate drop breakoff, optimize drop shape and minimize drop speed variations over the range of drop printing rates. The ink jet printer of the present invention may be used to print with a wide variety of inks, including phase change inks to achieve high print quality at high print rates.

Abstract: A drop-on-demand ink jet print head (9) has an ink pressure chamber (22) coupled to a source of ink (11) and an ink drop ejecting orifice (103) with an ink drop ejection orifice outlet (14). An acoustic driver (36), in response to a driver signal (100), produces a pressure wave in the ink and causes the ink to pass outwardly through the ink drop ejecting orifice (103) and the ink jet ejection orifice outlet (14) of the ink jet print head (9). In accordance with the present invention, controlling the operation of the ink jet print head (9) with a particular drive signal reduces print quality degradation resulting from rectified diffusion, which is the growth of air bubbles dissolved in the ink from the repeated application of pressure pulses to the ink residing within the ink pressure chamber (22) of the ink jet print head (9), such pressure pulses causing the application of pressures below ambient pressure.

Abstract: A drop-on-demand ink jet has an ink chamber coupled to a source of ink, and an ink drop orifice with an outlet. An acoustic driver produces a pressure wave in the ink and causes the ink to pass outwardly through the ink drop orifice and outlet. The size of the ink drops may be varied, such as by driving the acoustic driver with varying drive signals, preferably comprising individual or combinations of plural bipolar drive pulses. The ink jet printer of the present invention may be used to print with a wide variety of inks, including phase change inks.

Abstract: An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q.sub.0, Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier having an open loop gain, A.sub.v, which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i.sub..delta., in any one of the currents. The adjustment substantially cancels i.sub..delta. and thereby substantially reduces the presence of i.sub..delta. in the output current. The presence of i.sub..delta. in the output signal is substantially equal to i.sub..delta. /(1+A.sub.v).

Abstract: A DAC includes a simple width-scaled weighted array (104) of N number of current sources and a weighted cascode current divider (108) comprised of m number of current sources. The simple width-scaled weighted array conducts N first scaled currents (I.sub.0 -I.sub.3), the array including N first transistors (116a-116d) connected to different ones of N second transistors (112a-112d), one of the N second transistors (112d) having a gate width w. The weighted cascode current divider includes M current sources, the current divider including M third transistors (120a-120d) that conduct M second scaled currents (I.sub.4 -I.sub.7) which are summed at a node (134). The node is connected to a master current transistor (138) that conducts a current I.sub.S and has a gate width w.

Abstract: A regenerative comparator with a differential amplifier pair of transistors (Q.sub.1D, Q.sub.1E, Q.sub.2D, and Q.sub.2E) and a differential regenerative pair of transistors (Q.sub.3D, Q.sub.3E, Q.sub.4D, and Q.sub.4E), utilizes one or more of the following three techniques to reduce hysteresis by reducing the amount of charge storage in transistors. First, the transistors are arranged in a bootstrap cascode configuration having a depletion mode device (Q.sub.D) and an enhancement mode device (Q.sub.E). Second, a differential amplifier pair source-coupling implementation (D.sub.1 -D.sub.4, Q.sub.5A -Q.sub.5C, and Q.sub.6A -Q.sub.6C) allows current to flow through the transistors of the differential amplifier pair and differential regenerative pair independent of whether current is flowing through the branch (52 or 4) that connects the emitters or sources of the enhancement devices of the amplifier pair and regenerative pair. Third, the comparator includes keep-alive current sources (Q.sub.KA1 -Q.sub.