Abstract: An operational amplifier that may be fabricated on an integrated circuit is disclosed. Three precision emitter followers and four additional transistors comprise the major components of the op-amp. Two of the precision emitter followers are connected to the inverting and non-inverting inputs of the op-amp, respectively. The outputs of these two precision emitter followers are connected together to form a differential pair of precision emitter followers. Four additional transistors are used to convert the differential output of the precision emitter follower differential pair to a single-ended output and to provide gain. Two of the four additional transistors are used to mirror the currents in the drive transistors of the differential pair of precision emitter followers. These two mirrored currents are then fed to the drive and sense transistors of a current mirror respectively to convert the differential currents into a single-ended voltage.

Abstract: A pen like computer pointing device images as an array of pixels the spatial features of generally any micro textured or micro detailed work surface below the tip of the pen. The photo detector responses are digitized and stored as a frame into memory. Motion produces successive frames of translated patterns of pixel information, which are compared by autocorrelation to ascertain the direction and amount of movement. A contact sensor senses when the tip of the pointing device is in contact with the work surface. Buttons are included on the body of the pointing device that allow it to function in place of a computer mouse device.

Abstract: The dependancies of a computer service are modeled. The modeling hierarchically defines the relationships between the computer service and the hardware and software services which the computer service depends. These relationships may be contained in data structures defining a directed acyclic graph. The model also defines which measurements need to be taken to determine health and performance of the computer service and the health and performance of all the computer services upon which the computer service depends. Software agents that take these measurements may be deployed using the model to determine the measurement locations and functions. Data from measurement agents may be propagated up the model hierarchy. The model may also be visualized by a graphical interface to communicate the dependancies and the health and status of the services upon which the modeled service depends.

Abstract: User commands and command parameters in a graphical user interface are logged in a command log. Repeating patterns of commands and command parameters are automatically detected. This detection is invisible to the user. The user is then prompted to see if a shortcut script should be created for a given repeating pattern of commands and command parameters that has been detected. If the user responds affirmatively, a shortcut script is created that will execute that repeating pattern of commands and command parameters. The user may also be given the option of editing the commands and command parameters before they are made into a shortcut script.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Reflections on bus stubs are reduced by sensing when transition occurs on the bus. When a transition is detected, an impedance matched clamp device is activated that clamps the signal to the new (post-transition) voltage for a short period of time. This clamping action reduces the energy in the reflected wave which reduces the ability of the reflected wave to change the voltage on the bus. A receiver detects when a transition occurs on the bus. The output of the receiver is coupled to a delay device. Logic gates combine the output of the delay device with the output of the receiver to produce two pulsed outputs. One pulsed output is pulsed in response to a low-to-high transition on the bus, the other pulsed output is pulsed in response to a high-to-low transition on the bus. These pulsed outputs control the clamp devices so that the clamp devices are only turned on for a short period of time.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: A switching power supply that uses the intrinsic series resistance of an output bypass capacitor to sense changes in current flow through a switch that is connects between the input and output of the switching power supply. When the switch runs on, current flows from the input to the output and through a bypass capacitor. The intrinsic series resistance of the bypass capacitor develops a voltage across it as current flows through the capacitor. This voltage is used by a sense circuit to help determine when to shut off the switch. A low-cost regulator develops an output voltage that is divided and compared to a reference to determine if the input voltage is sufficient. If it is not, the power supply is not allowed to operate and the switch is not allowed to turn on.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: A circuit and method for detecting when converting a number from a floating point format to a fixed point format will result in a loss of precision. All bits but the most significant bit of the exponent of the floating point number are inverted. This results in a transformed exponent that is input to a comparator. The mantissa of the floating point number is input to a signed trailing one detector (STOD). The STOD outputs a signed number that indicates the bit position of the least significant logical "1" in the mantissa, plus a bias number. The bias number is chosen to be the number of bits in the fractional part of the fixed point format minus the number of bits in the mantissa. The output of the STOD is input to the other input of the comparator. The output of the comparator indicates whether or not a loss of precision occurs.

Abstract: The phase of an acquisition clock for a digital oscilloscope is modulated by summing an offset voltage with the output of the phase detector of a phase lock loop. The offset voltage is generated by a digital-to-analog converter which is fed input values by a microprocessor running a number generator routine.

Abstract: A circuit for reducing capacitive coupling between a culprit and a victim signal line is provided which comprises two inverters, a n-channel FET connected as a capacitor, and a p-channel FET connected as a capacitor. The input of both inverters are connected to the culprit line. The first inverter is designed to respond to high-to-low transition on the culprit line more rapidly than a low-to-high transition. The output of the first inverter is connected to the drain and source of the n-channel FET. The gate of the n-channel FET is connected to the victim line. The second inverter is designed to respond to low-to-high transition on the culprit line more rapidly than a high-to-low transition. The output of the second inverter is connected to the drain and source of the p-channel FET. The gate of the p-channel FET is connected to the victim line.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: The phase of an acquisition clock for a digital oscilloscope is modulated by summing an offset voltage with the output of the phase detector of a delay lock loop. The offset voltage is generated by a digital-to-analog converter which is fed input values by a microprocessor running a number generator routine.

Abstract: A thermal interface 26 between a heat source (e.g., an IC die) 24 and a heat sink 28 comprises a metallic mesh (26a) filled with a thermally conductive semi-liquid substance (26b). The thermally conductive semi-liquid substance may comprise, e.g., silicone grease or paraffin. The wire mesh may comprise silver, copper and/or gold cloth.