Abstract: A system and method for reducing non-repeatable positioning errors. Non-repeatable positioning errors caused by the effects stiction and backlash in the mechanical system are reduced by "shaking" or vibrating the positioning system in a controlled manner. After the system input is set to the desired value, the positioning system is "shaken" by inputting a series of offsets that oscillate around the desired location and gradually decrease in amplitude, eventually reaching zero. In a specific embodiment, a lead screw is threaded through a follower nut which is connected to a magnetic tape read/write head. The lead screw is rotated by a mechanical transmission which provides gear reduction from a computer controlled stepper motor. The tape head's non-repeatable positioning error is reduced by alternately stepping the stepper motor in opposite directions a specified number of steps and periodically reducing the specified number of steps until zero is eventually reached.

Abstract: In a test instrument, display locking is reduced by the addition of a non-constant time delay to each acquisition cycle. The time delay may be randomly chosen or follow a predetermined algorithm. Decreased system throughput caused by the addition of a non-constant time delay may be minimized by alternately storing acquired data in two acquisition memories. Display locking may also be reduced by rejecting selected triggers. The data acquired from these selected triggers is not processed for display. The triggers whose data is not processed for display may be randomly chosen or they may be chosen by a predetermined algorithm. Rejecting triggers and the addition of a non-constant time delay may be used in combination or individually to reduce display locking.

Abstract: The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

Abstract: An ESD protection system for protecting a CMOS integrated circuit (IC) with multiple power supplies is provided. The ESD protection system uses on-chip diodes to route ESD current from a first IC pin to the main positive power supply, where it is partly absorbed by the parasitic capacitance between the positive supply and ground. A charge sharing diode is provided between the main power supply and the clean power supply networks so that more of the ESD current may be absorbed by the parasitic capacitance between the clean power supply networks and ground. A core shunt circuit, which turns on when an ESD event is sensed, is provided to directly shunt ESD current from the positive supply to ground. Another diode is used to route current from the ground network out a second IC pin.

Abstract: A shift register is clocked by propagating two clock networks in opposite directions: one from input towards the output, the other from the output towards the input. The parasitic delays at the end of these networks are picked to be approximately equal. An extra latch is added to the shift register where the two clock networks meet to prevent a race condition. Both clock networks consist of non-overlapping clocks. Non-overlapping clock generator circuits are used to restore the non-overlap of the clocks when parasitic effects start to cause clock overlap as the clocks are propagated over long distances. An extra latch in the shift register at the non-overlapping clock generators prevents the delay of the non-overlapping clock generator from causing a race condition.

Abstract: Small voltage changes on a highly capacitive signal are sensed rapidly by placing a shielding impedance between the signal to be sensed and the input to a regenerative sense circuit. A regenerative sense circuit has a sense amplifier which controls a switching means that is connected to the input to the sense amplifier. When the output of the sense amplifier reaches a threshold value, it turns the switching means on. This switching means increases the rate of change on the input to the sense amplifier which causes the switching means to turn on even more. The input and output of the sense amplifier are able to switch more rapidly because the shielding impedance allows the switching means to change the state of the input to the sense amplifier without having to completely change the voltage level on the highly capacitive input signal. A small voltage difference between two signals is sensed by two cross-coupled, actively loaded, NMOS inverters.

Abstract: Small voltage changes on a highly capacitive signal are sensed rapidly by placing a shielding impedance between the signal to be sensed and the input to a regenerative sense circuit. A regenerative sense circuit has a sense amplifier which controls a switching means that is connected to the input to the sense amplifier. When the output of the sense amplifier reaches a threshold value, it turns the switching means on. This switching means increases the rate of change on the input to the sense amplifier which causes the switching means to turn on even more. The input and output of the sense amplifier are able to switch more rapidly because the shielding impedance allows the switching means to change the state of the input to the sense amplifier without having to completely change the voltage level on the highly capacitive input signal. A small voltage difference between two signals is sensed by two cross-coupled, actively loaded, NMOS inverters.