Abstract: As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.

Abstract: A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and only partially over the current-conducting member to expose a contact portion of the member. A first contact via is provided in conductive communication with the contact portion of the member, the first contact via having a self-aligned silicide-containing region. A second contact via is provided in conductive communication with the second portion of the semiconductor device region, the second contact via extending through the first film.

Abstract: A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch stop layer includes a layer of dielectric material overlying the intrinsic base, the opened etch stop layer self-aligned to the emitter. The bipolar transistor further includes a raised extrinsic base self-aligned to the emitter, the raised extrinsic base overlying the intrinsic base layer.

Abstract: A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.

Abstract: An ECC based system and method within an integrated circuit memory for self-repair of a failed memory element is disclosed. The method includes processing, within the integrated circuit, data and check bits retrieved from addressed memory locations therein. The locations of memory failures are automatically recorded within the integrated circuit. Logic circuits within the integrated circuit automatically identify failure patterns based on the locations. Based on the identified failure patterns, logic circuits within the integrated circuit then permanently replace a failed memory element with an appropriate redundancy element, using devices such as electronic fuse or antifuse. In this manner, the integrated circuit automatically identifies and effects self repair of a failed memory element therein.

Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

Abstract: A method is provided for defining spacings between the gates of field effect transistors (FETs) of an integrated circuit and the source and drain regions thereof, the spacings differing in width between a first FET and a second FET. The method includes forming gate stacks of the integrated circuit over a substrate, and forming first spacers on sidewalls of the gate stacks. Second spacers are then formed over the first spacers. Thereafter, source and drain regions of the first FET are formed in alignment with the second spacers of a first gate stack of the gate stacks. The second spacers are then removed from the first spacers of the gate stacks. Thereafter, the first spacers of a second gate stack are anisotropically etched in a substantially vertical direction to remove horizontally extending portions of the first spacers, and source and drain regions of the second FET are formed in alignment with portions of the first spacers of the first gate stack which remain after the etching.

Abstract: A method of making a buried plate region in a semiconductor substrate is provided. A trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A liner is formed along at least a portion of the trench sidewall, and thereafter, a dopant source layer is formed over the liner along the lower portion of the trench sidewall. The semiconductor substrate is then annealed to drive a dopant into the semiconductor substrate adjacent to the lower portion of the trench sidewall, while preventing the dopant from being driven into the semiconductor substrate adjacent to the upper portion of the trench sidewall.

Abstract: A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semiconductive layers, such that the raised extrinsic base is self-aligned to the emitter.

Abstract: A bipolar transistor is provided which includes a collector region, an intrinsic base layer including a single-crystal semiconductor overlying the collector region, and an emitter disposed within a first opening overlying the intrinsic base layer. The bipolar transistor includes a raised extrinsic base, which in turn includes a raised extrinsic base layer and a link-up region which electrically connects the raised extrinsic base layer to the intrinsic base layer. The link-up region also self-aligns the raised extrinsic base to the emitter. The link-up region is disposed in a second opening separate from the first opening and in an undercut region extending from the second opening below the raised extrinsic base layer.

Abstract: A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.

Abstract: A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

Abstract: Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto.

Abstract: A structure and method are provided for fabricating a field effect transistor (FET) having a metal gate structure. A metal gate structure is formed in an opening within a dielectric region formerly occupied by a sacrificial gate. The metal gate structure includes a first layer contacting a gate dielectric formed over a semiconductor region of a substrate. The first layer includes a material selected from the group consisting of metals and metal compounds. The gate further includes a silicide formed over the first layer. The FET further includes a source region and a drain region formed on opposite sides of the gate, the source and drain regions being silicided after the first layer of the gate is formed.

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract: An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

Abstract: As disclosed herein, systems and methods are provided for generating and distributing a plurality of reference currents on an integrated circuit. In a particular embodiment, an integrated circuit is disclosed which includes a reference current generator adapted to generate a plurality of reference currents. Such circuit includes an operational amplifier coupled to receive, at a first polarity input, a reference voltage, and a first transistor Q1 having a biasing input coupled to an output of the operational amplifier. The first transistor also has an output coupled to a fixed potential through a first resistor R1, and the output of the first transistor Q1 is further coupled as feedback to a second polarity input of the operational amplifier. One or more second transistors Qi are provided in the circuit, each of which has a biasing input coupled to the output of the operational amplifier, and an output coupled to the fixed potential through a respective second resistor Ri.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.