Abstract: Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.

Abstract: An apparatus and method for detection of electromechanical and mechanical errors in an electron beam device is provided. First the existing subfield is divided into a gridlike structure where each grid can be considered a target. Then a plurality of target points are provided on each grid for measuring combined directional variances. The separated horizontal and vertical variances is also measured for each of the target points. This leads to the performance of a significance tests, based on the F statistic which we refer to as FHV, for horizontal and vertical values of each target points during which FSTITCH values are also obtained. The FSTITCH values are then compared for horizontal and vertical values and an error alert provided when there is a sufficiently large disparity between the separated FSTITCH values. In an alternate embodiment of the present invention, a three dimensional grid is also provided to be used in a similar manner.

Abstract: As disclosed herein, a system and method are provided for detection and measurement of noise on E beam tools and devices including a spectrum analyzer which looks at the different frequency components of the noise. The deflected electron beam from the tool is calibrated in a coarse and fine mode by scanning the beam over a grid-like calibration target. The position of where the bars are detected is compared to where they actually are, and the deflection can be calibrated so that it matches the grid. This invention can utilize a Fast Fourier Transform (FFT) of the time-ordered data which allows one to see peaks associated with noise.

Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Abstract: A high-quality diode is formed in an SOI process, using standard steps and implant doses that are used in the process for other devices such as a FET and a buried resistor; in particular using a buried resistor mask and implant to form one side of the diode, using the FET gate oxide to terminate the P-N junction, and using the FET gate to protect the junction from shorting during the silicide step.

Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

Abstract: Disclosed herein is a method of filling isolation trenches in a substrate. The method includes anisotropically etching trenches in a surface of a substrate and partially filling the trenches with a deposited oxide. As a consequence of the deposition, the oxide accumulates in mounds on the surface between trenches. The trenches are then filled with a supporting material of a highly flowable material such as anti-reflective coating (ARC), low-K dielectric, or a spin-on-polymer, or alternatively, a supporting material of polysilicon. A flattening process is then applied to lower the mound topography. The supporting material is then removed and the filling of the trenches with oxide is then continued. When polysilicon is used as the supporting material, the mounds are removed by wet etching prior to removing the polysilicon.

Abstract: The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.

Abstract: A multi-beam shaped-beam electron beam lithography system employs conventional lenses and magnetic deflectors, with an array of lithographically fabricated electrodes disposed about a central axis to simultaneously and independently deflect electron beams in beamlet exposure ranges separated transversely from one another within a subfield, so that subfields overlap.

Abstract: A stencil-scattering mask for e-beam lithography includes four complementary sub-field reticles, each of which is exposed with one fourth of the total dose. “Doughnut” stencil shapes have four different patterns of struts, so that an area that is blocked by a strut in one shape is exposed in three other shapes.

Abstract: A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract: A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.

Abstract: A method for preparing a computer memory cell for a data write operation thereto is disclosed. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices within the memory cell, and is connected at an opposite end to pull-down devices within the memory cell. The memory cell further has a pair of access transistors for selectively coupling the memory cell to a pair of complementary bitlines. In an exemplary embodiment, the method includes adjusting the voltage of the cell supply voltage source from a first voltage value to a second voltage value, the second voltage value being less than the first voltage value. The memory cell is then coupled to the pair of complementary bitlines, thereby facilitating the data write operation. Following the data write operation, the cell supply voltage is restored from the second voltage value back to the first voltage value.

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.

Abstract: A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.

Abstract: A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.

Abstract: An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier.