Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.

Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.

Abstract: A system and apparatus for wireless communications directly between a sender and a receiver using a sending unit and a receiving unit. The sending unit is formed as a glove having a pulse triggering mechanism. The glove is wearable by a user who is the source of a communications signal. The pulse triggering mechanism is motion activated by a finger tip to trigger an electrical signal transmitted wirelessly to the receiving unit. The receiving unit is in the form of a patch worn by a user that receives a tactile message for silent communications.

Abstract: The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater.

Abstract: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD?(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

Abstract: A segmented insulative device and related kit for insulating components of a thermal distribution system. The kit includes a sheet of segmented insulation formed by a composite layer of segmented, flexible, pre-sewn insulation that is easily cut to size in the field using scissors, utility knives or other simple, hand-held cutting devices. The kit also includes two-sided hook-and-loop straps as fasteners, also easily cut to length, using hand-held devices. The segmented insulation and the hook-and-loop straps are attached to one another in the field using a stapler or other hand-held attachment device. This provides an installation kit that an installer can use to provide a versatile insulation in the form of the assembled segmented insulative device. The segmented insulative device lends itself to quick customization on-site rather than requiring costly off-site manufacture or pre-assembly and subsequent quick installation on the pipe component requiring thermal installation.

Abstract: A segmented insulative device and related kit for insulating components of a thermal distribution system, and particularly chilled fluid systems. The kit includes a sheet of segmented insulation formed by a composite layer of segmented, flexible, pre-sewn insulation that is easily cut to size in the field using scissors, utility knives or other simple, hand-held cutting devices. The composite layer includes at least one outer layer of low permeance laminate devoid of stitching and adhered to the pre-sewn insulation. The kit also includes low permeance pressure-sensitive adhesive tape as fasteners, also easily cut to length, using hand-held devices. The low permeance laminate and the low permeance pressure-sensitive adhesive tape form a contiguous outer water vapor barrier free of stitching that would otherwise compromise low permeance. The segmented insulation and the fasteners are attached to one another in the field.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.