Abstract: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Abstract: A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.

Abstract: Correction of glitches output from a delta-sigma modulator is accomplished using an integer boundary crossing detector and a FIR filter. The detector monitors a portion of an input to the modulator. The detector recognizes a transition from an all 1's bit pattern to an all 0's bit pattern or vice versa as representative of potential for a glitch to be present on the output of the modulator. The detector responsively generates condition detection output. Receipt of such condition detection output triggers the generation of a correction signal by the filter. The correction signal is, at least substantially similar, in magnitude but opposite in sign from to the expected glitch at the output of the modulator. The correction signal is added to the output of the modulator to substantially eliminate the glitch.

Abstract: Apparatus and methods facilitating a distributed approach to performance and functionality testing of location-sensitive wireless data communication systems and equipment are described. A plurality of test units, geographically distributed at arbitrary points in a three-dimensional volume surround the system or equipment under test. Each test unit generates test stimuli and records responses from the device under test, and emulates the effects of changes in spatial location within an actual wireless network environment. A central controller co-ordinates the set of test units to ensure that they act as a logical whole, and enables testing to be performed in a repeatable manner in spite of the variations introduced by the location sensitive characteristics of wireless data communication networks. The central controller also maintains a user interface that provides a unified view of the complete test system, and a unified view of the behavior of the system or equipment under test.

Abstract: Apparatus and methods facilitating a distributed approach to measuring the RF propagation characteristics of an indoor area or region are described. Such measurements are particularly useful during the installation and management of indoor wireless data communication networks, such as Wireless Local Area Networks (WLANs). A plurality of sounder units may be geographically distributed at arbitrary points in a two-dimensional area surrounding the indoor area or region whose RF propagation characteristics are to be measured. These sounder units are linked to a central controller, which functions to control all of the sounder units as well as to maintain a user interface that provides a user with a display of the measured propagation characteristics of the region. Each sounder unit is capable of independently injecting RF stimulus signals with some desired radiation pattern into the region being measured, as well as recording received signals from which the RF propagation characteristics may be calculated.

Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.

Abstract: An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

Abstract: The present invention relates generally to computer software, and more specifically, to a method and system of making computer software resistant to tampering and reverse-engineering. Tampering refers to changing computer software in a manner that is against the wishes of the original author, and is distinct from obscurity techniques which do not change the underlieing data or control flow of a program. Broadly speaking, the method of the invention is to analyse the effectiveness of various encoding techniques by measuring the number of possible decodings corresponding to a given encoded world. This analysis gave rise to a number of new data flow encoding techniques including alternative mixed encoding (a combination of linear and residue number encoding), and multinomial encoding.

Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.

Abstract: An integrated spectral sensing engine featuring energy sources and detectors within a single package that includes sample interfacing optics and acquisition and processing electronics. The miniaturized sensor is optimized for specific laboratory and field-based measurements by integration into a handheld format. Design and fabrication components support high volume manufacturing. Spectral selectivity is provided by either continuous variable optical filters or filter matrix devices. The sensor's response covers the range from 200 nm to 25 ?m based on various solid-state detectors. The wavelength range can be extended by the use of filter-matrix devices. Measurement modes include transmittance/absorbance, turbidity (light scattering) and fluorescence (emission). On board data processing includes raw data acquisition, data massaging and the output of computed results. Sensor applications include water and environmental, food and beverage, chemical and petroleum, and medical analyses.

Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

Abstract: A method and apparatus (5) for simulating and analyzing industrial thermal processes, including industrial heat-treatment, processes, melting, solidification, quenching and the like, used in the manufacture of metals, alloys and metal matrix composite components. The apparatus (5) includes an optional environmental chamber (10) used for situations where testing room conditions are too hot or too cold and would thus interfere with operation of the apparatus (5) without such chamber (10). The apparatus (5) includes a multifunctional excitation coil (40) that serves the function of the omitted environmental chamber (10). The apparatus (5) also includes one or more high frequency resonant inverters (15) and a cooling means (20). The apparatus (5) integrates melting and thermal processing capabilities with a thermal analyzer and a control system.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.